153c81a8cSYingwei Zheng; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 253c81a8cSYingwei Zheng; RUN: llc < %s -mtriple=riscv64 | FileCheck %s 353c81a8cSYingwei Zheng 453c81a8cSYingwei Zhengdefine i16 @narrow_load(ptr %p1, ptr %p2) { 553c81a8cSYingwei Zheng; CHECK-LABEL: narrow_load: 653c81a8cSYingwei Zheng; CHECK: # %bb.0: # %entry 753c81a8cSYingwei Zheng; CHECK-NEXT: lhu a2, 0(a0) 853c81a8cSYingwei Zheng; CHECK-NEXT: lui a3, 2 953c81a8cSYingwei Zheng; CHECK-NEXT: lui a4, 16 10*9122c523SPengcheng Wang; CHECK-NEXT: addiw a3, a3, -1 1153c81a8cSYingwei Zheng; CHECK-NEXT: addi a4, a4, -1 12*9122c523SPengcheng Wang; CHECK-NEXT: xor a2, a2, a3 1353c81a8cSYingwei Zheng; CHECK-NEXT: xor a4, a3, a4 1453c81a8cSYingwei Zheng; CHECK-NEXT: or a2, a2, a4 1553c81a8cSYingwei Zheng; CHECK-NEXT: sw a2, 0(a1) 1653c81a8cSYingwei Zheng; CHECK-NEXT: lhu a0, 0(a0) 1753c81a8cSYingwei Zheng; CHECK-NEXT: and a0, a0, a3 1853c81a8cSYingwei Zheng; CHECK-NEXT: ret 1953c81a8cSYingwei Zhengentry: 2053c81a8cSYingwei Zheng %bf.load = load i16, ptr %p1, align 2 2153c81a8cSYingwei Zheng %bf.clear = and i16 %bf.load, 8191 2253c81a8cSYingwei Zheng %not = xor i16 %bf.clear, -1 2353c81a8cSYingwei Zheng %conv1 = zext i16 %not to i32 2453c81a8cSYingwei Zheng store i32 %conv1, ptr %p2, align 4 2553c81a8cSYingwei Zheng %bf.load2 = load i16, ptr %p1, align 2 2653c81a8cSYingwei Zheng %bf.clear3 = and i16 %bf.load2, 8191 2753c81a8cSYingwei Zheng ret i16 %bf.clear3 2853c81a8cSYingwei Zheng} 29