1309e41ddSSimon Pilgrim; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2309e41ddSSimon Pilgrim; RUN: llc < %s -mtriple=riscv32-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV32 3309e41ddSSimon Pilgrim; RUN: llc < %s -mtriple=riscv64-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV64 4309e41ddSSimon Pilgrim 5*8505c3b1SSimon Pilgrim; Don't fold freeze(assertsext(x)) -> assertsext(freeze(x)) 6309e41ddSSimon Pilgrimdefine i32 @PR66603(double %x) nounwind { 7309e41ddSSimon Pilgrim; RV32-LABEL: PR66603: 8309e41ddSSimon Pilgrim; RV32: # %bb.0: 9309e41ddSSimon Pilgrim; RV32-NEXT: fcvt.w.d a0, fa0, rtz 10*8505c3b1SSimon Pilgrim; RV32-NEXT: slli a0, a0, 24 11*8505c3b1SSimon Pilgrim; RV32-NEXT: srai a0, a0, 24 12309e41ddSSimon Pilgrim; RV32-NEXT: ret 13309e41ddSSimon Pilgrim; 14309e41ddSSimon Pilgrim; RV64-LABEL: PR66603: 15309e41ddSSimon Pilgrim; RV64: # %bb.0: 16309e41ddSSimon Pilgrim; RV64-NEXT: fcvt.l.d a0, fa0, rtz 17*8505c3b1SSimon Pilgrim; RV64-NEXT: slli a0, a0, 56 18*8505c3b1SSimon Pilgrim; RV64-NEXT: srai a0, a0, 56 19309e41ddSSimon Pilgrim; RV64-NEXT: ret 20309e41ddSSimon Pilgrim %as_i8 = fptosi double %x to i8 21309e41ddSSimon Pilgrim %frozen_i8 = freeze i8 %as_i8 22309e41ddSSimon Pilgrim %ext = sext i8 %frozen_i8 to i32 23309e41ddSSimon Pilgrim ret i32 %ext 24309e41ddSSimon Pilgrim} 25