xref: /llvm-project/llvm/test/CodeGen/RISCV/pr56110.ll (revision 9067070d91e9d8cdd8509ffa56a076f08a3d7281)
1314dbde1SCraig Topper; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2314dbde1SCraig Topper; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
3*9067070dSCraig Topper; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem | FileCheck %s
4314dbde1SCraig Topper
5314dbde1SCraig Topperdefine void @foo_set(ptr nocapture noundef %a, i32 noundef %v) {
6314dbde1SCraig Topper; CHECK-LABEL: foo_set:
7314dbde1SCraig Topper; CHECK:       # %bb.0: # %entry
8314dbde1SCraig Topper; CHECK-NEXT:    srli a2, a1, 8
9314dbde1SCraig Topper; CHECK-NEXT:    sb a1, 3(a0)
10314dbde1SCraig Topper; CHECK-NEXT:    sb a2, 4(a0)
11314dbde1SCraig Topper; CHECK-NEXT:    ret
12314dbde1SCraig Topperentry:
13314dbde1SCraig Topper  %bf.load = load i96, ptr %a, align 1
14314dbde1SCraig Topper  %0 = and i32 %v, 65535
15314dbde1SCraig Topper  %bf.value = zext i32 %0 to i96
16314dbde1SCraig Topper  %bf.shl = shl nuw nsw i96 %bf.value, 24
17314dbde1SCraig Topper  %bf.clear = and i96 %bf.load, -1099494850561
18314dbde1SCraig Topper  %bf.set = or i96 %bf.clear, %bf.shl
19314dbde1SCraig Topper  store i96 %bf.set, ptr %a, align 1
20314dbde1SCraig Topper  ret void
21314dbde1SCraig Topper}
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