13b786f2cSKerry McLaughlin; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2c31a8104SCraig Topper; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV32 3c31a8104SCraig Topper; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV64 43b786f2cSKerry McLaughlin 53b786f2cSKerry McLaughlin; FIXED WIDTH 63b786f2cSKerry McLaughlin 73b786f2cSKerry McLaughlindefine i16 @ctz_v4i32(<4 x i32> %a) { 83b786f2cSKerry McLaughlin; RV32-LABEL: ctz_v4i32: 93b786f2cSKerry McLaughlin; RV32: # %bb.0: 10c31a8104SCraig Topper; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 11c31a8104SCraig Topper; RV32-NEXT: vmsne.vi v0, v8, 0 12c31a8104SCraig Topper; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma 13c31a8104SCraig Topper; RV32-NEXT: vmv.v.i v8, 0 14c31a8104SCraig Topper; RV32-NEXT: vmerge.vim v8, v8, -1, v0 15c31a8104SCraig Topper; RV32-NEXT: vid.v v9 16c31a8104SCraig Topper; RV32-NEXT: vrsub.vi v9, v9, 4 17c31a8104SCraig Topper; RV32-NEXT: vand.vv v8, v8, v9 18c31a8104SCraig Topper; RV32-NEXT: vredmaxu.vs v8, v8, v8 19c31a8104SCraig Topper; RV32-NEXT: vmv.x.s a0, v8 203b786f2cSKerry McLaughlin; RV32-NEXT: li a1, 4 213b786f2cSKerry McLaughlin; RV32-NEXT: sub a1, a1, a0 223b786f2cSKerry McLaughlin; RV32-NEXT: andi a0, a1, 255 233b786f2cSKerry McLaughlin; RV32-NEXT: ret 243b786f2cSKerry McLaughlin; 253b786f2cSKerry McLaughlin; RV64-LABEL: ctz_v4i32: 263b786f2cSKerry McLaughlin; RV64: # %bb.0: 27c31a8104SCraig Topper; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma 28c31a8104SCraig Topper; RV64-NEXT: vmsne.vi v0, v8, 0 29c31a8104SCraig Topper; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma 30c31a8104SCraig Topper; RV64-NEXT: vmv.v.i v8, 0 31c31a8104SCraig Topper; RV64-NEXT: vmerge.vim v8, v8, -1, v0 32c31a8104SCraig Topper; RV64-NEXT: vid.v v9 33c31a8104SCraig Topper; RV64-NEXT: vrsub.vi v9, v9, 4 34c31a8104SCraig Topper; RV64-NEXT: vand.vv v8, v8, v9 35c31a8104SCraig Topper; RV64-NEXT: vredmaxu.vs v8, v8, v8 36c31a8104SCraig Topper; RV64-NEXT: vmv.x.s a0, v8 373b786f2cSKerry McLaughlin; RV64-NEXT: li a1, 4 383b786f2cSKerry McLaughlin; RV64-NEXT: subw a1, a1, a0 393b786f2cSKerry McLaughlin; RV64-NEXT: andi a0, a1, 255 403b786f2cSKerry McLaughlin; RV64-NEXT: ret 413b786f2cSKerry McLaughlin %res = call i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32> %a, i1 0) 423b786f2cSKerry McLaughlin ret i16 %res 433b786f2cSKerry McLaughlin} 443b786f2cSKerry McLaughlin 453b786f2cSKerry McLaughlin; ZERO IS POISON 463b786f2cSKerry McLaughlin 473b786f2cSKerry McLaughlindefine i32 @ctz_v2i1_poison(<2 x i1> %a) { 483b786f2cSKerry McLaughlin; RV32-LABEL: ctz_v2i1_poison: 493b786f2cSKerry McLaughlin; RV32: # %bb.0: 50c31a8104SCraig Topper; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 51*5b9af38aSCraig Topper; RV32-NEXT: vfirst.m a0, v0 523b786f2cSKerry McLaughlin; RV32-NEXT: ret 533b786f2cSKerry McLaughlin; 543b786f2cSKerry McLaughlin; RV64-LABEL: ctz_v2i1_poison: 553b786f2cSKerry McLaughlin; RV64: # %bb.0: 56c31a8104SCraig Topper; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 57*5b9af38aSCraig Topper; RV64-NEXT: vfirst.m a0, v0 583b786f2cSKerry McLaughlin; RV64-NEXT: ret 593b786f2cSKerry McLaughlin %res = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> %a, i1 1) 603b786f2cSKerry McLaughlin ret i32 %res 613b786f2cSKerry McLaughlin} 623b786f2cSKerry McLaughlin 633b786f2cSKerry McLaughlindeclare i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1>, i1) 643b786f2cSKerry McLaughlindeclare i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32>, i1) 65