1*23c0850dSBrandon Wu; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2*23c0850dSBrandon Wu; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \ 3*23c0850dSBrandon Wu; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK 4*23c0850dSBrandon Wu; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \ 5*23c0850dSBrandon Wu; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK 6*23c0850dSBrandon Wu 7*23c0850dSBrandon Wu; VCIX instructions can not reorder between each other. 8*23c0850dSBrandon Wudefine void @test_reorder(<vscale x 1 x i64> %vreg) { 9*23c0850dSBrandon Wu; CHECK-LABEL: test_reorder: 10*23c0850dSBrandon Wu; CHECK: # %bb.0: # %entry 11*23c0850dSBrandon Wu; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma 12*23c0850dSBrandon Wu; CHECK-NEXT: sf.vc.iv 0, 0, v8, 0 13*23c0850dSBrandon Wu; CHECK-NEXT: #APP 14*23c0850dSBrandon Wu; CHECK-NEXT: sf.vc.vv 3, 0, v8, v8 15*23c0850dSBrandon Wu; CHECK-EMPTY: 16*23c0850dSBrandon Wu; CHECK-NEXT: #NO_APP 17*23c0850dSBrandon Wu; CHECK-NEXT: ret 18*23c0850dSBrandon Wuentry: 19*23c0850dSBrandon Wu call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen 0, <vscale x 1 x i64> %vreg, iXLen 0, iXLen 0) 20*23c0850dSBrandon Wu call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;", "=r,^vr,~{memory},~{vl},~{sf.vcix_state}"(<vscale x 1 x i64> %vreg) 21*23c0850dSBrandon Wu ret void 22*23c0850dSBrandon Wu} 23