1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV64 %s 4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64LP64F %s 6 7define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) { 8; RV64-LABEL: callee_v2f32: 9; RV64: # %bb.0: 10; RV64-NEXT: fmv.w.x ft0, a2 11; RV64-NEXT: fmv.w.x ft1, a0 12; RV64-NEXT: fmv.w.x ft2, a3 13; RV64-NEXT: fmv.w.x ft3, a1 14; RV64-NEXT: fadd.s ft2, ft3, ft2 15; RV64-NEXT: fadd.s ft0, ft1, ft0 16; RV64-NEXT: fmv.x.w a0, ft0 17; RV64-NEXT: fmv.x.w a1, ft2 18; RV64-NEXT: ret 19; 20; RV64LP64F-LABEL: callee_v2f32: 21; RV64LP64F: # %bb.0: 22; RV64LP64F-NEXT: fadd.s fa0, fa0, fa2 23; RV64LP64F-NEXT: fadd.s fa1, fa1, fa3 24; RV64LP64F-NEXT: ret 25 %z = fadd <2 x float> %x, %y 26 ret <2 x float> %z 27} 28 29define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) { 30; RV64-LABEL: callee_v4f32: 31; RV64: # %bb.0: 32; RV64-NEXT: fmv.w.x ft0, a4 33; RV64-NEXT: fmv.w.x ft1, a7 34; RV64-NEXT: fmv.w.x ft2, a3 35; RV64-NEXT: fmv.w.x ft3, a6 36; RV64-NEXT: fmv.w.x ft4, a2 37; RV64-NEXT: fmv.w.x ft5, a5 38; RV64-NEXT: fmv.w.x ft6, a1 39; RV64-NEXT: flw ft7, 0(sp) 40; RV64-NEXT: fadd.s ft5, ft6, ft5 41; RV64-NEXT: fadd.s ft3, ft4, ft3 42; RV64-NEXT: fadd.s ft1, ft2, ft1 43; RV64-NEXT: fadd.s ft0, ft0, ft7 44; RV64-NEXT: fsw ft0, 12(a0) 45; RV64-NEXT: fsw ft1, 8(a0) 46; RV64-NEXT: fsw ft3, 4(a0) 47; RV64-NEXT: fsw ft5, 0(a0) 48; RV64-NEXT: ret 49; 50; RV64LP64F-LABEL: callee_v4f32: 51; RV64LP64F: # %bb.0: 52; RV64LP64F-NEXT: fadd.s ft0, fa0, fa4 53; RV64LP64F-NEXT: fadd.s ft1, fa1, fa5 54; RV64LP64F-NEXT: fadd.s ft2, fa2, fa6 55; RV64LP64F-NEXT: fadd.s ft3, fa3, fa7 56; RV64LP64F-NEXT: fsw ft3, 12(a0) 57; RV64LP64F-NEXT: fsw ft2, 8(a0) 58; RV64LP64F-NEXT: fsw ft1, 4(a0) 59; RV64LP64F-NEXT: fsw ft0, 0(a0) 60; RV64LP64F-NEXT: ret 61 %z = fadd <4 x float> %x, %y 62 ret <4 x float> %z 63} 64