xref: /llvm-project/llvm/test/CodeGen/RISCV/bfloat-frem.ll (revision 32597685574e594d745df1bb15dc0e626bd60566)
18a71f44eSAlex Bradbury; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2*32597685SJianjian Guan; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \
38a71f44eSAlex Bradbury; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFBFMIN %s
4*32597685SJianjian Guan; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \
58a71f44eSAlex Bradbury; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFBFMIN %s
68a71f44eSAlex Bradbury
78a71f44eSAlex Bradburydefine bfloat @frem_bf16(bfloat %a, bfloat %b) nounwind {
88a71f44eSAlex Bradbury; RV32IZFBFMIN-LABEL: frem_bf16:
98a71f44eSAlex Bradbury; RV32IZFBFMIN:       # %bb.0:
108a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    addi sp, sp, -16
118a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
128a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    fcvt.s.bf16 fa0, fa0
138a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    fcvt.s.bf16 fa1, fa1
14eabaee0cSFangrui Song; RV32IZFBFMIN-NEXT:    call fmodf
158a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    fcvt.bf16.s fa0, fa0
168a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
178a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    addi sp, sp, 16
188a71f44eSAlex Bradbury; RV32IZFBFMIN-NEXT:    ret
198a71f44eSAlex Bradbury;
208a71f44eSAlex Bradbury; RV64IZFBFMIN-LABEL: frem_bf16:
218a71f44eSAlex Bradbury; RV64IZFBFMIN:       # %bb.0:
228a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    addi sp, sp, -16
238a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
248a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    fcvt.s.bf16 fa0, fa0
258a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    fcvt.s.bf16 fa1, fa1
26eabaee0cSFangrui Song; RV64IZFBFMIN-NEXT:    call fmodf
278a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    fcvt.bf16.s fa0, fa0
288a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
298a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    addi sp, sp, 16
308a71f44eSAlex Bradbury; RV64IZFBFMIN-NEXT:    ret
318a71f44eSAlex Bradbury  %1 = frem bfloat %a, %b
328a71f44eSAlex Bradbury  ret bfloat %1
338a71f44eSAlex Bradbury}
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