1*22d26ae3SPiotr Fusik; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*22d26ae3SPiotr Fusik; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3*22d26ae3SPiotr Fusik; RUN: | FileCheck %s -check-prefix=RV32I 4*22d26ae3SPiotr Fusik; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5*22d26ae3SPiotr Fusik; RUN: | FileCheck %s -check-prefix=RV64I 6*22d26ae3SPiotr Fusik 7*22d26ae3SPiotr Fusikdefine i32 @and_0xfff_shl_2(i32 %x) { 8*22d26ae3SPiotr Fusik; RV32I-LABEL: and_0xfff_shl_2: 9*22d26ae3SPiotr Fusik; RV32I: # %bb.0: 10*22d26ae3SPiotr Fusik; RV32I-NEXT: slli a0, a0, 20 11*22d26ae3SPiotr Fusik; RV32I-NEXT: srli a0, a0, 18 12*22d26ae3SPiotr Fusik; RV32I-NEXT: ret 13*22d26ae3SPiotr Fusik; 14*22d26ae3SPiotr Fusik; RV64I-LABEL: and_0xfff_shl_2: 15*22d26ae3SPiotr Fusik; RV64I: # %bb.0: 16*22d26ae3SPiotr Fusik; RV64I-NEXT: slli a0, a0, 52 17*22d26ae3SPiotr Fusik; RV64I-NEXT: srli a0, a0, 50 18*22d26ae3SPiotr Fusik; RV64I-NEXT: ret 19*22d26ae3SPiotr Fusik %a = and i32 %x, 4095 20*22d26ae3SPiotr Fusik %s = shl i32 %a, 2 21*22d26ae3SPiotr Fusik ret i32 %s 22*22d26ae3SPiotr Fusik} 23*22d26ae3SPiotr Fusik 24*22d26ae3SPiotr Fusikdefine i32 @and_0x7ff_shl_2(i32 %x) { 25*22d26ae3SPiotr Fusik; RV32I-LABEL: and_0x7ff_shl_2: 26*22d26ae3SPiotr Fusik; RV32I: # %bb.0: 27*22d26ae3SPiotr Fusik; RV32I-NEXT: andi a0, a0, 2047 28*22d26ae3SPiotr Fusik; RV32I-NEXT: slli a0, a0, 2 29*22d26ae3SPiotr Fusik; RV32I-NEXT: ret 30*22d26ae3SPiotr Fusik; 31*22d26ae3SPiotr Fusik; RV64I-LABEL: and_0x7ff_shl_2: 32*22d26ae3SPiotr Fusik; RV64I: # %bb.0: 33*22d26ae3SPiotr Fusik; RV64I-NEXT: andi a0, a0, 2047 34*22d26ae3SPiotr Fusik; RV64I-NEXT: slli a0, a0, 2 35*22d26ae3SPiotr Fusik; RV64I-NEXT: ret 36*22d26ae3SPiotr Fusik %a = and i32 %x, 2047 37*22d26ae3SPiotr Fusik %s = shl i32 %a, 2 38*22d26ae3SPiotr Fusik ret i32 %s 39*22d26ae3SPiotr Fusik} 40*22d26ae3SPiotr Fusik 41*22d26ae3SPiotr Fusikdefine i64 @and_0xffffffff_shl_2(i64 %x) { 42*22d26ae3SPiotr Fusik; RV32I-LABEL: and_0xffffffff_shl_2: 43*22d26ae3SPiotr Fusik; RV32I: # %bb.0: 44*22d26ae3SPiotr Fusik; RV32I-NEXT: slli a2, a0, 2 45*22d26ae3SPiotr Fusik; RV32I-NEXT: srli a1, a0, 30 46*22d26ae3SPiotr Fusik; RV32I-NEXT: mv a0, a2 47*22d26ae3SPiotr Fusik; RV32I-NEXT: ret 48*22d26ae3SPiotr Fusik; 49*22d26ae3SPiotr Fusik; RV64I-LABEL: and_0xffffffff_shl_2: 50*22d26ae3SPiotr Fusik; RV64I: # %bb.0: 51*22d26ae3SPiotr Fusik; RV64I-NEXT: slli a0, a0, 32 52*22d26ae3SPiotr Fusik; RV64I-NEXT: srli a0, a0, 30 53*22d26ae3SPiotr Fusik; RV64I-NEXT: ret 54*22d26ae3SPiotr Fusik %a = and i64 %x, 4294967295 55*22d26ae3SPiotr Fusik %s = shl i64 %a, 2 56*22d26ae3SPiotr Fusik ret i64 %s 57*22d26ae3SPiotr Fusik} 58*22d26ae3SPiotr Fusik 59*22d26ae3SPiotr Fusikdefine i32 @and_0xfff_shl_2_multi_use(i32 %x) { 60*22d26ae3SPiotr Fusik; RV32I-LABEL: and_0xfff_shl_2_multi_use: 61*22d26ae3SPiotr Fusik; RV32I: # %bb.0: 62*22d26ae3SPiotr Fusik; RV32I-NEXT: slli a0, a0, 20 63*22d26ae3SPiotr Fusik; RV32I-NEXT: srli a0, a0, 20 64*22d26ae3SPiotr Fusik; RV32I-NEXT: slli a1, a0, 2 65*22d26ae3SPiotr Fusik; RV32I-NEXT: add a0, a0, a1 66*22d26ae3SPiotr Fusik; RV32I-NEXT: ret 67*22d26ae3SPiotr Fusik; 68*22d26ae3SPiotr Fusik; RV64I-LABEL: and_0xfff_shl_2_multi_use: 69*22d26ae3SPiotr Fusik; RV64I: # %bb.0: 70*22d26ae3SPiotr Fusik; RV64I-NEXT: slli a0, a0, 52 71*22d26ae3SPiotr Fusik; RV64I-NEXT: srli a0, a0, 52 72*22d26ae3SPiotr Fusik; RV64I-NEXT: slli a1, a0, 2 73*22d26ae3SPiotr Fusik; RV64I-NEXT: add a0, a0, a1 74*22d26ae3SPiotr Fusik; RV64I-NEXT: ret 75*22d26ae3SPiotr Fusik %a = and i32 %x, 4095 76*22d26ae3SPiotr Fusik %s = shl i32 %a, 2 77*22d26ae3SPiotr Fusik %r = add i32 %a, %s 78*22d26ae3SPiotr Fusik ret i32 %r 79*22d26ae3SPiotr Fusik} 80