xref: /llvm-project/llvm/test/CodeGen/RISCV/O0-pipeline.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343)
17cd78da8SCraig Topper; RUN: llc -mtriple=riscv32 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
27cd78da8SCraig Topper; RUN:   grep -v "Verify generated machine code" | \
37cd78da8SCraig Topper; RUN:   FileCheck %s --check-prefixes=CHECK
47cd78da8SCraig Topper; RUN: llc -mtriple=riscv64 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
57cd78da8SCraig Topper; RUN:   grep -v "Verify generated machine code" | \
67cd78da8SCraig Topper; RUN:   FileCheck %s --check-prefixes=CHECK
77cd78da8SCraig Topper
87cd78da8SCraig Topper; REQUIRES: asserts
97cd78da8SCraig Topper
107cd78da8SCraig Topper; CHECK-LABEL: Pass Arguments:
117cd78da8SCraig Topper; CHECK-NEXT: Target Library Information
127cd78da8SCraig Topper; CHECK-NEXT: Target Pass Configuration
137cd78da8SCraig Topper; CHECK-NEXT: Machine Module Information
147cd78da8SCraig Topper; CHECK-NEXT: Target Transform Information
157cd78da8SCraig Topper; CHECK-NEXT: Create Garbage Collector Module Metadata
167cd78da8SCraig Topper; CHECK-NEXT: Assumption Cache Tracker
177cd78da8SCraig Topper; CHECK-NEXT: Profile summary info
187cd78da8SCraig Topper; CHECK-NEXT: Machine Branch Probability Analysis
197cd78da8SCraig Topper; CHECK-NEXT:   ModulePass Manager
207cd78da8SCraig Topper; CHECK-NEXT:     Pre-ISel Intrinsic Lowering
217cd78da8SCraig Topper; CHECK-NEXT:     FunctionPass Manager
22af3758d6SMatthias Gehre; CHECK-NEXT:       Expand large div/rem
2389f36dd8SFreddy Ye; CHECK-NEXT:       Expand large fp convert
247cd78da8SCraig Topper; CHECK-NEXT:       Expand Atomic instructions
250ee10e94SAlex Bradbury; CHECK-NEXT:       RISC-V Zacas ABI fix
267cd78da8SCraig Topper; CHECK-NEXT:       Module Verifier
277cd78da8SCraig Topper; CHECK-NEXT:       Lower Garbage Collection Instructions
287cd78da8SCraig Topper; CHECK-NEXT:       Shadow Stack GC Lowering
297cd78da8SCraig Topper; CHECK-NEXT:       Remove unreachable blocks from the CFG
30cab81dd0SEgor Pasko; CHECK-NEXT:       Instrument function entry/exit with calls to e.g. mcount() (post inlining)
317cd78da8SCraig Topper; CHECK-NEXT:       Scalarize Masked Memory Intrinsics
327cd78da8SCraig Topper; CHECK-NEXT:       Expand reduction intrinsics
337cd78da8SCraig Topper; CHECK-NEXT:       Exception handling preparation
34a3a84c9eSNick Desaulniers; CHECK-NEXT:       Prepare callbr
357cd78da8SCraig Topper; CHECK-NEXT:       Safe Stack instrumentation pass
367cd78da8SCraig Topper; CHECK-NEXT:       Insert stack protectors
377cd78da8SCraig Topper; CHECK-NEXT:       Module Verifier
3899c12afeSOCHyams; CHECK-NEXT:       Assignment Tracking Analysis
390f4c9c01SCraig Topper; CHECK-NEXT:       RISC-V DAG->DAG Pattern Instruction Selection
407cd78da8SCraig Topper; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
417cd78da8SCraig Topper; CHECK-NEXT:       Local Stack Slot Allocation
420f4c9c01SCraig Topper; CHECK-NEXT:       RISC-V Pre-RA pseudo instruction expansion pass
437c836512SeopXD; CHECK-NEXT:       RISC-V Insert Read/Write CSR Pass
44014390d9SCraig Topper; CHECK-NEXT:       RISC-V Insert Write VXRM Pass
45e80d8e1bSYeting Kuo; CHECK-NEXT:       RISC-V Landing Pad Setup
4628233408SJack Styles; CHECK-NEXT:       Init Undef Pass
477cd78da8SCraig Topper; CHECK-NEXT:       Eliminate PHI nodes for register allocation
48675e7bd1SPiyou Chen; CHECK-NEXT:       Two-Address instruction pass
49675e7bd1SPiyou Chen; CHECK-NEXT:       Fast Register Allocator
501a58e886SLuke Lau; CHECK-NEXT:       RISC-V Insert VSETVLI pass
51d0a39e61SPiyou Chen; CHECK-NEXT:       Fast Register Allocator
527cd78da8SCraig Topper; CHECK-NEXT:       Remove Redundant DEBUG_VALUE analysis
537cd78da8SCraig Topper; CHECK-NEXT:       Fixup Statepoint Caller Saved
547cd78da8SCraig Topper; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
557cd78da8SCraig Topper; CHECK-NEXT:       Machine Optimization Remark Emitter
567cd78da8SCraig Topper; CHECK-NEXT:       Prologue/Epilogue Insertion & Frame Finalization
577cd78da8SCraig Topper; CHECK-NEXT:       Post-RA pseudo instruction expansion pass
58109aa586SCraig Topper; CHECK-NEXT:       RISC-V post-regalloc pseudo instruction expansion pass
5983835e22SSami Tolvanen; CHECK-NEXT:       Insert KCFI indirect call checks
607cd78da8SCraig Topper; CHECK-NEXT:       Analyze Machine Code For Garbage Collection
617cd78da8SCraig Topper; CHECK-NEXT:       Insert fentry calls
627cd78da8SCraig Topper; CHECK-NEXT:       Insert XRay ops
637cd78da8SCraig Topper; CHECK-NEXT:       Implement the 'patchable-function' attribute
647cd78da8SCraig Topper; CHECK-NEXT:       Branch relaxation pass
650f4c9c01SCraig Topper; CHECK-NEXT:       RISC-V Make Compressible
667cd78da8SCraig Topper; CHECK-NEXT:       Contiguously Lay Out Funclets
673d08ade7SStephen Tozer; CHECK-NEXT:       Remove Loads Into Fake Uses
687cd78da8SCraig Topper; CHECK-NEXT:       StackMap Liveness Analysis
697cd78da8SCraig Topper; CHECK-NEXT:       Live DEBUG_VALUE analysis
70dbe8c2c3SDmitry Vyukov; CHECK-NEXT:       Machine Sanitizer Binary Metadata
71*97982a8cSdlav-sc; CHECK-NEXT:       Insert CFI remember/restore state instructions
72557a5bc3SPaul Kirth; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
73557a5bc3SPaul Kirth; CHECK-NEXT:       Machine Optimization Remark Emitter
74557a5bc3SPaul Kirth; CHECK-NEXT:       Stack Frame Layout Analysis
759fb196b4SYeting Kuo; CHECK-NEXT:       RISC-V Indirect Branch Tracking
760f4c9c01SCraig Topper; CHECK-NEXT:       RISC-V pseudo instruction expansion pass
770f4c9c01SCraig Topper; CHECK-NEXT:       RISC-V atomic pseudo instruction expansion pass
7883835e22SSami Tolvanen; CHECK-NEXT:       Unpack machine instruction bundles
797cd78da8SCraig Topper; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
807cd78da8SCraig Topper; CHECK-NEXT:       Machine Optimization Remark Emitter
810f4c9c01SCraig Topper; CHECK-NEXT:       RISC-V Assembly Printer
827cd78da8SCraig Topper; CHECK-NEXT:       Free MachineFunction
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