1; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM 2; instruction format). 3 4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 6define i32 @msa_ir_cfcmsa_test() nounwind { 7entry: 8 %0 = tail call i32 @llvm.mips.cfcmsa(i32 0) 9 ret i32 %0 10} 11 12; CHECK: msa_ir_cfcmsa_test: 13; CHECK: cfcmsa $[[R1:[0-9]+]], $0 14; CHECK: .size msa_ir_cfcmsa_test 15; 16define i32 @msa_csr_cfcmsa_test() nounwind { 17entry: 18 %0 = tail call i32 @llvm.mips.cfcmsa(i32 1) 19 ret i32 %0 20} 21 22; CHECK: msa_csr_cfcmsa_test: 23; CHECK: cfcmsa $[[R1:[0-9]+]], $1 24; CHECK: .size msa_csr_cfcmsa_test 25; 26define i32 @msa_access_cfcmsa_test() nounwind { 27entry: 28 %0 = tail call i32 @llvm.mips.cfcmsa(i32 2) 29 ret i32 %0 30} 31 32; CHECK: msa_access_cfcmsa_test: 33; CHECK: cfcmsa $[[R1:[0-9]+]], $2 34; CHECK: .size msa_access_cfcmsa_test 35; 36define i32 @msa_save_cfcmsa_test() nounwind { 37entry: 38 %0 = tail call i32 @llvm.mips.cfcmsa(i32 3) 39 ret i32 %0 40} 41 42; CHECK: msa_save_cfcmsa_test: 43; CHECK: cfcmsa $[[R1:[0-9]+]], $3 44; CHECK: .size msa_save_cfcmsa_test 45; 46define i32 @msa_modify_cfcmsa_test() nounwind { 47entry: 48 %0 = tail call i32 @llvm.mips.cfcmsa(i32 4) 49 ret i32 %0 50} 51 52; CHECK: msa_modify_cfcmsa_test: 53; CHECK: cfcmsa $[[R1:[0-9]+]], $4 54; CHECK: .size msa_modify_cfcmsa_test 55; 56define i32 @msa_request_cfcmsa_test() nounwind { 57entry: 58 %0 = tail call i32 @llvm.mips.cfcmsa(i32 5) 59 ret i32 %0 60} 61 62; CHECK: msa_request_cfcmsa_test: 63; CHECK: cfcmsa $[[R1:[0-9]+]], $5 64; CHECK: .size msa_request_cfcmsa_test 65; 66define i32 @msa_map_cfcmsa_test() nounwind { 67entry: 68 %0 = tail call i32 @llvm.mips.cfcmsa(i32 6) 69 ret i32 %0 70} 71 72; CHECK: msa_map_cfcmsa_test: 73; CHECK: cfcmsa $[[R1:[0-9]+]], $6 74; CHECK: .size msa_map_cfcmsa_test 75; 76define i32 @msa_unmap_cfcmsa_test() nounwind { 77entry: 78 %0 = tail call i32 @llvm.mips.cfcmsa(i32 7) 79 ret i32 %0 80} 81 82; CHECK: msa_unmap_cfcmsa_test: 83; CHECK: cfcmsa $[[R1:[0-9]+]], $7 84; CHECK: .size msa_unmap_cfcmsa_test 85; 86define void @msa_ir_ctcmsa_test() nounwind { 87entry: 88 tail call void @llvm.mips.ctcmsa(i32 0, i32 1) 89 ret void 90} 91 92; CHECK: msa_ir_ctcmsa_test: 93; CHECK: ctcmsa $0 94; CHECK: .size msa_ir_ctcmsa_test 95; 96define void @msa_csr_ctcmsa_test() nounwind { 97entry: 98 tail call void @llvm.mips.ctcmsa(i32 1, i32 1) 99 ret void 100} 101 102; CHECK: msa_csr_ctcmsa_test: 103; CHECK: ctcmsa $1 104; CHECK: .size msa_csr_ctcmsa_test 105; 106define void @msa_access_ctcmsa_test() nounwind { 107entry: 108 tail call void @llvm.mips.ctcmsa(i32 2, i32 1) 109 ret void 110} 111 112; CHECK: msa_access_ctcmsa_test: 113; CHECK: ctcmsa $2 114; CHECK: .size msa_access_ctcmsa_test 115; 116define void @msa_save_ctcmsa_test() nounwind { 117entry: 118 tail call void @llvm.mips.ctcmsa(i32 3, i32 1) 119 ret void 120} 121 122; CHECK: msa_save_ctcmsa_test: 123; CHECK: ctcmsa $3 124; CHECK: .size msa_save_ctcmsa_test 125; 126define void @msa_modify_ctcmsa_test() nounwind { 127entry: 128 tail call void @llvm.mips.ctcmsa(i32 4, i32 1) 129 ret void 130} 131 132; CHECK: msa_modify_ctcmsa_test: 133; CHECK: ctcmsa $4 134; CHECK: .size msa_modify_ctcmsa_test 135; 136define void @msa_request_ctcmsa_test() nounwind { 137entry: 138 tail call void @llvm.mips.ctcmsa(i32 5, i32 1) 139 ret void 140} 141 142; CHECK: msa_request_ctcmsa_test: 143; CHECK: ctcmsa $5 144; CHECK: .size msa_request_ctcmsa_test 145; 146define void @msa_map_ctcmsa_test() nounwind { 147entry: 148 tail call void @llvm.mips.ctcmsa(i32 6, i32 1) 149 ret void 150} 151 152; CHECK: msa_map_ctcmsa_test: 153; CHECK: ctcmsa $6 154; CHECK: .size msa_map_ctcmsa_test 155; 156define void @msa_unmap_ctcmsa_test() nounwind { 157entry: 158 tail call void @llvm.mips.ctcmsa(i32 7, i32 1) 159 ret void 160} 161 162; CHECK: msa_unmap_ctcmsa_test: 163; CHECK: ctcmsa $7 164; CHECK: .size msa_unmap_ctcmsa_test 165; 166declare i32 @llvm.mips.cfcmsa(i32) nounwind 167declare void @llvm.mips.ctcmsa(i32, i32) nounwind 168