xref: /llvm-project/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1*9e9907f1SFangrui Song# RUN: not llc -mtriple=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
2bc6d07caSMatt Arsenault
3bc6d07caSMatt Arsenault---
4bc6d07caSMatt Arsenaultname: wrong_reg_class_frame_offset_reg
5bc6d07caSMatt ArsenaultmachineFunctionInfo:
6bc6d07caSMatt Arsenault  frameOffsetReg:  '$vgpr0'
7479145a5SJay Foad# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
8bc6d07caSMatt Arsenaultbody:             |
9bc6d07caSMatt Arsenault  bb.0:
10bc6d07caSMatt Arsenault
11bc6d07caSMatt Arsenault    S_ENDPGM
12bc6d07caSMatt Arsenault...
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