xref: /llvm-project/llvm/test/CodeGen/ARM/v6m-umul-with-overflow.ll (revision 208ddc5bdc554ed7c90d4515a04bb8f720b82213) 
1*208ddc5bSTim Northover; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
2*208ddc5bSTim Northover
3*208ddc5bSTim Northoverdefine i1 @unsigned_multiplication_did_overflow(i32, i32) {
4*208ddc5bSTim Northover; CHECK-LABEL: unsigned_multiplication_did_overflow:
5*208ddc5bSTim Northoverentry-block:
6*208ddc5bSTim Northover  %2 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %0, i32 %1)
7*208ddc5bSTim Northover  %3 = extractvalue { i32, i1 } %2, 1
8*208ddc5bSTim Northover  ret i1 %3
9*208ddc5bSTim Northover
10*208ddc5bSTim Northover; CHECK: mov{{s?}}    r2, r1
11*208ddc5bSTim Northover; CHECK: mov{{s?}}    r1, #0
12*208ddc5bSTim Northover; CHECK: mov{{s?}}    r3, {{#0|r1}}
13*208ddc5bSTim Northover; CHECK: bl     __aeabi_lmul
14*208ddc5bSTim Northover}
15*208ddc5bSTim Northover
16*208ddc5bSTim Northoverdeclare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
17