xref: /llvm-project/llvm/test/CodeGen/ARM/v6m-smul-with-overflow.ll (revision acbd4e141fdbbdec11831026a187987102dfa910) 
1*acbd4e14SRanjeet Singh; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
2*acbd4e14SRanjeet Singh
3*acbd4e14SRanjeet Singhdefine i1 @signed_multiplication_did_overflow(i32, i32) {
4*acbd4e14SRanjeet Singh; CHECK-LABEL: signed_multiplication_did_overflow:
5*acbd4e14SRanjeet Singhentry-block:
6*acbd4e14SRanjeet Singh  %2 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %1)
7*acbd4e14SRanjeet Singh  %3 = extractvalue { i32, i1 } %2, 1
8*acbd4e14SRanjeet Singh  ret i1 %3
9*acbd4e14SRanjeet Singh
10*acbd4e14SRanjeet Singh; CHECK: mov    r2, r1
11*acbd4e14SRanjeet Singh; CHECK: asrs   r1, r0, #31
12*acbd4e14SRanjeet Singh; CHECK: asrs   r3, r2, #31
13*acbd4e14SRanjeet Singh; CHECK: bl     __aeabi_lmul
14*acbd4e14SRanjeet Singh}
15*acbd4e14SRanjeet Singh
16*acbd4e14SRanjeet Singhdeclare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
17