xref: /llvm-project/llvm/test/CodeGen/ARM/usat-with-shift.ll (revision 675431b9878776e3c919b79162774a9cdabdaa4c)
120283ff4SMeera Nakrani; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
220283ff4SMeera Nakrani; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s
320283ff4SMeera Nakrani; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+dsp %s -o - | FileCheck %s
420283ff4SMeera Nakrani
520283ff4SMeera Nakranidefine arm_aapcs_vfpcc i32 @usat_lsl(i32 %num){
620283ff4SMeera Nakrani; CHECK-LABEL:  usat_lsl
720283ff4SMeera Nakrani; CHECK:        @ %bb.0: @ %entry
820283ff4SMeera Nakrani; CHECK-NEXT: 	usat	r0, #7, r0, lsl #2
920283ff4SMeera Nakrani; CHECK-NEXT:   bx	lr
1020283ff4SMeera Nakranientry:
1120283ff4SMeera Nakrani  %shl = shl i32 %num, 2
1220283ff4SMeera Nakrani  %0 = tail call i32 @llvm.arm.usat(i32 %shl, i32 7)
1320283ff4SMeera Nakrani  ret i32 %0
1420283ff4SMeera Nakrani}
1520283ff4SMeera Nakrani
1620283ff4SMeera Nakranidefine arm_aapcs_vfpcc i32 @usat_asr(i32 %num){
1720283ff4SMeera Nakrani; CHECK-LABEL:  usat_asr
1820283ff4SMeera Nakrani; CHECK:        @ %bb.0: @ %entry
1920283ff4SMeera Nakrani; CHECK-NEXT:   usat	r0, #7, r0, asr #2
2020283ff4SMeera Nakrani; CHECK-NEXT:   bx	lr
2120283ff4SMeera Nakranientry:
2220283ff4SMeera Nakrani  %shr = ashr i32 %num, 2
2320283ff4SMeera Nakrani  %0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)
2420283ff4SMeera Nakrani  ret i32 %0
2520283ff4SMeera Nakrani}
2620283ff4SMeera Nakrani
27*675431b9SMeera Nakranidefine arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){
28*675431b9SMeera Nakrani; CHECK-LABEL: usat_lsl2:
29*675431b9SMeera Nakrani; CHECK:       @ %bb.0: @ %entry
30*675431b9SMeera Nakrani; CHECK-NEXT:    usat r0, #15, r0, lsl #15
31*675431b9SMeera Nakrani; CHECK-NEXT:    bx lr
32*675431b9SMeera Nakranientry:
33*675431b9SMeera Nakrani  %shl = shl nsw i32 %num, 15
34*675431b9SMeera Nakrani  %0 = icmp sgt i32 %shl, 0
35*675431b9SMeera Nakrani  %1 = select i1 %0, i32 %shl, i32 0
36*675431b9SMeera Nakrani  %2 = icmp slt i32 %1, 32767
37*675431b9SMeera Nakrani  %3 = select i1 %2, i32 %1, i32 32767
38*675431b9SMeera Nakrani  ret i32 %3
39*675431b9SMeera Nakrani}
40*675431b9SMeera Nakrani
41*675431b9SMeera Nakranidefine arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){
42*675431b9SMeera Nakrani; CHECK-LABEL: usat_asr2:
43*675431b9SMeera Nakrani; CHECK:       @ %bb.0: @ %entry
44*675431b9SMeera Nakrani; CHECK-NEXT:    usat r0, #15, r0, asr #15
45*675431b9SMeera Nakrani; CHECK-NEXT:    bx lr
46*675431b9SMeera Nakranientry:
47*675431b9SMeera Nakrani  %shr = ashr i32 %num, 15
48*675431b9SMeera Nakrani  %0 = icmp sgt i32 %shr, 0
49*675431b9SMeera Nakrani  %1 = select i1 %0, i32 %shr, i32 0
50*675431b9SMeera Nakrani  %2 = icmp slt i32 %1, 32767
51*675431b9SMeera Nakrani  %3 = select i1 %2, i32 %1, i32 32767
52*675431b9SMeera Nakrani  ret i32 %3
53*675431b9SMeera Nakrani}
54*675431b9SMeera Nakrani
5520283ff4SMeera Nakranideclare i32 @llvm.arm.usat(i32, i32)
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