xref: /llvm-project/llvm/test/CodeGen/ARM/unschedule-reg-sequence.ll (revision 98265db84c332a6969b0ca10031f175f2af731fa)
1*98265db8SFilipp Zhinkin; RUN: llc -verify-machineinstrs < %s
2*98265db8SFilipp Zhinkin; Regression test for https://github.com/llvm/llvm-project/issues/58911
3*98265db8SFilipp Zhinkin
4*98265db8SFilipp Zhinkintarget datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
5*98265db8SFilipp Zhinkintarget triple = "armv7-none-unknown-eabi"
6*98265db8SFilipp Zhinkin
7*98265db8SFilipp Zhinkin@a = dso_local global i64 0, align 8
8*98265db8SFilipp Zhinkin@d = dso_local local_unnamed_addr global i32 0, align 4
9*98265db8SFilipp Zhinkin
10*98265db8SFilipp Zhinkindefine dso_local void @f() nounwind {
11*98265db8SFilipp Zhinkinentry:
12*98265db8SFilipp Zhinkin  store volatile i64 0, ptr @a, align 8
13*98265db8SFilipp Zhinkin  %0 = load i32, ptr @d, align 4
14*98265db8SFilipp Zhinkin  %tobool.not = icmp eq i32 %0, 0
15*98265db8SFilipp Zhinkin  %conv = zext i32 %0 to i64
16*98265db8SFilipp Zhinkin  %sub = sub nsw i64 0, %conv
17*98265db8SFilipp Zhinkin  %cond = select i1 %tobool.not, i64 0, i64 %sub
18*98265db8SFilipp Zhinkin  store volatile i64 %cond, ptr @a, align 8
19*98265db8SFilipp Zhinkin  ret void
20*98265db8SFilipp Zhinkin}
21*98265db8SFilipp Zhinkin
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