1*c3260c65SBenjamin Maxwell; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2*c3260c65SBenjamin Maxwell; RUN: llc -mtriple=thumbv7-gnu-linux < %s | FileCheck -check-prefixes=CHECK %s 3*c3260c65SBenjamin Maxwell 4*c3260c65SBenjamin Maxwelldefine { half, half } @test_sincos_f16(half %a) { 5*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_f16: 6*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 7*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r4, lr} 8*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #8 9*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_h2f_ieee 10*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #4 11*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r2, sp 12*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 13*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r0, [sp, #4] 14*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 15*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r4, r0 16*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r0, [sp] 17*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 18*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r1, r0 19*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r0, r4 20*c3260c65SBenjamin Maxwell; CHECK-NEXT: add sp, #8 21*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r4, pc} 22*c3260c65SBenjamin Maxwell %result = call { half, half } @llvm.sincos.f16(half %a) 23*c3260c65SBenjamin Maxwell ret { half, half } %result 24*c3260c65SBenjamin Maxwell} 25*c3260c65SBenjamin Maxwell 26*c3260c65SBenjamin Maxwelldefine half @test_sincos_f16_only_use_sin(half %a) { 27*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_f16_only_use_sin: 28*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 29*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r7, lr} 30*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #8 31*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_h2f_ieee 32*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #4 33*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r2, sp 34*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 35*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r0, [sp, #4] 36*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 37*c3260c65SBenjamin Maxwell; CHECK-NEXT: add sp, #8 38*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r7, pc} 39*c3260c65SBenjamin Maxwell %result = call { half, half } @llvm.sincos.f16(half %a) 40*c3260c65SBenjamin Maxwell %result.0 = extractvalue { half, half } %result, 0 41*c3260c65SBenjamin Maxwell ret half %result.0 42*c3260c65SBenjamin Maxwell} 43*c3260c65SBenjamin Maxwell 44*c3260c65SBenjamin Maxwelldefine half @test_sincos_f16_only_use_cos(half %a) { 45*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_f16_only_use_cos: 46*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 47*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r7, lr} 48*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #8 49*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_h2f_ieee 50*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #4 51*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r2, sp 52*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 53*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r0, [sp] 54*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 55*c3260c65SBenjamin Maxwell; CHECK-NEXT: add sp, #8 56*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r7, pc} 57*c3260c65SBenjamin Maxwell %result = call { half, half } @llvm.sincos.f16(half %a) 58*c3260c65SBenjamin Maxwell %result.1 = extractvalue { half, half } %result, 1 59*c3260c65SBenjamin Maxwell ret half %result.1 60*c3260c65SBenjamin Maxwell} 61*c3260c65SBenjamin Maxwell 62*c3260c65SBenjamin Maxwelldefine { <2 x half>, <2 x half> } @test_sincos_v2f16(<2 x half> %a) { 63*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_v2f16: 64*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 65*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r4, lr} 66*c3260c65SBenjamin Maxwell; CHECK-NEXT: vpush {d8} 67*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #24 68*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r4, r0 69*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r0, r1 70*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_h2f_ieee 71*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #12 72*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r2, sp, #8 73*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 74*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r0, r4 75*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_h2f_ieee 76*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #4 77*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r2, sp 78*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 79*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r0, [sp, #12] 80*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 81*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r1, [sp, #4] 82*c3260c65SBenjamin Maxwell; CHECK-NEXT: strh.w r0, [sp, #22] 83*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r0, r1 84*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 85*c3260c65SBenjamin Maxwell; CHECK-NEXT: strh.w r0, [sp, #20] 86*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r0, sp, #20 87*c3260c65SBenjamin Maxwell; CHECK-NEXT: vld1.32 {d8[0]}, [r0:32] 88*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r0, [sp, #8] 89*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 90*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r1, [sp] 91*c3260c65SBenjamin Maxwell; CHECK-NEXT: strh.w r0, [sp, #18] 92*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r0, r1 93*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl __gnu_f2h_ieee 94*c3260c65SBenjamin Maxwell; CHECK-NEXT: strh.w r0, [sp, #16] 95*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r0, sp, #16 96*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmovl.u16 q9, d8 97*c3260c65SBenjamin Maxwell; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32] 98*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmovl.u16 q8, d16 99*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov.32 r0, d18[0] 100*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov.32 r1, d18[1] 101*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov.32 r2, d16[0] 102*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov.32 r3, d16[1] 103*c3260c65SBenjamin Maxwell; CHECK-NEXT: add sp, #24 104*c3260c65SBenjamin Maxwell; CHECK-NEXT: vpop {d8} 105*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r4, pc} 106*c3260c65SBenjamin Maxwell %result = call { <2 x half>, <2 x half> } @llvm.sincos.v2f16(<2 x half> %a) 107*c3260c65SBenjamin Maxwell ret { <2 x half>, <2 x half> } %result 108*c3260c65SBenjamin Maxwell} 109*c3260c65SBenjamin Maxwell 110*c3260c65SBenjamin Maxwelldefine { float, float } @test_sincos_f32(float %a) { 111*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_f32: 112*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 113*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r7, lr} 114*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #8 115*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #4 116*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r2, sp 117*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 118*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd r1, r0, [sp], #8 119*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r7, pc} 120*c3260c65SBenjamin Maxwell %result = call { float, float } @llvm.sincos.f32(float %a) 121*c3260c65SBenjamin Maxwell ret { float, float } %result 122*c3260c65SBenjamin Maxwell} 123*c3260c65SBenjamin Maxwell 124*c3260c65SBenjamin Maxwelldefine { <2 x float>, <2 x float> } @test_sincos_v2f32(<2 x float> %a) { 125*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_v2f32: 126*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 127*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r7, lr} 128*c3260c65SBenjamin Maxwell; CHECK-NEXT: vpush {d8} 129*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #16 130*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov d8, r0, r1 131*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #4 132*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r2, sp 133*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov r0, s17 134*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 135*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov r0, s16 136*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r1, sp, #12 137*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r2, sp, #8 138*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosf 139*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr s1, [sp, #4] 140*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr s3, [sp] 141*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr s0, [sp, #12] 142*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr s2, [sp, #8] 143*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov r0, r1, d0 144*c3260c65SBenjamin Maxwell; CHECK-NEXT: vmov r2, r3, d1 145*c3260c65SBenjamin Maxwell; CHECK-NEXT: add sp, #16 146*c3260c65SBenjamin Maxwell; CHECK-NEXT: vpop {d8} 147*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r7, pc} 148*c3260c65SBenjamin Maxwell %result = call { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float> %a) 149*c3260c65SBenjamin Maxwell ret { <2 x float>, <2 x float> } %result 150*c3260c65SBenjamin Maxwell} 151*c3260c65SBenjamin Maxwell 152*c3260c65SBenjamin Maxwelldefine { double, double } @test_sincos_f64(double %a) { 153*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_f64: 154*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 155*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r7, lr} 156*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #16 157*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r2, sp, #8 158*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r3, sp 159*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincos 160*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd r0, r1, [sp, #8] 161*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd r2, r3, [sp], #16 162*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r7, pc} 163*c3260c65SBenjamin Maxwell %result = call { double, double } @llvm.sincos.f64(double %a) 164*c3260c65SBenjamin Maxwell ret { double, double } %result 165*c3260c65SBenjamin Maxwell} 166*c3260c65SBenjamin Maxwell 167*c3260c65SBenjamin Maxwelldefine { <2 x double>, <2 x double> } @test_sincos_v2f64(<2 x double> %a) { 168*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_v2f64: 169*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 170*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r4, lr} 171*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #32 172*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r1, r3 173*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r12, r2 174*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r2, sp, #24 175*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r3, sp, #16 176*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r4, r0 177*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r0, r12 178*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincos 179*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd r0, r1, [sp, #40] 180*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r2, sp, #8 181*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r3, sp 182*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincos 183*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr d19, [sp, #8] 184*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr d18, [sp, #24] 185*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr d17, [sp] 186*c3260c65SBenjamin Maxwell; CHECK-NEXT: vldr d16, [sp, #16] 187*c3260c65SBenjamin Maxwell; CHECK-NEXT: vst1.64 {d18, d19}, [r4]! 188*c3260c65SBenjamin Maxwell; CHECK-NEXT: vst1.64 {d16, d17}, [r4] 189*c3260c65SBenjamin Maxwell; CHECK-NEXT: add sp, #32 190*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r4, pc} 191*c3260c65SBenjamin Maxwell %result = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> %a) 192*c3260c65SBenjamin Maxwell ret { <2 x double>, <2 x double> } %result 193*c3260c65SBenjamin Maxwell} 194*c3260c65SBenjamin Maxwell 195*c3260c65SBenjamin Maxwelldefine { fp128, fp128 } @test_sincos_f128(fp128 %a) { 196*c3260c65SBenjamin Maxwell; CHECK-LABEL: test_sincos_f128: 197*c3260c65SBenjamin Maxwell; CHECK: @ %bb.0: 198*c3260c65SBenjamin Maxwell; CHECK-NEXT: push {r4, r5, r7, lr} 199*c3260c65SBenjamin Maxwell; CHECK-NEXT: sub sp, #40 200*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r12, r3 201*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldr r3, [sp, #56] 202*c3260c65SBenjamin Maxwell; CHECK-NEXT: add.w lr, sp, #8 203*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r4, r0 204*c3260c65SBenjamin Maxwell; CHECK-NEXT: add r0, sp, #24 205*c3260c65SBenjamin Maxwell; CHECK-NEXT: strd r0, lr, [sp] 206*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r0, r1 207*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r1, r2 208*c3260c65SBenjamin Maxwell; CHECK-NEXT: mov r2, r12 209*c3260c65SBenjamin Maxwell; CHECK-NEXT: bl sincosl 210*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd r2, r3, [sp, #16] 211*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd r12, r1, [sp, #8] 212*c3260c65SBenjamin Maxwell; CHECK-NEXT: str r3, [r4, #28] 213*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd r3, r5, [sp, #32] 214*c3260c65SBenjamin Maxwell; CHECK-NEXT: ldrd lr, r0, [sp, #24] 215*c3260c65SBenjamin Maxwell; CHECK-NEXT: strd r1, r2, [r4, #20] 216*c3260c65SBenjamin Maxwell; CHECK-NEXT: add.w r1, r4, #8 217*c3260c65SBenjamin Maxwell; CHECK-NEXT: stm.w r1, {r3, r5, r12} 218*c3260c65SBenjamin Maxwell; CHECK-NEXT: strd lr, r0, [r4] 219*c3260c65SBenjamin Maxwell; CHECK-NEXT: add sp, #40 220*c3260c65SBenjamin Maxwell; CHECK-NEXT: pop {r4, r5, r7, pc} 221*c3260c65SBenjamin Maxwell %result = call { fp128, fp128 } @llvm.sincos.f16(fp128 %a) 222*c3260c65SBenjamin Maxwell ret { fp128, fp128 } %result 223*c3260c65SBenjamin Maxwell} 224