1*945a660cSMehdi Amini; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM 2*945a660cSMehdi Amini; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM 3*945a660cSMehdi Amini; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB 49cf803c4SChad Rosier 569fb6ddcSChad Rosierdefine i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind { 669fb6ddcSChad Rosierentry: 769fb6ddcSChad Rosier; ARM: icmp_i16_signed 869fb6ddcSChad Rosier; ARM: sxth r0, r0 969fb6ddcSChad Rosier; ARM: sxth r1, r1 1069fb6ddcSChad Rosier; ARM: cmp r0, r1 1169fb6ddcSChad Rosier; THUMB: icmp_i16_signed 1269fb6ddcSChad Rosier; THUMB: sxth r0, r0 1369fb6ddcSChad Rosier; THUMB: sxth r1, r1 1469fb6ddcSChad Rosier; THUMB: cmp r0, r1 1569fb6ddcSChad Rosier %cmp = icmp slt i16 %a, %b 1669fb6ddcSChad Rosier %conv2 = zext i1 %cmp to i32 1769fb6ddcSChad Rosier ret i32 %conv2 1869fb6ddcSChad Rosier} 1969fb6ddcSChad Rosier 209cf803c4SChad Rosierdefine i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { 219cf803c4SChad Rosierentry: 229cf803c4SChad Rosier; ARM: icmp_i16_unsigned 239cf803c4SChad Rosier; ARM: uxth r0, r0 249cf803c4SChad Rosier; ARM: uxth r1, r1 259cf803c4SChad Rosier; ARM: cmp r0, r1 269cf803c4SChad Rosier; THUMB: icmp_i16_unsigned 279cf803c4SChad Rosier; THUMB: uxth r0, r0 289cf803c4SChad Rosier; THUMB: uxth r1, r1 299cf803c4SChad Rosier; THUMB: cmp r0, r1 309cf803c4SChad Rosier %cmp = icmp ult i16 %a, %b 319cf803c4SChad Rosier %conv2 = zext i1 %cmp to i32 329cf803c4SChad Rosier ret i32 %conv2 339cf803c4SChad Rosier} 349cf803c4SChad Rosier 359cf803c4SChad Rosierdefine i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind { 369cf803c4SChad Rosierentry: 379cf803c4SChad Rosier; ARM: icmp_i8_signed 389cf803c4SChad Rosier; ARM: sxtb r0, r0 399cf803c4SChad Rosier; ARM: sxtb r1, r1 409cf803c4SChad Rosier; ARM: cmp r0, r1 419cf803c4SChad Rosier; THUMB: icmp_i8_signed 429cf803c4SChad Rosier; THUMB: sxtb r0, r0 439cf803c4SChad Rosier; THUMB: sxtb r1, r1 449cf803c4SChad Rosier; THUMB: cmp r0, r1 459cf803c4SChad Rosier %cmp = icmp sgt i8 %a, %b 469cf803c4SChad Rosier %conv2 = zext i1 %cmp to i32 479cf803c4SChad Rosier ret i32 %conv2 489cf803c4SChad Rosier} 499cf803c4SChad Rosier 5069fb6ddcSChad Rosierdefine i32 @icmp_i8_unsigned(i8 %a, i8 %b) nounwind { 5169fb6ddcSChad Rosierentry: 5269fb6ddcSChad Rosier; ARM: icmp_i8_unsigned 5306ce03d1SJF Bastien; ARM: and r0, r0, #255 5406ce03d1SJF Bastien; ARM: and r1, r1, #255 5569fb6ddcSChad Rosier; ARM: cmp r0, r1 5669fb6ddcSChad Rosier; THUMB: icmp_i8_unsigned 5706ce03d1SJF Bastien; THUMB: and r0, r0, #255 5806ce03d1SJF Bastien; THUMB: and r1, r1, #255 5969fb6ddcSChad Rosier; THUMB: cmp r0, r1 6069fb6ddcSChad Rosier %cmp = icmp ugt i8 %a, %b 6169fb6ddcSChad Rosier %conv2 = zext i1 %cmp to i32 6269fb6ddcSChad Rosier ret i32 %conv2 6369fb6ddcSChad Rosier} 6469fb6ddcSChad Rosier 659cf803c4SChad Rosierdefine i32 @icmp_i1_unsigned(i1 %a, i1 %b) nounwind { 669cf803c4SChad Rosierentry: 679cf803c4SChad Rosier; ARM: icmp_i1_unsigned 689cf803c4SChad Rosier; ARM: and r0, r0, #1 699cf803c4SChad Rosier; ARM: and r1, r1, #1 709cf803c4SChad Rosier; ARM: cmp r0, r1 719cf803c4SChad Rosier; THUMB: icmp_i1_unsigned 729cf803c4SChad Rosier; THUMB: and r0, r0, #1 739cf803c4SChad Rosier; THUMB: and r1, r1, #1 749cf803c4SChad Rosier; THUMB: cmp r0, r1 759cf803c4SChad Rosier %cmp = icmp ult i1 %a, %b 769cf803c4SChad Rosier %conv2 = zext i1 %cmp to i32 779cf803c4SChad Rosier ret i32 %conv2 789cf803c4SChad Rosier} 79