16bc35a93SEugene Leviant; REQUIRES: asserts 26bc35a93SEugene Leviant; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 36bc35a93SEugene Leviant 4*25528d6dSFrancis Visoiu Mistrih; CHECK-LABEL: addv_i32:%bb.0 56bc35a93SEugene Leviant; CHECK: SU(8): {{.*}} VADDv4i32 66bc35a93SEugene Leviant; CHECK-NEXT: # preds left 76bc35a93SEugene Leviant; CHECK-NEXT: # succs left 86bc35a93SEugene Leviant; CHECK-NEXT: # rdefs left 96bc35a93SEugene Leviant; CHECK-NEXT: Latency : 3 106bc35a93SEugene Leviant 116bc35a93SEugene Leviantdefine <4 x i32> @addv_i32(<4 x i32>, <4 x i32>) { 126bc35a93SEugene Leviant %3 = add <4 x i32> %1, %0 136bc35a93SEugene Leviant ret <4 x i32> %3 146bc35a93SEugene Leviant} 156bc35a93SEugene Leviant 16*25528d6dSFrancis Visoiu Mistrih; CHECK-LABEL: addv_f32:%bb.0 176bc35a93SEugene Leviant; CHECK: SU(8): {{.*}} VADDfq 186bc35a93SEugene Leviant; CHECK-NEXT: # preds left 196bc35a93SEugene Leviant; CHECK-NEXT: # succs left 206bc35a93SEugene Leviant; CHECK-NEXT: # rdefs left 216bc35a93SEugene Leviant; CHECK-NEXT: Latency : 5 226bc35a93SEugene Leviant 236bc35a93SEugene Leviantdefine <4 x float> @addv_f32(<4 x float>, <4 x float>) { 246bc35a93SEugene Leviant %3 = fadd <4 x float> %0, %1 256bc35a93SEugene Leviant ret <4 x float> %3 266bc35a93SEugene Leviant} 27