xref: /llvm-project/llvm/test/CodeGen/ARM/a15-mla.ll (revision 7258735fa0b60dd7800f5b9859aceeee16bb4990)
1*7258735fSSaleem Abdulrasool; RUN: llc -mtriple=arm-eabi -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp %s -o - \
2*7258735fSSaleem Abdulrasool; RUN:  | FileCheck %s
37bd29146SSilviu Baranga
47bd29146SSilviu Baranga; This test checks that the VMLxForwarting feature is disabled for A15.
591ddaa1bSSilviu Baranga; CHECK: fun_a:
67bd29146SSilviu Barangadefine <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{
77bd29146SSilviu Baranga  %1 = add <4 x i32> %x, %y
87bd29146SSilviu Baranga; CHECK-NOT: vmul
97bd29146SSilviu Baranga; CHECK: vmla
107bd29146SSilviu Baranga  %2 = mul <4 x i32> %1, %1
117bd29146SSilviu Baranga  %3 = add <4 x i32> %y, %2
127bd29146SSilviu Baranga  ret <4 x i32> %3
137bd29146SSilviu Baranga}
1491ddaa1bSSilviu Baranga
1591ddaa1bSSilviu Baranga; This tests checks that VMLA FP patterns can be matched in instruction selection when targeting
1691ddaa1bSSilviu Baranga; Cortex-A15.
1791ddaa1bSSilviu Baranga; CHECK: fun_b:
1891ddaa1bSSilviu Barangadefine <4 x float> @fun_b(<4 x float> %x, <4 x float> %y, <4 x float> %z) nounwind{
1991ddaa1bSSilviu Baranga; CHECK: vmla.f32
2091ddaa1bSSilviu Baranga  %t = fmul <4 x float> %x, %y
2191ddaa1bSSilviu Baranga  %r = fadd <4 x float> %t, %z
2291ddaa1bSSilviu Baranga  ret <4 x float> %r
2391ddaa1bSSilviu Baranga}
2491ddaa1bSSilviu Baranga
2591ddaa1bSSilviu Baranga; This tests checks that FP VMLA instructions are not expanded into separate multiply/addition
2691ddaa1bSSilviu Baranga; operations when targeting Cortex-A15.
2791ddaa1bSSilviu Baranga; CHECK: fun_c:
2891ddaa1bSSilviu Barangadefine <4 x float> @fun_c(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %u, <4 x float> %v) nounwind{
2991ddaa1bSSilviu Baranga; CHECK: vmla.f32
3091ddaa1bSSilviu Baranga  %t1 = fmul <4 x float> %x, %y
3191ddaa1bSSilviu Baranga  %r1 = fadd <4 x float> %t1, %z
3291ddaa1bSSilviu Baranga; CHECK: vmla.f32
3391ddaa1bSSilviu Baranga  %t2 = fmul <4 x float> %u, %v
3491ddaa1bSSilviu Baranga  %r2 = fadd <4 x float> %t2, %r1
3591ddaa1bSSilviu Baranga  ret <4 x float> %r2
3691ddaa1bSSilviu Baranga}
3791ddaa1bSSilviu Baranga
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