xref: /llvm-project/llvm/test/Analysis/ValueTracking/numsignbits-from-assume.ll (revision f78610af3feb88f0e1edb2482dc77490fb4cad77) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4define i32 @computeNumSignBits_add1(i32 %in) {
5; CHECK-LABEL: @computeNumSignBits_add1(
6; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[IN:%.*]], 1
7; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[ADD]], 43
8; CHECK-NEXT:    call void @llvm.assume(i1 [[COND]])
9; CHECK-NEXT:    [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
10; CHECK-NEXT:    ret i32 [[SH]]
11;
12  %add = add i32 %in, 1
13  %cond = icmp ule i32 %add, 42
14  call void @llvm.assume(i1 %cond)
15  %sh = shl i32 %add, 3
16  ret i32 %sh
17}
18
19define i32 @computeNumSignBits_add2(i32 %in1, i32 %in2) {
20; CHECK-LABEL: @computeNumSignBits_add2(
21; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[IN1:%.*]], [[IN2:%.*]]
22; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[ADD]], 43
23; CHECK-NEXT:    call void @llvm.assume(i1 [[COND]])
24; CHECK-NEXT:    [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
25; CHECK-NEXT:    ret i32 [[SH]]
26;
27  %add = add i32 %in1, %in2
28  %cond = icmp ule i32 %add, 42
29  call void @llvm.assume(i1 %cond)
30  %sh = shl i32 %add, 3
31  ret i32 %sh
32}
33
34define i32 @computeNumSignBits_sub1(i32 %in) {
35; CHECK-LABEL: @computeNumSignBits_sub1(
36; CHECK-NEXT:    [[SUB:%.*]] = sub i32 1, [[IN:%.*]]
37; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[SUB]], 43
38; CHECK-NEXT:    call void @llvm.assume(i1 [[COND]])
39; CHECK-NEXT:    [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
40; CHECK-NEXT:    ret i32 [[SH]]
41;
42  %sub = sub i32 1, %in
43  %cond = icmp ule i32 %sub, 42
44  call void @llvm.assume(i1 %cond)
45  %sh = shl i32 %sub, 3
46  ret i32 %sh
47}
48
49define i32 @computeNumSignBits_sub2(i32 %in) {
50; CHECK-LABEL: @computeNumSignBits_sub2(
51; CHECK-NEXT:    [[SUB:%.*]] = add nsw i32 [[IN:%.*]], -1
52; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[SUB]], 43
53; CHECK-NEXT:    call void @llvm.assume(i1 [[COND]])
54; CHECK-NEXT:    [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
55; CHECK-NEXT:    ret i32 [[SH]]
56;
57  %sub = sub i32 %in, 1
58  %cond = icmp ule i32 %sub, 42
59  call void @llvm.assume(i1 %cond)
60  %sh = shl i32 %sub, 3
61  ret i32 %sh
62}
63
64define i32 @computeNumSignBits_sub3(i32 %in1, i32 %in2) {
65; CHECK-LABEL: @computeNumSignBits_sub3(
66; CHECK-NEXT:    [[SUB:%.*]] = sub i32 [[IN1:%.*]], [[IN2:%.*]]
67; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[SUB]], 43
68; CHECK-NEXT:    call void @llvm.assume(i1 [[COND]])
69; CHECK-NEXT:    [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
70; CHECK-NEXT:    ret i32 [[SH]]
71;
72  %sub = sub i32 %in1, %in2
73  %cond = icmp ule i32 %sub, 42
74  call void @llvm.assume(i1 %cond)
75  %sh = shl i32 %sub, 3
76  ret i32 %sh
77}
78
79define i32 @computeNumSignBits_mul(i32 %in1, i32 %in2) {
80; CHECK-LABEL: @computeNumSignBits_mul(
81; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[IN1:%.*]], [[IN2:%.*]]
82; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[MUL]], 43
83; CHECK-NEXT:    call void @llvm.assume(i1 [[COND]])
84; CHECK-NEXT:    [[SH:%.*]] = shl nuw nsw i32 [[MUL]], 3
85; CHECK-NEXT:    ret i32 [[SH]]
86;
87  %mul = mul i32 %in1, %in2
88  %cond = icmp ule i32 %mul, 42
89  call void @llvm.assume(i1 %cond)
90  %sh = shl i32 %mul, 3
91  ret i32 %sh
92}
93
94define i32 @computeNumSignBits_select(i32 %in, i1 %s) {
95; CHECK-LABEL: @computeNumSignBits_select(
96; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[S:%.*]], i32 [[IN:%.*]], i32 1
97; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[SEL]], 43
98; CHECK-NEXT:    call void @llvm.assume(i1 [[COND]])
99; CHECK-NEXT:    [[SH:%.*]] = shl nuw nsw i32 [[SEL]], 3
100; CHECK-NEXT:    ret i32 [[SH]]
101;
102  %sel = select i1 %s, i32 %in, i32 1
103  %cond = icmp ule i32 %sel, 42
104  call void @llvm.assume(i1 %cond)
105  %sh = shl i32 %sel, 3
106  ret i32 %sh
107}
108
109declare void @llvm.assume(i1)
110