133d24fe3SLuke Lau; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 2 233d24fe3SLuke Lau; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v | FileCheck %s -check-prefixes=CHECK,RV32 333d24fe3SLuke Lau; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v | FileCheck %s -check-prefixes=CHECK,RV64 4*475890cdSShih-Po Hung; RUN: opt < %s -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=riscv32 -mattr=+v | FileCheck %s -check-prefixes=CHECK-SIZE,RV32-SIZE 5*475890cdSShih-Po Hung; RUN: opt < %s -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=riscv64 -mattr=+v | FileCheck %s -check-prefixes=CHECK-SIZE,RV64-SIZE 633d24fe3SLuke Lau 733d24fe3SLuke Laudefine <8 x i8> @insert_subvector_middle_v8i8(<8 x i8> %v, <8 x i8> %w) { 833d24fe3SLuke Lau; CHECK-LABEL: 'insert_subvector_middle_v8i8' 9f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 10, i32 11, i32 6, i32 7> 100a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %res 1133d24fe3SLuke Lau; 12*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_middle_v8i8' 13*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 10, i32 11, i32 6, i32 7> 14*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %res 15*475890cdSShih-Po Hung; 1633d24fe3SLuke Lau %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 10, i32 11, i32 6, i32 7> 1733d24fe3SLuke Lau ret <8 x i8> %res 1833d24fe3SLuke Lau} 1933d24fe3SLuke Lau 2033d24fe3SLuke Laudefine <8 x i8> @insert_subvector_end_v8i8(<8 x i8> %v, <8 x i8> %w) { 2133d24fe3SLuke Lau; CHECK-LABEL: 'insert_subvector_end_v8i8' 22f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 230a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %res 2433d24fe3SLuke Lau; 25*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_end_v8i8' 26*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 27*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %res 28*475890cdSShih-Po Hung; 2933d24fe3SLuke Lau %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 3033d24fe3SLuke Lau ret <8 x i8> %res 3133d24fe3SLuke Lau} 3233d24fe3SLuke Lau 3333d24fe3SLuke Laudefine <8 x i8> @insert_subvector_end_swapped_v8i8(<8 x i8> %v, <8 x i8> %w) { 3433d24fe3SLuke Lau; CHECK-LABEL: 'insert_subvector_end_swapped_v8i8' 35f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 0, i32 1, i32 2, i32 3> 360a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %res 3733d24fe3SLuke Lau; 38*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_end_swapped_v8i8' 39*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 0, i32 1, i32 2, i32 3> 40*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %res 41*475890cdSShih-Po Hung; 4233d24fe3SLuke Lau %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 0, i32 1, i32 2, i32 3> 4333d24fe3SLuke Lau ret <8 x i8> %res 4433d24fe3SLuke Lau} 4533d24fe3SLuke Lau 4633d24fe3SLuke Laudefine <8 x i8> @insert_subvector_short_v8i8(<8 x i8> %v, <8 x i8> %w) { 4733d24fe3SLuke Lau; CHECK-LABEL: 'insert_subvector_short_v8i8' 48f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7> 490a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %res 5033d24fe3SLuke Lau; 51*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_short_v8i8' 52*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7> 53*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %res 54*475890cdSShih-Po Hung; 5533d24fe3SLuke Lau %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7> 5633d24fe3SLuke Lau ret <8 x i8> %res 5733d24fe3SLuke Lau} 5833d24fe3SLuke Lau 5933d24fe3SLuke Laudefine <8 x i8> @insert_subvector_offset_1_v8i8(<8 x i8> %v, <8 x i8> %w) { 6033d24fe3SLuke Lau; CHECK-LABEL: 'insert_subvector_offset_1_v8i8' 61f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 5, i32 6, i32 7> 620a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %res 6333d24fe3SLuke Lau; 64*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_offset_1_v8i8' 65*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 5, i32 6, i32 7> 66*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %res 67*475890cdSShih-Po Hung; 6833d24fe3SLuke Lau %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 5, i32 6, i32 7> 6933d24fe3SLuke Lau ret <8 x i8> %res 7033d24fe3SLuke Lau} 7133d24fe3SLuke Lau 7233d24fe3SLuke Laudefine <8 x i64> @insert_subvector_offset_1_v8i64(<8 x i64> %v, <8 x i64> %w) { 73f23ea4cbSLuke Lau; CHECK-LABEL: 'insert_subvector_offset_1_v8i64' 74f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 5, i32 6, i32 7> 750a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %res 7633d24fe3SLuke Lau; 77*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_offset_1_v8i64' 78*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 5, i32 6, i32 7> 79*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i64> %res 80*475890cdSShih-Po Hung; 8133d24fe3SLuke Lau %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 5, i32 6, i32 7> 8233d24fe3SLuke Lau ret <8 x i64> %res 8333d24fe3SLuke Lau} 8433d24fe3SLuke Lau 85f23ea4cbSLuke Lau; FIXME: This is expensive and involves vrgathers and vslideups 86f23ea4cbSLuke Laudefine <12 x i8> @insert_subvector_concat_v6i8(<6 x i8> %x, <6 x i8> %y) { 87f23ea4cbSLuke Lau; CHECK-LABEL: 'insert_subvector_concat_v6i8' 88f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = shufflevector <6 x i8> %x, <6 x i8> %y, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> 890a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <12 x i8> %a 90f23ea4cbSLuke Lau; 91*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_concat_v6i8' 92*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = shufflevector <6 x i8> %x, <6 x i8> %y, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> 93*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <12 x i8> %a 94*475890cdSShih-Po Hung; 95f23ea4cbSLuke Lau %a = shufflevector <6 x i8> %x, <6 x i8> %y, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> 96f23ea4cbSLuke Lau ret <12 x i8> %a 97f23ea4cbSLuke Lau} 98f23ea4cbSLuke Lau 99f23ea4cbSLuke Lau; FIXME: This is a concat is emitted as one vslideup 100f23ea4cbSLuke Laudefine <8 x i8> @insert_subvector_concat_v8i8(<4 x i8> %x, <4 x i8> %y) { 101f23ea4cbSLuke Lau; CHECK-LABEL: 'insert_subvector_concat_v8i8' 102f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = shufflevector <4 x i8> %x, <4 x i8> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 1030a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %a 104f23ea4cbSLuke Lau; 105*475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'insert_subvector_concat_v8i8' 106*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = shufflevector <4 x i8> %x, <4 x i8> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 107*475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %a 108*475890cdSShih-Po Hung; 109f23ea4cbSLuke Lau %a = shufflevector <4 x i8> %x, <4 x i8> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 110f23ea4cbSLuke Lau ret <8 x i8> %a 111f23ea4cbSLuke Lau} 112f23ea4cbSLuke Lau 113f23ea4cbSLuke Lau;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: 114f23ea4cbSLuke Lau; RV32: {{.*}} 115*475890cdSShih-Po Hung; RV32-SIZE: {{.*}} 116f23ea4cbSLuke Lau; RV64: {{.*}} 117*475890cdSShih-Po Hung; RV64-SIZE: {{.*}} 118