xref: /llvm-project/llvm/test/Analysis/CostModel/AMDGPU/fneg.ll (revision 38fffa630ee80163dc65e759392ad29798905679) 
1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
2; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
3; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=SIZE %s
4; END.
5
6define void @fneg_f16() {
7; CHECK-LABEL: 'fneg_f16'
8; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
9; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
10; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
11; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
12; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
13; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x half> undef
14; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
15; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
16; CHECK-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
17;
18; SIZE-LABEL: 'fneg_f16'
19; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
20; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
21; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
22; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
23; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
24; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x half> undef
25; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
26; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
27; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
28;
29  %f16 = fneg half undef
30  %v2f16 = fneg <2 x half> undef
31  %v3f16 = fneg <3 x half> undef
32  %v4f16 = fneg <4 x half> undef
33  %v5f16 = fneg <5 x half> undef
34  %v8f16 = fneg <8 x half> undef
35  %v16f16 = fneg <16 x half> undef
36  %v17f16 = fneg <17 x half> undef
37  ret void
38}
39
40define void @fneg_bf16() {
41; CHECK-LABEL: 'fneg_bf16'
42; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg bfloat undef
43; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x bfloat> undef
44; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x bfloat> undef
45; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x bfloat> undef
46; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x bfloat> undef
47; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x bfloat> undef
48; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x bfloat> undef
49; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x bfloat> undef
50; CHECK-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
51;
52; SIZE-LABEL: 'fneg_bf16'
53; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg bfloat undef
54; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x bfloat> undef
55; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x bfloat> undef
56; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x bfloat> undef
57; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x bfloat> undef
58; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x bfloat> undef
59; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x bfloat> undef
60; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x bfloat> undef
61; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
62;
63  %f16 = fneg bfloat undef
64  %v2f16 = fneg <2 x bfloat> undef
65  %v3f16 = fneg <3 x bfloat> undef
66  %v4f16 = fneg <4 x bfloat> undef
67  %v5f16 = fneg <5 x bfloat> undef
68  %v8f16 = fneg <8 x bfloat> undef
69  %v16f16 = fneg <16 x bfloat> undef
70  %v17f16 = fneg <17 x bfloat> undef
71  ret void
72}
73
74define void @fneg_f32() {
75; CHECK-LABEL: 'fneg_f32'
76; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
77; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
78; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
79; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
80; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
81; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
82; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
83; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32 = fneg <16 x float> undef
84; CHECK-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
85;
86; SIZE-LABEL: 'fneg_f32'
87; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
88; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
89; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
90; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
91; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
92; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
93; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
94; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32 = fneg <16 x float> undef
95; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
96;
97  %f32 = fneg float undef
98  %v2f32 = fneg <2 x float> undef
99  %v3f32 = fneg <3 x float> undef
100  %v4f32 = fneg <4 x float> undef
101  %v5f32 = fneg <5 x float> undef
102  %v8f32 = fneg <8 x float> undef
103  %v9f32 = fneg <9 x float> undef
104  %v16f32 = fneg <16 x float> undef
105  ret void
106}
107
108define void @fneg_f64() {
109; CHECK-LABEL: 'fneg_f64'
110; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
111; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
112; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
113; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
114; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
115; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f64 = fneg <8 x double> undef
116; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f64 = fneg <16 x double> undef
117; CHECK-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
118;
119; SIZE-LABEL: 'fneg_f64'
120; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
121; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
122; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
123; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
124; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
125; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f64 = fneg <8 x double> undef
126; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f64 = fneg <16 x double> undef
127; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
128;
129  %f64 = fneg double undef
130  %v2f64 = fneg <2 x double> undef
131  %v3f64 = fneg <3 x double> undef
132  %v4f64 = fneg <4 x double> undef
133  %v5f64 = fneg <5 x double> undef
134  %v8f64 = fneg <8 x double> undef
135  %v16f64 = fneg <16 x double> undef
136  ret void
137}
138
139define i32 @fneg_idiom(i32 %arg) {
140; CHECK-LABEL: 'fneg_idiom'
141; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
142; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> splat (float -0.000000e+00), undef
143; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> splat (float -0.000000e+00), undef
144; CHECK-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> splat (float -0.000000e+00), undef
145; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double -0.000000e+00, undef
146; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = fsub <2 x double> splat (double -0.000000e+00), undef
147; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V4F64 = fsub <4 x double> splat (double -0.000000e+00), undef
148; CHECK-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V8F64 = fsub <8 x double> splat (double -0.000000e+00), undef
149; CHECK-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
150;
151; SIZE-LABEL: 'fneg_idiom'
152; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
153; SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> splat (float -0.000000e+00), undef
154; SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> splat (float -0.000000e+00), undef
155; SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> splat (float -0.000000e+00), undef
156; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %F64 = fsub double -0.000000e+00, undef
157; SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> splat (double -0.000000e+00), undef
158; SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fsub <4 x double> splat (double -0.000000e+00), undef
159; SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V8F64 = fsub <8 x double> splat (double -0.000000e+00), undef
160; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
161;
162  %F32 = fsub float -0.0, undef
163  %V4F32 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef
164  %V8F32 = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
165  %V16F32 = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
166
167  %F64 = fsub double -0.0, undef
168  %V2F64 = fsub <2 x double> <double -0.0, double -0.0>, undef
169  %V4F64 = fsub <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, undef
170  %V8F64 = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, undef
171
172  ret i32 undef
173}
174