1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the X86SelectionDAGInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstrInfo.h" 15 #include "X86ISelLowering.h" 16 #include "X86RegisterInfo.h" 17 #include "X86Subtarget.h" 18 #include "X86SelectionDAGInfo.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/IR/DerivedTypes.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "x86-selectiondag-info" 26 27 bool X86SelectionDAGInfo::isBaseRegConflictPossible( 28 SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const { 29 // We cannot use TRI->hasBasePointer() until *after* we select all basic 30 // blocks. Legalization may introduce new stack temporaries with large 31 // alignment requirements. Fall back to generic code if there are any 32 // dynamic stack adjustments (hopefully rare) and the base pointer would 33 // conflict if we had to use it. 34 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 35 if (!MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment()) 36 return false; 37 38 const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>( 39 DAG.getSubtarget().getRegisterInfo()); 40 unsigned BaseReg = TRI->getBaseRegister(); 41 for (unsigned R : ClobberSet) 42 if (BaseReg == R) 43 return true; 44 return false; 45 } 46 47 SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset( 48 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 49 SDValue Size, unsigned Align, bool isVolatile, 50 MachinePointerInfo DstPtrInfo) const { 51 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 52 const X86Subtarget &Subtarget = 53 DAG.getMachineFunction().getSubtarget<X86Subtarget>(); 54 55 #ifndef NDEBUG 56 // If the base register might conflict with our physical registers, bail out. 57 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, 58 X86::ECX, X86::EAX, X86::EDI}; 59 assert(!isBaseRegConflictPossible(DAG, ClobberSet)); 60 #endif 61 62 // If to a segment-relative address space, use the default lowering. 63 if (DstPtrInfo.getAddrSpace() >= 256) 64 return SDValue(); 65 66 // If not DWORD aligned or size is more than the threshold, call the library. 67 // The libc version is likely to be faster for these cases. It can use the 68 // address value and run time information about the CPU. 69 if ((Align & 3) != 0 || !ConstantSize || 70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { 71 // Check to see if there is a specialized entry-point for memory zeroing. 72 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 73 74 if (const char *bzeroEntry = V && 75 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) { 76 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 77 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout()); 78 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext()); 79 TargetLowering::ArgListTy Args; 80 TargetLowering::ArgListEntry Entry; 81 Entry.Node = Dst; 82 Entry.Ty = IntPtrTy; 83 Args.push_back(Entry); 84 Entry.Node = Size; 85 Args.push_back(Entry); 86 87 TargetLowering::CallLoweringInfo CLI(DAG); 88 CLI.setDebugLoc(dl) 89 .setChain(Chain) 90 .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), 91 DAG.getExternalSymbol(bzeroEntry, IntPtr), 92 std::move(Args)) 93 .setDiscardResult(); 94 95 std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI); 96 return CallResult.second; 97 } 98 99 // Otherwise have the target-independent code call memset. 100 return SDValue(); 101 } 102 103 uint64_t SizeVal = ConstantSize->getZExtValue(); 104 SDValue InFlag; 105 EVT AVT; 106 SDValue Count; 107 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 108 unsigned BytesLeft = 0; 109 if (ValC) { 110 unsigned ValReg; 111 uint64_t Val = ValC->getZExtValue() & 255; 112 113 // If the value is a constant, then we can potentially use larger sets. 114 switch (Align & 3) { 115 case 2: // WORD aligned 116 AVT = MVT::i16; 117 ValReg = X86::AX; 118 Val = (Val << 8) | Val; 119 break; 120 case 0: // DWORD aligned 121 AVT = MVT::i32; 122 ValReg = X86::EAX; 123 Val = (Val << 8) | Val; 124 Val = (Val << 16) | Val; 125 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 126 AVT = MVT::i64; 127 ValReg = X86::RAX; 128 Val = (Val << 32) | Val; 129 } 130 break; 131 default: // Byte aligned 132 AVT = MVT::i8; 133 ValReg = X86::AL; 134 Count = DAG.getIntPtrConstant(SizeVal, dl); 135 break; 136 } 137 138 if (AVT.bitsGT(MVT::i8)) { 139 unsigned UBytes = AVT.getSizeInBits() / 8; 140 Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl); 141 BytesLeft = SizeVal % UBytes; 142 } 143 144 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), 145 InFlag); 146 InFlag = Chain.getValue(1); 147 } else { 148 AVT = MVT::i8; 149 Count = DAG.getIntPtrConstant(SizeVal, dl); 150 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 151 InFlag = Chain.getValue(1); 152 } 153 154 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, 155 Count, InFlag); 156 InFlag = Chain.getValue(1); 157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, 158 Dst, InFlag); 159 InFlag = Chain.getValue(1); 160 161 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 162 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 163 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops); 164 165 if (BytesLeft) { 166 // Handle the last 1 - 7 bytes. 167 unsigned Offset = SizeVal - BytesLeft; 168 EVT AddrVT = Dst.getValueType(); 169 EVT SizeVT = Size.getValueType(); 170 171 Chain = DAG.getMemset(Chain, dl, 172 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 173 DAG.getConstant(Offset, dl, AddrVT)), 174 Src, 175 DAG.getConstant(BytesLeft, dl, SizeVT), 176 Align, isVolatile, false, 177 DstPtrInfo.getWithOffset(Offset)); 178 } 179 180 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 181 return Chain; 182 } 183 184 SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy( 185 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 186 SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, 187 MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { 188 // This requires the copy size to be a constant, preferably 189 // within a subtarget-specific limit. 190 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 191 const X86Subtarget &Subtarget = 192 DAG.getMachineFunction().getSubtarget<X86Subtarget>(); 193 if (!ConstantSize) 194 return SDValue(); 195 uint64_t SizeVal = ConstantSize->getZExtValue(); 196 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) 197 return SDValue(); 198 199 /// If not DWORD aligned, it is more efficient to call the library. However 200 /// if calling the library is not allowed (AlwaysInline), then soldier on as 201 /// the code generated here is better than the long load-store sequence we 202 /// would otherwise get. 203 if (!AlwaysInline && (Align & 3) != 0) 204 return SDValue(); 205 206 // If to a segment-relative address space, use the default lowering. 207 if (DstPtrInfo.getAddrSpace() >= 256 || 208 SrcPtrInfo.getAddrSpace() >= 256) 209 return SDValue(); 210 211 // If the base register might conflict with our physical registers, bail out. 212 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, 213 X86::ECX, X86::ESI, X86::EDI}; 214 if (isBaseRegConflictPossible(DAG, ClobberSet)) 215 return SDValue(); 216 217 MVT AVT; 218 if (Subtarget.hasFastString()) 219 // If the target has fast strings, then it's at least as fast to use 220 // REP MOVSB instead of REP MOVS{W,D,Q}, and it avoids having to handle 221 // BytesLeft. 222 AVT = MVT::i8; 223 else if (Align & 1) 224 AVT = MVT::i8; 225 else if (Align & 2) 226 AVT = MVT::i16; 227 else if (Align & 4) 228 // DWORD aligned 229 AVT = MVT::i32; 230 else 231 // QWORD aligned 232 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32; 233 234 unsigned UBytes = AVT.getSizeInBits() / 8; 235 unsigned CountVal = SizeVal / UBytes; 236 SDValue Count = DAG.getIntPtrConstant(CountVal, dl); 237 unsigned BytesLeft = SizeVal % UBytes; 238 239 SDValue InFlag; 240 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, 241 Count, InFlag); 242 InFlag = Chain.getValue(1); 243 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, 244 Dst, InFlag); 245 InFlag = Chain.getValue(1); 246 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RSI : X86::ESI, 247 Src, InFlag); 248 InFlag = Chain.getValue(1); 249 250 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 251 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 252 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops); 253 254 SmallVector<SDValue, 4> Results; 255 Results.push_back(RepMovs); 256 if (BytesLeft) { 257 // Handle the last 1 - 7 bytes. 258 unsigned Offset = SizeVal - BytesLeft; 259 EVT DstVT = Dst.getValueType(); 260 EVT SrcVT = Src.getValueType(); 261 EVT SizeVT = Size.getValueType(); 262 Results.push_back(DAG.getMemcpy(Chain, dl, 263 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 264 DAG.getConstant(Offset, dl, 265 DstVT)), 266 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 267 DAG.getConstant(Offset, dl, 268 SrcVT)), 269 DAG.getConstant(BytesLeft, dl, SizeVT), 270 Align, isVolatile, AlwaysInline, false, 271 DstPtrInfo.getWithOffset(Offset), 272 SrcPtrInfo.getWithOffset(Offset))); 273 } 274 275 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results); 276 } 277