1b51b90d6SPhoebe Wang//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===// 2b51b90d6SPhoebe Wang// 3b51b90d6SPhoebe Wang// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4b51b90d6SPhoebe Wang// See https://llvm.org/LICENSE.txt for license information. 5b51b90d6SPhoebe Wang// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6b51b90d6SPhoebe Wang// 7b51b90d6SPhoebe Wang//===----------------------------------------------------------------------===// 8b51b90d6SPhoebe Wang// 9b51b90d6SPhoebe Wang// This file describes the instructions that make up the Intel RAO-INT 10b51b90d6SPhoebe Wang// instruction set. 11b51b90d6SPhoebe Wang// 12b51b90d6SPhoebe Wang//===----------------------------------------------------------------------===// 13b51b90d6SPhoebe Wang 14b51b90d6SPhoebe Wang//===----------------------------------------------------------------------===// 15b51b90d6SPhoebe Wang// RAO-INT instructions 16b51b90d6SPhoebe Wang 17b51b90d6SPhoebe Wangdef SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 18b51b90d6SPhoebe Wang 19b51b90d6SPhoebe Wangdef X86rao_add : SDNode<"X86ISD::AADD", SDTRAOBinaryArith, 20b51b90d6SPhoebe Wang [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 21b51b90d6SPhoebe Wangdef X86rao_or : SDNode<"X86ISD::AOR", SDTRAOBinaryArith, 22b51b90d6SPhoebe Wang [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 23b51b90d6SPhoebe Wangdef X86rao_xor : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith, 24b51b90d6SPhoebe Wang [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 25b51b90d6SPhoebe Wangdef X86rao_and : SDNode<"X86ISD::AAND", SDTRAOBinaryArith, 26b51b90d6SPhoebe Wang [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 27b51b90d6SPhoebe Wang 28*02d56801SXinWang10multiclass RaoInt<string m, string suffix = ""> { 29*02d56801SXinWang10 let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR32:$src2)] in 30*02d56801SXinWang10 def 32mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi32>; 31*02d56801SXinWang10 let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR64:$src2)] in 32*02d56801SXinWang10 def 64mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi64>; 33b51b90d6SPhoebe Wang} 34b51b90d6SPhoebe Wang 35*02d56801SXinWang10let Predicates = [HasRAOINT, NoEGPR] in { 36*02d56801SXinWang10 defm AADD : RaoInt<"add">, T8; 37*02d56801SXinWang10 defm AAND : RaoInt<"and">, T8, PD; 38*02d56801SXinWang10 defm AOR : RaoInt<"or" >, T8, XD; 39*02d56801SXinWang10 defm AXOR : RaoInt<"xor">, T8, XS; 40*02d56801SXinWang10} 41*02d56801SXinWang10 42*02d56801SXinWang10let Predicates = [HasRAOINT, HasEGPR, In64BitMode] in { 43*02d56801SXinWang10 defm AADD : RaoInt<"add", "_EVEX">, EVEX, T_MAP4; 44*02d56801SXinWang10 defm AAND : RaoInt<"and", "_EVEX">, EVEX, T_MAP4, PD; 45*02d56801SXinWang10 defm AOR : RaoInt<"or", "_EVEX">, EVEX, T_MAP4, XD; 46*02d56801SXinWang10 defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS; 47*02d56801SXinWang10} 48