xref: /llvm-project/llvm/lib/Target/X86/X86InsertWait.cpp (revision 3057e850b88e8faf754db02293066e1182da2954)
18fdafb7dSLiu, Chen3 //-  X86Insertwait.cpp - Strict-Fp:Insert wait instruction X87 instructions --//
28fdafb7dSLiu, Chen3 //
38fdafb7dSLiu, Chen3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
48fdafb7dSLiu, Chen3 // See https://llvm.org/LICENSE.txt for license information.
58fdafb7dSLiu, Chen3 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
68fdafb7dSLiu, Chen3 //
78fdafb7dSLiu, Chen3 //===----------------------------------------------------------------------===//
88fdafb7dSLiu, Chen3 //
98fdafb7dSLiu, Chen3 // This file defines the pass which insert x86 wait instructions after each
108fdafb7dSLiu, Chen3 // X87 instructions when strict float is enabled.
118fdafb7dSLiu, Chen3 //
128fdafb7dSLiu, Chen3 // The logic to insert a wait instruction after an X87 instruction is as below:
138fdafb7dSLiu, Chen3 // 1. If the X87 instruction don't raise float exception nor is a load/store
148fdafb7dSLiu, Chen3 //    instruction, or is a x87 control instruction, don't insert wait.
158fdafb7dSLiu, Chen3 // 2. If the X87 instruction is an instruction which the following instruction
168fdafb7dSLiu, Chen3 //    is an X87 exception synchronizing X87 instruction, don't insert wait.
178fdafb7dSLiu, Chen3 // 3. For other situations, insert wait instruction.
188fdafb7dSLiu, Chen3 //
198fdafb7dSLiu, Chen3 //===----------------------------------------------------------------------===//
208fdafb7dSLiu, Chen3 
218fdafb7dSLiu, Chen3 #include "X86.h"
228fdafb7dSLiu, Chen3 #include "X86InstrInfo.h"
238fdafb7dSLiu, Chen3 #include "X86Subtarget.h"
248fdafb7dSLiu, Chen3 #include "llvm/CodeGen/MachineBasicBlock.h"
258fdafb7dSLiu, Chen3 #include "llvm/CodeGen/MachineFunction.h"
268fdafb7dSLiu, Chen3 #include "llvm/CodeGen/MachineFunctionPass.h"
278fdafb7dSLiu, Chen3 #include "llvm/CodeGen/MachineInstr.h"
288fdafb7dSLiu, Chen3 #include "llvm/CodeGen/MachineInstrBuilder.h"
298fdafb7dSLiu, Chen3 #include "llvm/CodeGen/MachineOperand.h"
308fdafb7dSLiu, Chen3 #include "llvm/IR/DebugLoc.h"
318fdafb7dSLiu, Chen3 #include "llvm/Support/Debug.h"
328fdafb7dSLiu, Chen3 
338fdafb7dSLiu, Chen3 using namespace llvm;
348fdafb7dSLiu, Chen3 
358fdafb7dSLiu, Chen3 #define DEBUG_TYPE "x86-insert-wait"
368fdafb7dSLiu, Chen3 
378fdafb7dSLiu, Chen3 namespace {
388fdafb7dSLiu, Chen3 
398fdafb7dSLiu, Chen3 class WaitInsert : public MachineFunctionPass {
408fdafb7dSLiu, Chen3 public:
418fdafb7dSLiu, Chen3   static char ID;
428fdafb7dSLiu, Chen3 
WaitInsert()438fdafb7dSLiu, Chen3   WaitInsert() : MachineFunctionPass(ID) {}
448fdafb7dSLiu, Chen3 
458fdafb7dSLiu, Chen3   bool runOnMachineFunction(MachineFunction &MF) override;
468fdafb7dSLiu, Chen3 
getPassName() const478fdafb7dSLiu, Chen3   StringRef getPassName() const override {
488fdafb7dSLiu, Chen3     return "X86 insert wait instruction";
498fdafb7dSLiu, Chen3   }
508fdafb7dSLiu, Chen3 };
518fdafb7dSLiu, Chen3 
528fdafb7dSLiu, Chen3 } // namespace
538fdafb7dSLiu, Chen3 
548fdafb7dSLiu, Chen3 char WaitInsert::ID = 0;
558fdafb7dSLiu, Chen3 
createX86InsertX87waitPass()568fdafb7dSLiu, Chen3 FunctionPass *llvm::createX86InsertX87waitPass() { return new WaitInsert(); }
578fdafb7dSLiu, Chen3 
isX87ControlInstruction(MachineInstr & MI)588fdafb7dSLiu, Chen3 static bool isX87ControlInstruction(MachineInstr &MI) {
598fdafb7dSLiu, Chen3   switch (MI.getOpcode()) {
608fdafb7dSLiu, Chen3   case X86::FNINIT:
618fdafb7dSLiu, Chen3   case X86::FLDCW16m:
628fdafb7dSLiu, Chen3   case X86::FNSTCW16m:
638fdafb7dSLiu, Chen3   case X86::FNSTSW16r:
648fdafb7dSLiu, Chen3   case X86::FNSTSWm:
658fdafb7dSLiu, Chen3   case X86::FNCLEX:
668fdafb7dSLiu, Chen3   case X86::FLDENVm:
678fdafb7dSLiu, Chen3   case X86::FSTENVm:
688fdafb7dSLiu, Chen3   case X86::FRSTORm:
698fdafb7dSLiu, Chen3   case X86::FSAVEm:
708fdafb7dSLiu, Chen3   case X86::FINCSTP:
718fdafb7dSLiu, Chen3   case X86::FDECSTP:
728fdafb7dSLiu, Chen3   case X86::FFREE:
738fdafb7dSLiu, Chen3   case X86::FFREEP:
748fdafb7dSLiu, Chen3   case X86::FNOP:
758fdafb7dSLiu, Chen3   case X86::WAIT:
768fdafb7dSLiu, Chen3     return true;
778fdafb7dSLiu, Chen3   default:
788fdafb7dSLiu, Chen3     return false;
798fdafb7dSLiu, Chen3   }
808fdafb7dSLiu, Chen3 }
818fdafb7dSLiu, Chen3 
isX87NonWaitingControlInstruction(MachineInstr & MI)828fdafb7dSLiu, Chen3 static bool isX87NonWaitingControlInstruction(MachineInstr &MI) {
838fdafb7dSLiu, Chen3   // a few special control instructions don't perform a wait operation
848fdafb7dSLiu, Chen3   switch (MI.getOpcode()) {
858fdafb7dSLiu, Chen3   case X86::FNINIT:
868fdafb7dSLiu, Chen3   case X86::FNSTSW16r:
878fdafb7dSLiu, Chen3   case X86::FNSTSWm:
888fdafb7dSLiu, Chen3   case X86::FNSTCW16m:
898fdafb7dSLiu, Chen3   case X86::FNCLEX:
908fdafb7dSLiu, Chen3     return true;
918fdafb7dSLiu, Chen3   default:
928fdafb7dSLiu, Chen3     return false;
938fdafb7dSLiu, Chen3   }
948fdafb7dSLiu, Chen3 }
958fdafb7dSLiu, Chen3 
runOnMachineFunction(MachineFunction & MF)968fdafb7dSLiu, Chen3 bool WaitInsert::runOnMachineFunction(MachineFunction &MF) {
978fdafb7dSLiu, Chen3   if (!MF.getFunction().hasFnAttribute(Attribute::StrictFP))
988fdafb7dSLiu, Chen3     return false;
998fdafb7dSLiu, Chen3 
1008fdafb7dSLiu, Chen3   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
101e80605e2SSimon Pilgrim   const X86InstrInfo *TII = ST.getInstrInfo();
1028fdafb7dSLiu, Chen3   bool Changed = false;
1038fdafb7dSLiu, Chen3 
1048fdafb7dSLiu, Chen3   for (MachineBasicBlock &MBB : MF) {
1058fdafb7dSLiu, Chen3     for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
1068fdafb7dSLiu, Chen3       // Jump non X87 instruction.
107*3057e850SSerge Pavlov       if (!X86::isX87Instruction(*MI))
1088fdafb7dSLiu, Chen3         continue;
1098fdafb7dSLiu, Chen3       // If the instruction instruction neither has float exception nor is
1108fdafb7dSLiu, Chen3       // a load/store instruction, or the instruction is x87 control
1118fdafb7dSLiu, Chen3       // instruction, do not insert wait.
1128fdafb7dSLiu, Chen3       if (!(MI->mayRaiseFPException() || MI->mayLoadOrStore()) ||
1138fdafb7dSLiu, Chen3           isX87ControlInstruction(*MI))
1148fdafb7dSLiu, Chen3         continue;
1158fdafb7dSLiu, Chen3       // If the following instruction is an X87 instruction and isn't an X87
1168fdafb7dSLiu, Chen3       // non-waiting control instruction, we can omit insert wait instruction.
1178fdafb7dSLiu, Chen3       MachineBasicBlock::iterator AfterMI = std::next(MI);
118*3057e850SSerge Pavlov       if (AfterMI != MBB.end() && X86::isX87Instruction(*AfterMI) &&
1198fdafb7dSLiu, Chen3           !isX87NonWaitingControlInstruction(*AfterMI))
1208fdafb7dSLiu, Chen3         continue;
1218fdafb7dSLiu, Chen3 
1228fdafb7dSLiu, Chen3       BuildMI(MBB, AfterMI, MI->getDebugLoc(), TII->get(X86::WAIT));
1238fdafb7dSLiu, Chen3       LLVM_DEBUG(dbgs() << "\nInsert wait after:\t" << *MI);
1248fdafb7dSLiu, Chen3       // Jump the newly inserting wait
1258fdafb7dSLiu, Chen3       ++MI;
1268fdafb7dSLiu, Chen3       Changed = true;
1278fdafb7dSLiu, Chen3     }
1288fdafb7dSLiu, Chen3   }
1298fdafb7dSLiu, Chen3   return Changed;
1308fdafb7dSLiu, Chen3 }
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