1 //===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for X86. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 15 16 #include "llvm/CodeGen/RegisterBankInfo.h" 17 18 #define GET_REGBANK_DECLARATIONS 19 #include "X86GenRegisterBank.inc" 20 21 namespace llvm { 22 23 class LLT; 24 25 class X86GenRegisterBankInfo : public RegisterBankInfo { 26 protected: 27 #define GET_TARGET_REGBANK_CLASS 28 #include "X86GenRegisterBank.inc" 29 #define GET_TARGET_REGBANK_INFO_CLASS 30 #include "X86GenRegisterBankInfo.def" 31 32 static RegisterBankInfo::PartialMapping PartMappings[]; 33 static RegisterBankInfo::ValueMapping ValMappings[]; 34 35 static PartialMappingIdx getPartialMappingIdx(const MachineInstr &MI, 36 const LLT &Ty, bool isFP); 37 static const RegisterBankInfo::ValueMapping * 38 getValueMapping(PartialMappingIdx Idx, unsigned NumOperands); 39 }; 40 41 class TargetRegisterInfo; 42 43 /// This class provides the information for the target register banks. 44 class X86RegisterBankInfo final : public X86GenRegisterBankInfo { 45 private: 46 /// Get an instruction mapping. 47 /// \return An InstructionMappings with a statically allocated 48 /// OperandsMapping. 49 const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI, 50 bool isFP) const; 51 52 /// Track the bank of each instruction operand(register) 53 static void 54 getInstrPartialMappingIdxs(const MachineInstr &MI, 55 const MachineRegisterInfo &MRI, const bool isFP, 56 SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx); 57 58 /// Construct the instruction ValueMapping from PartialMappingIdxs 59 /// \return true if mapping succeeded. 60 static bool 61 getInstrValueMapping(const MachineInstr &MI, 62 const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx, 63 SmallVectorImpl<const ValueMapping *> &OpdsMapping); 64 65 // Maximum recursion depth for hasFPConstraints. 66 const unsigned MaxFPRSearchDepth = 2; 67 68 /// \returns true if \p MI only uses and defines FPRs. 69 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI, 70 const TargetRegisterInfo &TRI, 71 unsigned Depth = 0) const; 72 73 /// \returns true if \p MI only uses FPRs. 74 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 75 const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 76 77 /// \returns true if \p MI only defines FPRs. 78 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 79 const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 80 81 public: 82 X86RegisterBankInfo(const TargetRegisterInfo &TRI); 83 84 InstructionMappings 85 getInstrAlternativeMappings(const MachineInstr &MI) const override; 86 87 /// See RegisterBankInfo::applyMapping. 88 void applyMappingImpl(MachineIRBuilder &Builder, 89 const OperandsMapper &OpdMapper) const override; 90 91 const InstructionMapping & 92 getInstrMapping(const MachineInstr &MI) const override; 93 }; 94 95 } // namespace llvm 96 #endif 97