1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssembly.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyTargetMachine.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Transforms/Scalar.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm" 31 32 // Emscripten's asm.js-style exception handling 33 static cl::opt<bool> EnableEmException( 34 "enable-emscripten-cxx-exceptions", 35 cl::desc("WebAssembly Emscripten-style exception handling"), 36 cl::init(false)); 37 38 // Emscripten's asm.js-style setjmp/longjmp handling 39 static cl::opt<bool> EnableEmSjLj( 40 "enable-emscripten-sjlj", 41 cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"), 42 cl::init(false)); 43 44 extern "C" void LLVMInitializeWebAssemblyTarget() { 45 // Register the target. 46 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); 47 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); 48 49 // Register exception handling pass to opt 50 initializeWebAssemblyLowerEmscriptenEHSjLjPass( 51 *PassRegistry::getPassRegistry()); 52 } 53 54 //===----------------------------------------------------------------------===// 55 // WebAssembly Lowering public interface. 56 //===----------------------------------------------------------------------===// 57 58 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 59 if (!RM.hasValue()) 60 return Reloc::PIC_; 61 return *RM; 62 } 63 64 /// Create an WebAssembly architecture model. 65 /// 66 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 67 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 68 const TargetOptions &Options, Optional<Reloc::Model> RM, 69 CodeModel::Model CM, CodeGenOpt::Level OL) 70 : LLVMTargetMachine(T, 71 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 72 : "e-m:e-p:32:32-i64:64-n32:64-S128", 73 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 74 CM, OL), 75 TLOF(make_unique<WebAssemblyTargetObjectFile>()) { 76 // WebAssembly type-checks instructions, but a noreturn function with a return 77 // type that doesn't match the context will cause a check failure. So we lower 78 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 79 // 'unreachable' instructions which is meant for that case. 80 this->Options.TrapUnreachable = true; 81 82 initAsmInfo(); 83 84 // Note that we don't use setRequiresStructuredCFG(true). It disables 85 // optimizations than we're ok with, and want, such as critical edge 86 // splitting and tail merging. 87 } 88 89 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 90 91 const WebAssemblySubtarget * 92 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 93 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 94 Attribute FSAttr = F.getFnAttribute("target-features"); 95 96 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 97 ? CPUAttr.getValueAsString().str() 98 : TargetCPU; 99 std::string FS = !FSAttr.hasAttribute(Attribute::None) 100 ? FSAttr.getValueAsString().str() 101 : TargetFS; 102 103 auto &I = SubtargetMap[CPU + FS]; 104 if (!I) { 105 // This needs to be done before we create a new subtarget since any 106 // creation will depend on the TM and the code generation flags on the 107 // function that reside in TargetOptions. 108 resetTargetOptions(F); 109 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 110 } 111 return I.get(); 112 } 113 114 namespace { 115 /// WebAssembly Code Generator Pass Configuration Options. 116 class WebAssemblyPassConfig final : public TargetPassConfig { 117 public: 118 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM) 119 : TargetPassConfig(TM, PM) {} 120 121 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 122 return getTM<WebAssemblyTargetMachine>(); 123 } 124 125 FunctionPass *createTargetRegisterAllocator(bool) override; 126 127 void addIRPasses() override; 128 bool addInstSelector() override; 129 void addPostRegAlloc() override; 130 bool addGCPasses() override { return false; } 131 void addPreEmitPass() override; 132 }; 133 } // end anonymous namespace 134 135 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 136 return TargetIRAnalysis([this](const Function &F) { 137 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 138 }); 139 } 140 141 TargetPassConfig * 142 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 143 return new WebAssemblyPassConfig(this, PM); 144 } 145 146 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 147 return nullptr; // No reg alloc 148 } 149 150 //===----------------------------------------------------------------------===// 151 // The following functions are called from lib/CodeGen/Passes.cpp to modify 152 // the CodeGen pass sequence. 153 //===----------------------------------------------------------------------===// 154 155 void WebAssemblyPassConfig::addIRPasses() { 156 if (TM->Options.ThreadModel == ThreadModel::Single) 157 // In "single" mode, atomics get lowered to non-atomics. 158 addPass(createLowerAtomicPass()); 159 else 160 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 161 // control specifically what gets lowered. 162 addPass(createAtomicExpandPass(TM)); 163 164 // Optimize "returned" function attributes. 165 if (getOptLevel() != CodeGenOpt::None) 166 addPass(createWebAssemblyOptimizeReturned()); 167 168 // If exception handling is not enabled and setjmp/longjmp handling is 169 // enabled, we lower invokes into calls and delete unreachable landingpad 170 // blocks. Lowering invokes when there is no EH support is done in 171 // TargetPassConfig::addPassesToHandleExceptions, but this runs after this 172 // function and SjLj handling expects all invokes to be lowered before. 173 if (!EnableEmException) { 174 addPass(createLowerInvokePass()); 175 // The lower invoke pass may create unreachable code. Remove it in order not 176 // to process dead blocks in setjmp/longjmp handling. 177 addPass(createUnreachableBlockEliminationPass()); 178 } 179 180 // Handle exceptions and setjmp/longjmp if enabled. 181 if (EnableEmException || EnableEmSjLj) 182 addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException, 183 EnableEmSjLj)); 184 185 TargetPassConfig::addIRPasses(); 186 } 187 188 bool WebAssemblyPassConfig::addInstSelector() { 189 (void)TargetPassConfig::addInstSelector(); 190 addPass( 191 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 192 // Run the argument-move pass immediately after the ScheduleDAG scheduler 193 // so that we can fix up the ARGUMENT instructions before anything else 194 // sees them in the wrong place. 195 addPass(createWebAssemblyArgumentMove()); 196 // Set the p2align operands. This information is present during ISel, however 197 // it's inconvenient to collect. Collect it now, and update the immediate 198 // operands. 199 addPass(createWebAssemblySetP2AlignOperands()); 200 return false; 201 } 202 203 void WebAssemblyPassConfig::addPostRegAlloc() { 204 // TODO: The following CodeGen passes don't currently support code containing 205 // virtual registers. Consider removing their restrictions and re-enabling 206 // them. 207 208 // Has no asserts of its own, but was not written to handle virtual regs. 209 disablePass(&ShrinkWrapID); 210 211 // These functions all require the NoVRegs property. 212 disablePass(&MachineCopyPropagationID); 213 disablePass(&PostRASchedulerID); 214 disablePass(&FuncletLayoutID); 215 disablePass(&StackMapLivenessID); 216 disablePass(&LiveDebugValuesID); 217 disablePass(&PatchableFunctionID); 218 219 TargetPassConfig::addPostRegAlloc(); 220 } 221 222 void WebAssemblyPassConfig::addPreEmitPass() { 223 TargetPassConfig::addPreEmitPass(); 224 225 // Now that we have a prologue and epilogue and all frame indices are 226 // rewritten, eliminate SP and FP. This allows them to be stackified, 227 // colored, and numbered with the rest of the registers. 228 addPass(createWebAssemblyReplacePhysRegs()); 229 230 if (getOptLevel() != CodeGenOpt::None) { 231 // LiveIntervals isn't commonly run this late. Re-establish preconditions. 232 addPass(createWebAssemblyPrepareForLiveIntervals()); 233 234 // Depend on LiveIntervals and perform some optimizations on it. 235 addPass(createWebAssemblyOptimizeLiveIntervals()); 236 237 // Prepare store instructions for register stackifying. 238 addPass(createWebAssemblyStoreResults()); 239 240 // Mark registers as representing wasm's value stack. This is a key 241 // code-compression technique in WebAssembly. We run this pass (and 242 // StoreResults above) very late, so that it sees as much code as possible, 243 // including code emitted by PEI and expanded by late tail duplication. 244 addPass(createWebAssemblyRegStackify()); 245 246 // Run the register coloring pass to reduce the total number of registers. 247 // This runs after stackification so that it doesn't consider registers 248 // that become stackified. 249 addPass(createWebAssemblyRegColoring()); 250 } 251 252 // Eliminate multiple-entry loops. 253 addPass(createWebAssemblyFixIrreducibleControlFlow()); 254 255 // Put the CFG in structured form; insert BLOCK and LOOP markers. 256 addPass(createWebAssemblyCFGStackify()); 257 258 // Lower br_unless into br_if. 259 addPass(createWebAssemblyLowerBrUnless()); 260 261 // Perform the very last peephole optimizations on the code. 262 if (getOptLevel() != CodeGenOpt::None) 263 addPass(createWebAssemblyPeephole()); 264 265 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 266 addPass(createWebAssemblyRegNumbering()); 267 } 268