1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssembly.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyTargetMachine.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Target/TargetOptions.h" 26 #include "llvm/Transforms/Scalar.h" 27 using namespace llvm; 28 29 #define DEBUG_TYPE "wasm" 30 31 extern "C" void LLVMInitializeWebAssemblyTarget() { 32 // Register the target. 33 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); 34 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); 35 } 36 37 //===----------------------------------------------------------------------===// 38 // WebAssembly Lowering public interface. 39 //===----------------------------------------------------------------------===// 40 41 /// Create an WebAssembly architecture model. 42 /// 43 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 44 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 45 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 46 CodeGenOpt::Level OL) 47 : LLVMTargetMachine(T, 48 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 49 : "e-m:e-p:32:32-i64:64-n32:64-S128", 50 TT, CPU, FS, Options, RM, CM, OL), 51 TLOF(make_unique<WebAssemblyTargetObjectFile>()) { 52 // WebAssembly type-checks expressions, but a noreturn function with a return 53 // type that doesn't match the context will cause a check failure. So we lower 54 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 55 // 'unreachable' expression which is meant for that case. 56 this->Options.TrapUnreachable = true; 57 58 initAsmInfo(); 59 60 // Note that we don't use setRequiresStructuredCFG(true). It disables 61 // optimizations than we're ok with, and want, such as critical edge 62 // splitting and tail merging. 63 } 64 65 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 66 67 const WebAssemblySubtarget * 68 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 69 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 70 Attribute FSAttr = F.getFnAttribute("target-features"); 71 72 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 73 ? CPUAttr.getValueAsString().str() 74 : TargetCPU; 75 std::string FS = !FSAttr.hasAttribute(Attribute::None) 76 ? FSAttr.getValueAsString().str() 77 : TargetFS; 78 79 auto &I = SubtargetMap[CPU + FS]; 80 if (!I) { 81 // This needs to be done before we create a new subtarget since any 82 // creation will depend on the TM and the code generation flags on the 83 // function that reside in TargetOptions. 84 resetTargetOptions(F); 85 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 86 } 87 return I.get(); 88 } 89 90 namespace { 91 /// WebAssembly Code Generator Pass Configuration Options. 92 class WebAssemblyPassConfig final : public TargetPassConfig { 93 public: 94 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM) 95 : TargetPassConfig(TM, PM) {} 96 97 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 98 return getTM<WebAssemblyTargetMachine>(); 99 } 100 101 FunctionPass *createTargetRegisterAllocator(bool) override; 102 103 void addIRPasses() override; 104 bool addInstSelector() override; 105 bool addILPOpts() override; 106 void addPreRegAlloc() override; 107 void addPostRegAlloc() override; 108 bool addGCPasses() override { return false; } 109 void addPreEmitPass() override; 110 }; 111 } // end anonymous namespace 112 113 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 114 return TargetIRAnalysis([this](const Function &F) { 115 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 116 }); 117 } 118 119 TargetPassConfig * 120 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 121 return new WebAssemblyPassConfig(this, PM); 122 } 123 124 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 125 return nullptr; // No reg alloc 126 } 127 128 //===----------------------------------------------------------------------===// 129 // The following functions are called from lib/CodeGen/Passes.cpp to modify 130 // the CodeGen pass sequence. 131 //===----------------------------------------------------------------------===// 132 133 void WebAssemblyPassConfig::addIRPasses() { 134 if (TM->Options.ThreadModel == ThreadModel::Single) 135 // In "single" mode, atomics get lowered to non-atomics. 136 addPass(createLowerAtomicPass()); 137 else 138 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 139 // control specifically what gets lowered. 140 addPass(createAtomicExpandPass(TM)); 141 142 // Optimize "returned" function attributes. 143 if (getOptLevel() != CodeGenOpt::None) 144 addPass(createWebAssemblyOptimizeReturned()); 145 146 TargetPassConfig::addIRPasses(); 147 } 148 149 bool WebAssemblyPassConfig::addInstSelector() { 150 (void)TargetPassConfig::addInstSelector(); 151 addPass( 152 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 153 // Run the argument-move pass immediately after the ScheduleDAG scheduler 154 // so that we can fix up the ARGUMENT instructions before anything else 155 // sees them in the wrong place. 156 addPass(createWebAssemblyArgumentMove()); 157 // Set the p2align operands. This information is present during ISel, however 158 // it's inconvenient to collect. Collect it now, and update the immediate 159 // operands. 160 addPass(createWebAssemblySetP2AlignOperands()); 161 return false; 162 } 163 164 bool WebAssemblyPassConfig::addILPOpts() { 165 (void)TargetPassConfig::addILPOpts(); 166 return true; 167 } 168 169 void WebAssemblyPassConfig::addPreRegAlloc() { 170 TargetPassConfig::addPreRegAlloc(); 171 172 // Prepare store instructions for register stackifying. 173 if (getOptLevel() != CodeGenOpt::None) 174 addPass(createWebAssemblyStoreResults()); 175 } 176 177 void WebAssemblyPassConfig::addPostRegAlloc() { 178 // TODO: The following CodeGen passes don't currently support code containing 179 // virtual registers. Consider removing their restrictions and re-enabling 180 // them. 181 182 // Has no asserts of its own, but was not written to handle virtual regs. 183 disablePass(&ShrinkWrapID); 184 // We use our own PrologEpilogInserter which is very slightly modified to 185 // tolerate virtual registers. 186 disablePass(&PrologEpilogCodeInserterID); 187 188 // These functions all require the AllVRegsAllocated property. 189 disablePass(&MachineCopyPropagationID); 190 disablePass(&PostRASchedulerID); 191 disablePass(&FuncletLayoutID); 192 disablePass(&StackMapLivenessID); 193 disablePass(&LiveDebugValuesID); 194 195 if (getOptLevel() != CodeGenOpt::None) { 196 // Mark registers as representing wasm's expression stack. 197 addPass(createWebAssemblyRegStackify()); 198 199 // Run the register coloring pass to reduce the total number of registers. 200 addPass(createWebAssemblyRegColoring()); 201 } 202 203 TargetPassConfig::addPostRegAlloc(); 204 205 // Run WebAssembly's version of the PrologEpilogInserter. Target-independent 206 // PEI runs after PostRegAlloc and after ShrinkWrap. Putting it here will run 207 // PEI before ShrinkWrap but otherwise in the same position in the order. 208 addPass(createWebAssemblyPEI()); 209 } 210 211 void WebAssemblyPassConfig::addPreEmitPass() { 212 TargetPassConfig::addPreEmitPass(); 213 214 // Eliminate multiple-entry loops. 215 addPass(createWebAssemblyFixIrreducibleControlFlow()); 216 217 // Put the CFG in structured form; insert BLOCK and LOOP markers. 218 addPass(createWebAssemblyCFGStackify()); 219 220 // Lower br_unless into br_if. 221 addPass(createWebAssemblyLowerBrUnless()); 222 223 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 224 addPass(createWebAssemblyRegNumbering()); 225 226 // Perform the very last peephole optimizations on the code. 227 if (getOptLevel() != CodeGenOpt::None) 228 addPass(createWebAssemblyPeephole()); 229 } 230