1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssembly.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyTargetMachine.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/CommandLine.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Target/TargetOptions.h" 28 #include "llvm/Transforms/Scalar.h" 29 using namespace llvm; 30 31 #define DEBUG_TYPE "wasm" 32 33 extern "C" void LLVMInitializeWebAssemblyTarget() { 34 // Register the target. 35 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); 36 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); 37 } 38 39 //===----------------------------------------------------------------------===// 40 // WebAssembly Lowering public interface. 41 //===----------------------------------------------------------------------===// 42 43 /// Create an WebAssembly architecture model. 44 /// 45 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 46 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 47 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 48 CodeGenOpt::Level OL) 49 : LLVMTargetMachine(T, TT.isArch64Bit() 50 ? "e-p:64:64-i64:64-n32:64-S128" 51 : "e-p:32:32-i64:64-n32:64-S128", 52 TT, CPU, FS, Options, RM, CM, OL), 53 TLOF(make_unique<WebAssemblyTargetObjectFile>()) { 54 // WebAssembly type-checks expressions, but a noreturn function with a return 55 // type that doesn't match the context will cause a check failure. So we lower 56 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 57 // 'unreachable' expression which is meant for that case. 58 this->Options.TrapUnreachable = true; 59 60 initAsmInfo(); 61 62 // We need a reducible CFG, so disable some optimizations which tend to 63 // introduce irreducibility. 64 setRequiresStructuredCFG(true); 65 } 66 67 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 68 69 const WebAssemblySubtarget * 70 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 71 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 72 Attribute FSAttr = F.getFnAttribute("target-features"); 73 74 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 75 ? CPUAttr.getValueAsString().str() 76 : TargetCPU; 77 std::string FS = !FSAttr.hasAttribute(Attribute::None) 78 ? FSAttr.getValueAsString().str() 79 : TargetFS; 80 81 auto &I = SubtargetMap[CPU + FS]; 82 if (!I) { 83 // This needs to be done before we create a new subtarget since any 84 // creation will depend on the TM and the code generation flags on the 85 // function that reside in TargetOptions. 86 resetTargetOptions(F); 87 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 88 } 89 return I.get(); 90 } 91 92 namespace { 93 /// WebAssembly Code Generator Pass Configuration Options. 94 class WebAssemblyPassConfig final : public TargetPassConfig { 95 public: 96 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM) 97 : TargetPassConfig(TM, PM) {} 98 99 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 100 return getTM<WebAssemblyTargetMachine>(); 101 } 102 103 FunctionPass *createTargetRegisterAllocator(bool) override; 104 105 void addIRPasses() override; 106 bool addPreISel() override; 107 bool addInstSelector() override; 108 bool addILPOpts() override; 109 void addPreRegAlloc() override; 110 void addPostRegAlloc() override; 111 void addPreSched2() override; 112 void addPreEmitPass() override; 113 }; 114 } // end anonymous namespace 115 116 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 117 return TargetIRAnalysis([this](const Function &F) { 118 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 119 }); 120 } 121 122 TargetPassConfig * 123 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 124 return new WebAssemblyPassConfig(this, PM); 125 } 126 127 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 128 return nullptr; // No reg alloc 129 } 130 131 //===----------------------------------------------------------------------===// 132 // The following functions are called from lib/CodeGen/Passes.cpp to modify 133 // the CodeGen pass sequence. 134 //===----------------------------------------------------------------------===// 135 136 void WebAssemblyPassConfig::addIRPasses() { 137 if (TM->Options.ThreadModel == ThreadModel::Single) 138 // In "single" mode, atomics get lowered to non-atomics. 139 addPass(createLowerAtomicPass()); 140 else 141 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 142 // control specifically what gets lowered. 143 addPass(createAtomicExpandPass(TM)); 144 145 // Optimize "returned" function attributes. 146 addPass(createWebAssemblyOptimizeReturned()); 147 148 TargetPassConfig::addIRPasses(); 149 } 150 151 bool WebAssemblyPassConfig::addPreISel() { return false; } 152 153 bool WebAssemblyPassConfig::addInstSelector() { 154 addPass( 155 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 156 return false; 157 } 158 159 bool WebAssemblyPassConfig::addILPOpts() { return true; } 160 161 void WebAssemblyPassConfig::addPreRegAlloc() { 162 // Prepare store instructions for register stackifying. 163 addPass(createWebAssemblyStoreResults()); 164 165 // Mark registers as representing wasm's expression stack. 166 addPass(createWebAssemblyRegStackify()); 167 } 168 169 void WebAssemblyPassConfig::addPostRegAlloc() { 170 // TODO: The following CodeGen passes don't currently support code containing 171 // virtual registers. Consider removing their restrictions and re-enabling 172 // them. 173 // 174 // Fails with: Regalloc must assign all vregs. 175 disablePass(&PrologEpilogCodeInserterID); 176 // Fails with: should be run after register allocation. 177 disablePass(&MachineCopyPropagationID); 178 179 // TODO: Until we get ReverseBranchCondition support, MachineBlockPlacement 180 // can create ugly-looking control flow. 181 disablePass(&MachineBlockPlacementID); 182 183 // Run the register coloring pass to reduce the total number of registers. 184 addPass(createWebAssemblyRegColoring()); 185 } 186 187 void WebAssemblyPassConfig::addPreSched2() {} 188 189 void WebAssemblyPassConfig::addPreEmitPass() { 190 addPass(createWebAssemblyCFGStackify()); 191 addPass(createWebAssemblyRegNumbering()); 192 addPass(createWebAssemblyPeephole()); 193 } 194