1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssembly.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyTargetMachine.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Transforms/Scalar.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm" 31 32 extern "C" void LLVMInitializeWebAssemblyTarget() { 33 // Register the target. 34 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); 35 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); 36 } 37 38 //===----------------------------------------------------------------------===// 39 // WebAssembly Lowering public interface. 40 //===----------------------------------------------------------------------===// 41 42 /// Create an WebAssembly architecture model. 43 /// 44 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 45 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 46 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 47 CodeGenOpt::Level OL) 48 : LLVMTargetMachine(T, TT.isArch64Bit() 49 ? "e-p:64:64-i64:64-n32:64-S128" 50 : "e-p:32:32-i64:64-n32:64-S128", 51 TT, CPU, FS, Options, RM, CM, OL), 52 TLOF(make_unique<WebAssemblyTargetObjectFile>()) { 53 // WebAssembly type-checks expressions, but a noreturn function with a return 54 // type that doesn't match the context will cause a check failure. So we lower 55 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 56 // 'unreachable' expression which is meant for that case. 57 this->Options.TrapUnreachable = true; 58 59 initAsmInfo(); 60 61 // We need a reducible CFG, so disable some optimizations which tend to 62 // introduce irreducibility. 63 setRequiresStructuredCFG(true); 64 } 65 66 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 67 68 const WebAssemblySubtarget * 69 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 70 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 71 Attribute FSAttr = F.getFnAttribute("target-features"); 72 73 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 74 ? CPUAttr.getValueAsString().str() 75 : TargetCPU; 76 std::string FS = !FSAttr.hasAttribute(Attribute::None) 77 ? FSAttr.getValueAsString().str() 78 : TargetFS; 79 80 auto &I = SubtargetMap[CPU + FS]; 81 if (!I) { 82 // This needs to be done before we create a new subtarget since any 83 // creation will depend on the TM and the code generation flags on the 84 // function that reside in TargetOptions. 85 resetTargetOptions(F); 86 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 87 } 88 return I.get(); 89 } 90 91 namespace { 92 /// WebAssembly Code Generator Pass Configuration Options. 93 class WebAssemblyPassConfig final : public TargetPassConfig { 94 public: 95 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM) 96 : TargetPassConfig(TM, PM) {} 97 98 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 99 return getTM<WebAssemblyTargetMachine>(); 100 } 101 102 FunctionPass *createTargetRegisterAllocator(bool) override; 103 104 void addIRPasses() override; 105 bool addPreISel() override; 106 bool addInstSelector() override; 107 bool addILPOpts() override; 108 void addPreRegAlloc() override; 109 void addPostRegAlloc() override; 110 void addPreSched2() override; 111 void addPreEmitPass() override; 112 }; 113 } // end anonymous namespace 114 115 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 116 return TargetIRAnalysis([this](const Function &F) { 117 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 118 }); 119 } 120 121 TargetPassConfig * 122 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 123 return new WebAssemblyPassConfig(this, PM); 124 } 125 126 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 127 return nullptr; // No reg alloc 128 } 129 130 //===----------------------------------------------------------------------===// 131 // The following functions are called from lib/CodeGen/Passes.cpp to modify 132 // the CodeGen pass sequence. 133 //===----------------------------------------------------------------------===// 134 135 void WebAssemblyPassConfig::addIRPasses() { 136 // FIXME: the default for this option is currently POSIX, whereas 137 // WebAssembly's MVP should default to Single. 138 if (TM->Options.ThreadModel == ThreadModel::Single) 139 addPass(createLowerAtomicPass()); 140 else 141 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 142 // control specifically what gets lowered. 143 addPass(createAtomicExpandPass(TM)); 144 145 TargetPassConfig::addIRPasses(); 146 } 147 148 bool WebAssemblyPassConfig::addPreISel() { return false; } 149 150 bool WebAssemblyPassConfig::addInstSelector() { 151 addPass( 152 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 153 return false; 154 } 155 156 bool WebAssemblyPassConfig::addILPOpts() { return true; } 157 158 void WebAssemblyPassConfig::addPreRegAlloc() {} 159 160 void WebAssemblyPassConfig::addPostRegAlloc() { 161 // FIXME: the following passes dislike virtual registers. Disable them for now 162 // so that basic tests can pass. Future patches will remedy this. 163 // 164 // Fails with: Regalloc must assign all vregs. 165 disablePass(&PrologEpilogCodeInserterID); 166 // Fails with: should be run after register allocation. 167 disablePass(&MachineCopyPropagationID); 168 169 // TODO: Until we get ReverseBranchCondition support, MachineBlockPlacement 170 // can create ugly-looking control flow. 171 disablePass(&MachineBlockPlacementID); 172 } 173 174 void WebAssemblyPassConfig::addPreSched2() {} 175 176 void WebAssemblyPassConfig::addPreEmitPass() { 177 addPass(createWebAssemblyCFGStackify()); 178 } 179