1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssemblyTargetMachine.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssembly.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Transforms/Scalar.h" 28 #include "llvm/Transforms/Utils.h" 29 using namespace llvm; 30 31 #define DEBUG_TYPE "wasm" 32 33 // Emscripten's asm.js-style exception handling 34 static cl::opt<bool> EnableEmException( 35 "enable-emscripten-cxx-exceptions", 36 cl::desc("WebAssembly Emscripten-style exception handling"), 37 cl::init(false)); 38 39 // Emscripten's asm.js-style setjmp/longjmp handling 40 static cl::opt<bool> EnableEmSjLj( 41 "enable-emscripten-sjlj", 42 cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"), 43 cl::init(false)); 44 45 extern "C" void LLVMInitializeWebAssemblyTarget() { 46 // Register the target. 47 RegisterTargetMachine<WebAssemblyTargetMachine> X( 48 getTheWebAssemblyTarget32()); 49 RegisterTargetMachine<WebAssemblyTargetMachine> Y( 50 getTheWebAssemblyTarget64()); 51 52 // Register backend passes 53 auto &PR = *PassRegistry::getPassRegistry(); 54 initializeWebAssemblyLowerEmscriptenEHSjLjPass(PR); 55 initializeLowerGlobalDtorsPass(PR); 56 initializeFixFunctionBitcastsPass(PR); 57 initializeOptimizeReturnedPass(PR); 58 initializeWebAssemblyArgumentMovePass(PR); 59 initializeWebAssemblySetP2AlignOperandsPass(PR); 60 initializeWebAssemblyReplacePhysRegsPass(PR); 61 initializeWebAssemblyPrepareForLiveIntervalsPass(PR); 62 initializeWebAssemblyOptimizeLiveIntervalsPass(PR); 63 initializeWebAssemblyStoreResultsPass(PR); 64 initializeWebAssemblyRegStackifyPass(PR); 65 initializeWebAssemblyRegColoringPass(PR); 66 initializeWebAssemblyExplicitLocalsPass(PR); 67 initializeWebAssemblyFixIrreducibleControlFlowPass(PR); 68 initializeWebAssemblyLateEHPreparePass(PR); 69 initializeWebAssemblyCFGSortPass(PR); 70 initializeWebAssemblyCFGStackifyPass(PR); 71 initializeWebAssemblyLowerBrUnlessPass(PR); 72 initializeWebAssemblyRegNumberingPass(PR); 73 initializeWebAssemblyPeepholePass(PR); 74 initializeWebAssemblyCallIndirectFixupPass(PR); 75 } 76 77 //===----------------------------------------------------------------------===// 78 // WebAssembly Lowering public interface. 79 //===----------------------------------------------------------------------===// 80 81 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 82 if (!RM.hasValue()) 83 return Reloc::PIC_; 84 return *RM; 85 } 86 87 /// Create an WebAssembly architecture model. 88 /// 89 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 90 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 91 const TargetOptions &Options, Optional<Reloc::Model> RM, 92 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) 93 : LLVMTargetMachine(T, 94 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 95 : "e-m:e-p:32:32-i64:64-n32:64-S128", 96 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 97 CM ? *CM : CodeModel::Large, OL), 98 TLOF(TT.isOSBinFormatELF() ? 99 static_cast<TargetLoweringObjectFile*>( 100 new WebAssemblyTargetObjectFileELF()) : 101 static_cast<TargetLoweringObjectFile*>( 102 new WebAssemblyTargetObjectFile())) { 103 // WebAssembly type-checks instructions, but a noreturn function with a return 104 // type that doesn't match the context will cause a check failure. So we lower 105 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 106 // 'unreachable' instructions which is meant for that case. 107 this->Options.TrapUnreachable = true; 108 109 // WebAssembly treats each function as an independent unit. Force 110 // -ffunction-sections, effectively, so that we can emit them independently. 111 if (!TT.isOSBinFormatELF()) { 112 this->Options.FunctionSections = true; 113 this->Options.DataSections = true; 114 this->Options.UniqueSectionNames = true; 115 } 116 117 initAsmInfo(); 118 119 // Note that we don't use setRequiresStructuredCFG(true). It disables 120 // optimizations than we're ok with, and want, such as critical edge 121 // splitting and tail merging. 122 } 123 124 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 125 126 const WebAssemblySubtarget * 127 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 128 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 129 Attribute FSAttr = F.getFnAttribute("target-features"); 130 131 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 132 ? CPUAttr.getValueAsString().str() 133 : TargetCPU; 134 std::string FS = !FSAttr.hasAttribute(Attribute::None) 135 ? FSAttr.getValueAsString().str() 136 : TargetFS; 137 138 auto &I = SubtargetMap[CPU + FS]; 139 if (!I) { 140 // This needs to be done before we create a new subtarget since any 141 // creation will depend on the TM and the code generation flags on the 142 // function that reside in TargetOptions. 143 resetTargetOptions(F); 144 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 145 } 146 return I.get(); 147 } 148 149 namespace { 150 class StripThreadLocal final : public ModulePass { 151 // The default thread model for wasm is single, where thread-local variables 152 // are identical to regular globals and should be treated the same. So this 153 // pass just converts all GlobalVariables to NotThreadLocal 154 static char ID; 155 156 public: 157 StripThreadLocal() : ModulePass(ID) {} 158 bool runOnModule(Module &M) override { 159 for (auto &GV : M.globals()) 160 GV.setThreadLocalMode(GlobalValue::ThreadLocalMode::NotThreadLocal); 161 return true; 162 } 163 }; 164 char StripThreadLocal::ID = 0; 165 166 /// WebAssembly Code Generator Pass Configuration Options. 167 class WebAssemblyPassConfig final : public TargetPassConfig { 168 public: 169 WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM) 170 : TargetPassConfig(TM, PM) {} 171 172 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 173 return getTM<WebAssemblyTargetMachine>(); 174 } 175 176 FunctionPass *createTargetRegisterAllocator(bool) override; 177 178 void addIRPasses() override; 179 bool addInstSelector() override; 180 void addPostRegAlloc() override; 181 bool addGCPasses() override { return false; } 182 void addPreEmitPass() override; 183 }; 184 } // end anonymous namespace 185 186 TargetTransformInfo 187 WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) { 188 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 189 } 190 191 TargetPassConfig * 192 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 193 return new WebAssemblyPassConfig(*this, PM); 194 } 195 196 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 197 return nullptr; // No reg alloc 198 } 199 200 //===----------------------------------------------------------------------===// 201 // The following functions are called from lib/CodeGen/Passes.cpp to modify 202 // the CodeGen pass sequence. 203 //===----------------------------------------------------------------------===// 204 205 void WebAssemblyPassConfig::addIRPasses() { 206 if (TM->Options.ThreadModel == ThreadModel::Single) { 207 // In "single" mode, atomics get lowered to non-atomics. 208 addPass(createLowerAtomicPass()); 209 addPass(new StripThreadLocal()); 210 } else { 211 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 212 // control specifically what gets lowered. 213 addPass(createAtomicExpandPass()); 214 } 215 216 // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls. 217 addPass(createWebAssemblyLowerGlobalDtors()); 218 219 // Fix function bitcasts, as WebAssembly requires caller and callee signatures 220 // to match. 221 addPass(createWebAssemblyFixFunctionBitcasts()); 222 223 // Optimize "returned" function attributes. 224 if (getOptLevel() != CodeGenOpt::None) 225 addPass(createWebAssemblyOptimizeReturned()); 226 227 // If exception handling is not enabled and setjmp/longjmp handling is 228 // enabled, we lower invokes into calls and delete unreachable landingpad 229 // blocks. Lowering invokes when there is no EH support is done in 230 // TargetPassConfig::addPassesToHandleExceptions, but this runs after this 231 // function and SjLj handling expects all invokes to be lowered before. 232 if (!EnableEmException && 233 TM->Options.ExceptionModel == ExceptionHandling::None) { 234 addPass(createLowerInvokePass()); 235 // The lower invoke pass may create unreachable code. Remove it in order not 236 // to process dead blocks in setjmp/longjmp handling. 237 addPass(createUnreachableBlockEliminationPass()); 238 } 239 240 // Handle exceptions and setjmp/longjmp if enabled. 241 if (EnableEmException || EnableEmSjLj) 242 addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException, 243 EnableEmSjLj)); 244 245 TargetPassConfig::addIRPasses(); 246 } 247 248 bool WebAssemblyPassConfig::addInstSelector() { 249 (void)TargetPassConfig::addInstSelector(); 250 addPass( 251 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 252 // Run the argument-move pass immediately after the ScheduleDAG scheduler 253 // so that we can fix up the ARGUMENT instructions before anything else 254 // sees them in the wrong place. 255 addPass(createWebAssemblyArgumentMove()); 256 // Set the p2align operands. This information is present during ISel, however 257 // it's inconvenient to collect. Collect it now, and update the immediate 258 // operands. 259 addPass(createWebAssemblySetP2AlignOperands()); 260 return false; 261 } 262 263 void WebAssemblyPassConfig::addPostRegAlloc() { 264 // TODO: The following CodeGen passes don't currently support code containing 265 // virtual registers. Consider removing their restrictions and re-enabling 266 // them. 267 268 // These functions all require the NoVRegs property. 269 disablePass(&MachineCopyPropagationID); 270 disablePass(&PostRAMachineSinkingID); 271 disablePass(&PostRASchedulerID); 272 disablePass(&FuncletLayoutID); 273 disablePass(&StackMapLivenessID); 274 disablePass(&LiveDebugValuesID); 275 disablePass(&PatchableFunctionID); 276 disablePass(&ShrinkWrapID); 277 278 TargetPassConfig::addPostRegAlloc(); 279 } 280 281 void WebAssemblyPassConfig::addPreEmitPass() { 282 TargetPassConfig::addPreEmitPass(); 283 284 // Now that we have a prologue and epilogue and all frame indices are 285 // rewritten, eliminate SP and FP. This allows them to be stackified, 286 // colored, and numbered with the rest of the registers. 287 addPass(createWebAssemblyReplacePhysRegs()); 288 289 // Rewrite pseudo call_indirect instructions as real instructions. 290 // This needs to run before register stackification, because we change the 291 // order of the arguments. 292 addPass(createWebAssemblyCallIndirectFixup()); 293 294 if (getOptLevel() != CodeGenOpt::None) { 295 // LiveIntervals isn't commonly run this late. Re-establish preconditions. 296 addPass(createWebAssemblyPrepareForLiveIntervals()); 297 298 // Depend on LiveIntervals and perform some optimizations on it. 299 addPass(createWebAssemblyOptimizeLiveIntervals()); 300 301 // Prepare store instructions for register stackifying. 302 addPass(createWebAssemblyStoreResults()); 303 304 // Mark registers as representing wasm's value stack. This is a key 305 // code-compression technique in WebAssembly. We run this pass (and 306 // StoreResults above) very late, so that it sees as much code as possible, 307 // including code emitted by PEI and expanded by late tail duplication. 308 addPass(createWebAssemblyRegStackify()); 309 310 // Run the register coloring pass to reduce the total number of registers. 311 // This runs after stackification so that it doesn't consider registers 312 // that become stackified. 313 addPass(createWebAssemblyRegColoring()); 314 } 315 316 // Eliminate multiple-entry loops. Do this before inserting explicit get_local 317 // and set_local operators because we create a new variable that we want 318 // converted into a local. 319 addPass(createWebAssemblyFixIrreducibleControlFlow()); 320 321 // Insert explicit get_local and set_local operators. 322 addPass(createWebAssemblyExplicitLocals()); 323 324 // Do various transformations for exception handling 325 addPass(createWebAssemblyLateEHPrepare()); 326 327 // Sort the blocks of the CFG into topological order, a prerequisite for 328 // BLOCK and LOOP markers. 329 addPass(createWebAssemblyCFGSort()); 330 331 // Insert BLOCK and LOOP markers. 332 addPass(createWebAssemblyCFGStackify()); 333 334 // Lower br_unless into br_if. 335 addPass(createWebAssemblyLowerBrUnless()); 336 337 // Perform the very last peephole optimizations on the code. 338 if (getOptLevel() != CodeGenOpt::None) 339 addPass(createWebAssemblyPeephole()); 340 341 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 342 addPass(createWebAssemblyRegNumbering()); 343 } 344