1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssemblyTargetMachine.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssembly.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Transforms/Scalar.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm" 31 32 // Emscripten's asm.js-style exception handling 33 static cl::opt<bool> EnableEmException( 34 "enable-emscripten-cxx-exceptions", 35 cl::desc("WebAssembly Emscripten-style exception handling"), 36 cl::init(false)); 37 38 // Emscripten's asm.js-style setjmp/longjmp handling 39 static cl::opt<bool> EnableEmSjLj( 40 "enable-emscripten-sjlj", 41 cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"), 42 cl::init(false)); 43 44 extern "C" void LLVMInitializeWebAssemblyTarget() { 45 // Register the target. 46 RegisterTargetMachine<WebAssemblyTargetMachine> X( 47 getTheWebAssemblyTarget32()); 48 RegisterTargetMachine<WebAssemblyTargetMachine> Y( 49 getTheWebAssemblyTarget64()); 50 51 // Register exception handling pass to opt 52 initializeWebAssemblyLowerEmscriptenEHSjLjPass( 53 *PassRegistry::getPassRegistry()); 54 } 55 56 //===----------------------------------------------------------------------===// 57 // WebAssembly Lowering public interface. 58 //===----------------------------------------------------------------------===// 59 60 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 61 if (!RM.hasValue()) 62 return Reloc::PIC_; 63 return *RM; 64 } 65 66 /// Create an WebAssembly architecture model. 67 /// 68 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 69 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 70 const TargetOptions &Options, Optional<Reloc::Model> RM, 71 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) 72 : LLVMTargetMachine(T, 73 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 74 : "e-m:e-p:32:32-i64:64-n32:64-S128", 75 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 76 CM ? *CM : CodeModel::Large, OL), 77 TLOF(TT.isOSBinFormatELF() ? 78 static_cast<TargetLoweringObjectFile*>( 79 new WebAssemblyTargetObjectFileELF()) : 80 static_cast<TargetLoweringObjectFile*>( 81 new WebAssemblyTargetObjectFile())) { 82 // WebAssembly type-checks instructions, but a noreturn function with a return 83 // type that doesn't match the context will cause a check failure. So we lower 84 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 85 // 'unreachable' instructions which is meant for that case. 86 this->Options.TrapUnreachable = true; 87 88 // WebAssembly treats each function as an independent unit. Force 89 // -ffunction-sections, effectively, so that we can emit them independently. 90 if (!TT.isOSBinFormatELF()) { 91 this->Options.FunctionSections = true; 92 this->Options.DataSections = true; 93 this->Options.UniqueSectionNames = true; 94 } 95 96 initAsmInfo(); 97 98 // Note that we don't use setRequiresStructuredCFG(true). It disables 99 // optimizations than we're ok with, and want, such as critical edge 100 // splitting and tail merging. 101 } 102 103 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 104 105 const WebAssemblySubtarget * 106 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 107 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 108 Attribute FSAttr = F.getFnAttribute("target-features"); 109 110 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 111 ? CPUAttr.getValueAsString().str() 112 : TargetCPU; 113 std::string FS = !FSAttr.hasAttribute(Attribute::None) 114 ? FSAttr.getValueAsString().str() 115 : TargetFS; 116 117 auto &I = SubtargetMap[CPU + FS]; 118 if (!I) { 119 // This needs to be done before we create a new subtarget since any 120 // creation will depend on the TM and the code generation flags on the 121 // function that reside in TargetOptions. 122 resetTargetOptions(F); 123 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 124 } 125 return I.get(); 126 } 127 128 namespace { 129 /// WebAssembly Code Generator Pass Configuration Options. 130 class WebAssemblyPassConfig final : public TargetPassConfig { 131 public: 132 WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM) 133 : TargetPassConfig(TM, PM) {} 134 135 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 136 return getTM<WebAssemblyTargetMachine>(); 137 } 138 139 FunctionPass *createTargetRegisterAllocator(bool) override; 140 141 void addIRPasses() override; 142 bool addInstSelector() override; 143 void addPostRegAlloc() override; 144 bool addGCPasses() override { return false; } 145 void addPreEmitPass() override; 146 }; 147 } // end anonymous namespace 148 149 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 150 return TargetIRAnalysis([this](const Function &F) { 151 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 152 }); 153 } 154 155 TargetPassConfig * 156 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 157 return new WebAssemblyPassConfig(*this, PM); 158 } 159 160 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 161 return nullptr; // No reg alloc 162 } 163 164 //===----------------------------------------------------------------------===// 165 // The following functions are called from lib/CodeGen/Passes.cpp to modify 166 // the CodeGen pass sequence. 167 //===----------------------------------------------------------------------===// 168 169 void WebAssemblyPassConfig::addIRPasses() { 170 if (TM->Options.ThreadModel == ThreadModel::Single) 171 // In "single" mode, atomics get lowered to non-atomics. 172 addPass(createLowerAtomicPass()); 173 else 174 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 175 // control specifically what gets lowered. 176 addPass(createAtomicExpandPass()); 177 178 // Fix function bitcasts, as WebAssembly requires caller and callee signatures 179 // to match. 180 addPass(createWebAssemblyFixFunctionBitcasts()); 181 182 // Optimize "returned" function attributes. 183 if (getOptLevel() != CodeGenOpt::None) 184 addPass(createWebAssemblyOptimizeReturned()); 185 186 // If exception handling is not enabled and setjmp/longjmp handling is 187 // enabled, we lower invokes into calls and delete unreachable landingpad 188 // blocks. Lowering invokes when there is no EH support is done in 189 // TargetPassConfig::addPassesToHandleExceptions, but this runs after this 190 // function and SjLj handling expects all invokes to be lowered before. 191 if (!EnableEmException) { 192 addPass(createLowerInvokePass()); 193 // The lower invoke pass may create unreachable code. Remove it in order not 194 // to process dead blocks in setjmp/longjmp handling. 195 addPass(createUnreachableBlockEliminationPass()); 196 } 197 198 // Handle exceptions and setjmp/longjmp if enabled. 199 if (EnableEmException || EnableEmSjLj) 200 addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException, 201 EnableEmSjLj)); 202 203 TargetPassConfig::addIRPasses(); 204 } 205 206 bool WebAssemblyPassConfig::addInstSelector() { 207 (void)TargetPassConfig::addInstSelector(); 208 addPass( 209 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 210 // Run the argument-move pass immediately after the ScheduleDAG scheduler 211 // so that we can fix up the ARGUMENT instructions before anything else 212 // sees them in the wrong place. 213 addPass(createWebAssemblyArgumentMove()); 214 // Set the p2align operands. This information is present during ISel, however 215 // it's inconvenient to collect. Collect it now, and update the immediate 216 // operands. 217 addPass(createWebAssemblySetP2AlignOperands()); 218 return false; 219 } 220 221 void WebAssemblyPassConfig::addPostRegAlloc() { 222 // TODO: The following CodeGen passes don't currently support code containing 223 // virtual registers. Consider removing their restrictions and re-enabling 224 // them. 225 226 // Has no asserts of its own, but was not written to handle virtual regs. 227 disablePass(&ShrinkWrapID); 228 229 // These functions all require the NoVRegs property. 230 disablePass(&MachineCopyPropagationID); 231 disablePass(&PostRASchedulerID); 232 disablePass(&FuncletLayoutID); 233 disablePass(&StackMapLivenessID); 234 disablePass(&LiveDebugValuesID); 235 disablePass(&PatchableFunctionID); 236 237 TargetPassConfig::addPostRegAlloc(); 238 } 239 240 void WebAssemblyPassConfig::addPreEmitPass() { 241 TargetPassConfig::addPreEmitPass(); 242 243 // Now that we have a prologue and epilogue and all frame indices are 244 // rewritten, eliminate SP and FP. This allows them to be stackified, 245 // colored, and numbered with the rest of the registers. 246 addPass(createWebAssemblyReplacePhysRegs()); 247 248 // Rewrite pseudo call_indirect instructions as real instructions. 249 // This needs to run before register stackification, because we change the 250 // order of the arguments. 251 addPass(createWebAssemblyCallIndirectFixup()); 252 253 if (getOptLevel() != CodeGenOpt::None) { 254 // LiveIntervals isn't commonly run this late. Re-establish preconditions. 255 addPass(createWebAssemblyPrepareForLiveIntervals()); 256 257 // Depend on LiveIntervals and perform some optimizations on it. 258 addPass(createWebAssemblyOptimizeLiveIntervals()); 259 260 // Prepare store instructions for register stackifying. 261 addPass(createWebAssemblyStoreResults()); 262 263 // Mark registers as representing wasm's value stack. This is a key 264 // code-compression technique in WebAssembly. We run this pass (and 265 // StoreResults above) very late, so that it sees as much code as possible, 266 // including code emitted by PEI and expanded by late tail duplication. 267 addPass(createWebAssemblyRegStackify()); 268 269 // Run the register coloring pass to reduce the total number of registers. 270 // This runs after stackification so that it doesn't consider registers 271 // that become stackified. 272 addPass(createWebAssemblyRegColoring()); 273 } 274 275 // Eliminate multiple-entry loops. Do this before inserting explicit get_local 276 // and set_local operators because we create a new variable that we want 277 // converted into a local. 278 addPass(createWebAssemblyFixIrreducibleControlFlow()); 279 280 // Insert explicit get_local and set_local operators. 281 addPass(createWebAssemblyExplicitLocals()); 282 283 // Sort the blocks of the CFG into topological order, a prerequisite for 284 // BLOCK and LOOP markers. 285 addPass(createWebAssemblyCFGSort()); 286 287 // Insert BLOCK and LOOP markers. 288 addPass(createWebAssemblyCFGStackify()); 289 290 // Lower br_unless into br_if. 291 addPass(createWebAssemblyLowerBrUnless()); 292 293 // Perform the very last peephole optimizations on the code. 294 if (getOptLevel() != CodeGenOpt::None) 295 addPass(createWebAssemblyPeephole()); 296 297 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 298 addPass(createWebAssemblyRegNumbering()); 299 } 300