1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssembly.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyTargetMachine.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/CommandLine.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Target/TargetOptions.h" 28 #include "llvm/Transforms/Scalar.h" 29 using namespace llvm; 30 31 #define DEBUG_TYPE "wasm" 32 33 extern "C" void LLVMInitializeWebAssemblyTarget() { 34 // Register the target. 35 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); 36 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); 37 } 38 39 //===----------------------------------------------------------------------===// 40 // WebAssembly Lowering public interface. 41 //===----------------------------------------------------------------------===// 42 43 /// Create an WebAssembly architecture model. 44 /// 45 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 46 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 47 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 48 CodeGenOpt::Level OL) 49 : LLVMTargetMachine(T, TT.isArch64Bit() ? "e-p:64:64-i64:64-n32:64-S128" 50 : "e-p:32:32-i64:64-n32:64-S128", 51 TT, CPU, FS, Options, RM, CM, OL), 52 TLOF(make_unique<WebAssemblyTargetObjectFile>()) { 53 // WebAssembly type-checks expressions, but a noreturn function with a return 54 // type that doesn't match the context will cause a check failure. So we lower 55 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 56 // 'unreachable' expression which is meant for that case. 57 this->Options.TrapUnreachable = true; 58 59 initAsmInfo(); 60 61 // We need a reducible CFG, so disable some optimizations which tend to 62 // introduce irreducibility. 63 setRequiresStructuredCFG(true); 64 } 65 66 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 67 68 const WebAssemblySubtarget * 69 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 70 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 71 Attribute FSAttr = F.getFnAttribute("target-features"); 72 73 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 74 ? CPUAttr.getValueAsString().str() 75 : TargetCPU; 76 std::string FS = !FSAttr.hasAttribute(Attribute::None) 77 ? FSAttr.getValueAsString().str() 78 : TargetFS; 79 80 auto &I = SubtargetMap[CPU + FS]; 81 if (!I) { 82 // This needs to be done before we create a new subtarget since any 83 // creation will depend on the TM and the code generation flags on the 84 // function that reside in TargetOptions. 85 resetTargetOptions(F); 86 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 87 } 88 return I.get(); 89 } 90 91 namespace { 92 /// WebAssembly Code Generator Pass Configuration Options. 93 class WebAssemblyPassConfig final : public TargetPassConfig { 94 public: 95 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM) 96 : TargetPassConfig(TM, PM) {} 97 98 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 99 return getTM<WebAssemblyTargetMachine>(); 100 } 101 102 FunctionPass *createTargetRegisterAllocator(bool) override; 103 104 void addIRPasses() override; 105 bool addInstSelector() override; 106 bool addILPOpts() override; 107 void addPreRegAlloc() override; 108 void addPostRegAlloc() override; 109 void addPreEmitPass() override; 110 }; 111 } // end anonymous namespace 112 113 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 114 return TargetIRAnalysis([this](const Function &F) { 115 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 116 }); 117 } 118 119 TargetPassConfig * 120 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 121 return new WebAssemblyPassConfig(this, PM); 122 } 123 124 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 125 return nullptr; // No reg alloc 126 } 127 128 //===----------------------------------------------------------------------===// 129 // The following functions are called from lib/CodeGen/Passes.cpp to modify 130 // the CodeGen pass sequence. 131 //===----------------------------------------------------------------------===// 132 133 void WebAssemblyPassConfig::addIRPasses() { 134 if (TM->Options.ThreadModel == ThreadModel::Single) 135 // In "single" mode, atomics get lowered to non-atomics. 136 addPass(createLowerAtomicPass()); 137 else 138 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 139 // control specifically what gets lowered. 140 addPass(createAtomicExpandPass(TM)); 141 142 // Optimize "returned" function attributes. 143 addPass(createWebAssemblyOptimizeReturned()); 144 145 TargetPassConfig::addIRPasses(); 146 } 147 148 bool WebAssemblyPassConfig::addInstSelector() { 149 (void)TargetPassConfig::addInstSelector(); 150 addPass( 151 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 152 // Run the argument-move pass immediately after the ScheduleDAG scheduler 153 // so that we can fix up the ARGUMENT instructions before anything else 154 // sees them in the wrong place. 155 addPass(createWebAssemblyArgumentMove()); 156 return false; 157 } 158 159 bool WebAssemblyPassConfig::addILPOpts() { 160 (void)TargetPassConfig::addILPOpts(); 161 return true; 162 } 163 164 void WebAssemblyPassConfig::addPreRegAlloc() { 165 TargetPassConfig::addPreRegAlloc(); 166 167 // Prepare store instructions for register stackifying. 168 addPass(createWebAssemblyStoreResults()); 169 170 // Mark registers as representing wasm's expression stack. 171 addPass(createWebAssemblyRegStackify()); 172 } 173 174 void WebAssemblyPassConfig::addPostRegAlloc() { 175 // TODO: The following CodeGen passes don't currently support code containing 176 // virtual registers. Consider removing their restrictions and re-enabling 177 // them. 178 // 179 // Fails with: Regalloc must assign all vregs. 180 disablePass(&PrologEpilogCodeInserterID); 181 // Fails with: should be run after register allocation. 182 disablePass(&MachineCopyPropagationID); 183 184 // Run the register coloring pass to reduce the total number of registers. 185 addPass(createWebAssemblyRegColoring()); 186 187 TargetPassConfig::addPostRegAlloc(); 188 } 189 190 void WebAssemblyPassConfig::addPreEmitPass() { 191 TargetPassConfig::addPreEmitPass(); 192 193 // Put the CFG in structured form; insert BLOCK and LOOP markers. 194 addPass(createWebAssemblyCFGStackify()); 195 196 // Lower br_unless into br_if. 197 addPass(createWebAssemblyLowerBrUnless()); 198 199 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 200 addPass(createWebAssemblyRegNumbering()); 201 202 // Perform the very last peephole optimizations on the code. 203 addPass(createWebAssemblyPeephole()); 204 } 205