1009cd4e4SKit Barton //===-- PPCRegisterBankInfo.h -----------------------------------*- C++ -*-===// 2009cd4e4SKit Barton // 3009cd4e4SKit Barton // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4009cd4e4SKit Barton // See https://llvm.org/LICENSE.txt for license information. 5009cd4e4SKit Barton // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6009cd4e4SKit Barton // 7009cd4e4SKit Barton //===----------------------------------------------------------------------===// 8009cd4e4SKit Barton /// 9009cd4e4SKit Barton /// \file 10009cd4e4SKit Barton /// This file declares the targeting of the RegisterBankInfo class for PowerPC. 11009cd4e4SKit Barton /// 12009cd4e4SKit Barton //===----------------------------------------------------------------------===// 13009cd4e4SKit Barton 14009cd4e4SKit Barton #ifndef LLVM_LIB_TARGET_PPC_GISEL_PPCREGISTERBANKINFO_H 15009cd4e4SKit Barton #define LLVM_LIB_TARGET_PPC_GISEL_PPCREGISTERBANKINFO_H 16009cd4e4SKit Barton 17cb216076SMircea Trofin #include "llvm/CodeGen/RegisterBank.h" 18cb216076SMircea Trofin #include "llvm/CodeGen/RegisterBankInfo.h" 19009cd4e4SKit Barton #include "llvm/CodeGen/TargetRegisterInfo.h" 20009cd4e4SKit Barton 21009cd4e4SKit Barton #define GET_REGBANK_DECLARATIONS 22009cd4e4SKit Barton #include "PPCGenRegisterBank.inc" 23009cd4e4SKit Barton 24009cd4e4SKit Barton namespace llvm { 25009cd4e4SKit Barton class TargetRegisterInfo; 26009cd4e4SKit Barton 27009cd4e4SKit Barton class PPCGenRegisterBankInfo : public RegisterBankInfo { 28009cd4e4SKit Barton protected: 29be4a1dfbSKai Nacke enum PartialMappingIdx { 30be4a1dfbSKai Nacke PMI_None = -1, 31b41d22dbSChen Zheng PMI_GPR32 = 1, 32b41d22dbSChen Zheng PMI_GPR64 = 2, 33b41d22dbSChen Zheng PMI_FPR32 = 3, 34b41d22dbSChen Zheng PMI_FPR64 = 4, 353508f123SAmy Kwan PMI_VEC128 = 5, 363508f123SAmy Kwan PMI_CR = 6, 37b41d22dbSChen Zheng PMI_Min = PMI_GPR32, 38be4a1dfbSKai Nacke }; 39be4a1dfbSKai Nacke 40c4821073SCraig Topper static const RegisterBankInfo::PartialMapping PartMappings[]; 41c4821073SCraig Topper static const RegisterBankInfo::ValueMapping ValMappings[]; 42c4821073SCraig Topper static const PartialMappingIdx BankIDToCopyMapIdx[]; 43be4a1dfbSKai Nacke 44be4a1dfbSKai Nacke /// Get the pointer to the ValueMapping representing the RegisterBank 45be4a1dfbSKai Nacke /// at \p RBIdx. 46be4a1dfbSKai Nacke /// 47be4a1dfbSKai Nacke /// The returned mapping works for instructions with the same kind of 48be4a1dfbSKai Nacke /// operands for up to 3 operands. 49be4a1dfbSKai Nacke /// 50be4a1dfbSKai Nacke /// \pre \p RBIdx != PartialMappingIdx::None 51be4a1dfbSKai Nacke static const RegisterBankInfo::ValueMapping * 52be4a1dfbSKai Nacke getValueMapping(PartialMappingIdx RBIdx); 53be4a1dfbSKai Nacke 54be4a1dfbSKai Nacke /// Get the pointer to the ValueMapping of the operands of a copy 55be4a1dfbSKai Nacke /// instruction from the \p SrcBankID register bank to the \p DstBankID 56be4a1dfbSKai Nacke /// register bank with a size of \p Size. 57be4a1dfbSKai Nacke static const RegisterBankInfo::ValueMapping * 58be4a1dfbSKai Nacke getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size); 59be4a1dfbSKai Nacke 60009cd4e4SKit Barton #define GET_TARGET_REGBANK_CLASS 61009cd4e4SKit Barton #include "PPCGenRegisterBank.inc" 62009cd4e4SKit Barton }; 63009cd4e4SKit Barton 64009cd4e4SKit Barton class PPCRegisterBankInfo final : public PPCGenRegisterBankInfo { 65009cd4e4SKit Barton public: 66009cd4e4SKit Barton PPCRegisterBankInfo(const TargetRegisterInfo &TRI); 67be4a1dfbSKai Nacke 68be4a1dfbSKai Nacke const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 69be4a1dfbSKai Nacke LLT Ty) const override; 70*a79db96eSKai Nacke 71be4a1dfbSKai Nacke const InstructionMapping & 72be4a1dfbSKai Nacke getInstrMapping(const MachineInstr &MI) const override; 73be4a1dfbSKai Nacke 74be4a1dfbSKai Nacke InstructionMappings 75be4a1dfbSKai Nacke getInstrAlternativeMappings(const MachineInstr &MI) const override; 76503a935dSChen Zheng 77503a935dSChen Zheng private: 78503a935dSChen Zheng /// Maximum recursion depth for hasFPConstraints. 79503a935dSChen Zheng const unsigned MaxFPRSearchDepth = 2; 80503a935dSChen Zheng 81503a935dSChen Zheng /// \returns true if \p MI only uses and defines FPRs. 82503a935dSChen Zheng bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI, 83503a935dSChen Zheng const TargetRegisterInfo &TRI, 84503a935dSChen Zheng unsigned Depth = 0) const; 85503a935dSChen Zheng 86503a935dSChen Zheng /// \returns true if \p MI only uses FPRs. 87503a935dSChen Zheng bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 88503a935dSChen Zheng const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 89503a935dSChen Zheng 90503a935dSChen Zheng /// \returns true if \p MI only defines FPRs. 91503a935dSChen Zheng bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 92503a935dSChen Zheng const TargetRegisterInfo &TRI, unsigned Depth = 0) const; 93009cd4e4SKit Barton }; 94009cd4e4SKit Barton } // namespace llvm 95009cd4e4SKit Barton 96009cd4e4SKit Barton #endif 97