1 //===-- NVPTXReplaceImageHandles.cpp - Replace image handles for Fermi ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // On Fermi, image handles are not supported. To work around this, we traverse 10 // the machine code and replace image handles with concrete symbols. For this 11 // to work reliably, inlining of all function call must be performed. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MCTargetDesc/NVPTXBaseInfo.h" 15 #include "NVPTX.h" 16 #include "NVPTXMachineFunctionInfo.h" 17 #include "NVPTXSubtarget.h" 18 #include "NVPTXTargetMachine.h" 19 #include "llvm/ADT/DenseSet.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/Support/raw_ostream.h" 24 25 using namespace llvm; 26 27 namespace { 28 class NVPTXReplaceImageHandles : public MachineFunctionPass { 29 private: 30 static char ID; 31 DenseSet<MachineInstr *> InstrsToRemove; 32 33 public: 34 NVPTXReplaceImageHandles(); 35 36 bool runOnMachineFunction(MachineFunction &MF) override; 37 38 StringRef getPassName() const override { 39 return "NVPTX Replace Image Handles"; 40 } 41 private: 42 bool processInstr(MachineInstr &MI); 43 bool replaceImageHandle(MachineOperand &Op, MachineFunction &MF); 44 bool findIndexForHandle(MachineOperand &Op, MachineFunction &MF, 45 unsigned &Idx); 46 }; 47 } 48 49 char NVPTXReplaceImageHandles::ID = 0; 50 51 NVPTXReplaceImageHandles::NVPTXReplaceImageHandles() 52 : MachineFunctionPass(ID) {} 53 54 bool NVPTXReplaceImageHandles::runOnMachineFunction(MachineFunction &MF) { 55 bool Changed = false; 56 InstrsToRemove.clear(); 57 58 for (MachineBasicBlock &MBB : MF) 59 for (MachineInstr &MI : MBB) 60 Changed |= processInstr(MI); 61 62 // Now clean up any handle-access instructions 63 // This is needed in debug mode when code cleanup passes are not executed, 64 // but we need the handle access to be eliminated because they are not 65 // valid instructions when image handles are disabled. 66 for (MachineInstr *MI : InstrsToRemove) { 67 unsigned DefReg = MI->getOperand(0).getReg(); 68 // Only these that are not used can be removed. 69 if (MF.getRegInfo().use_nodbg_empty(DefReg)) 70 MI->eraseFromParent(); 71 } 72 return Changed; 73 } 74 75 static unsigned suldRegisterToIndexOpcode(unsigned RegOC) { 76 switch (RegOC) { 77 case NVPTX::SULD_1D_I8_CLAMP_R: 78 return NVPTX::SULD_1D_I8_CLAMP_I; 79 case NVPTX::SULD_1D_I16_CLAMP_R: 80 return NVPTX::SULD_1D_I16_CLAMP_I; 81 case NVPTX::SULD_1D_I32_CLAMP_R: 82 return NVPTX::SULD_1D_I32_CLAMP_I; 83 case NVPTX::SULD_1D_I64_CLAMP_R: 84 return NVPTX::SULD_1D_I64_CLAMP_I; 85 case NVPTX::SULD_1D_ARRAY_I8_CLAMP_R: 86 return NVPTX::SULD_1D_ARRAY_I8_CLAMP_I; 87 case NVPTX::SULD_1D_ARRAY_I16_CLAMP_R: 88 return NVPTX::SULD_1D_ARRAY_I16_CLAMP_I; 89 case NVPTX::SULD_1D_ARRAY_I32_CLAMP_R: 90 return NVPTX::SULD_1D_ARRAY_I32_CLAMP_I; 91 case NVPTX::SULD_1D_ARRAY_I64_CLAMP_R: 92 return NVPTX::SULD_1D_ARRAY_I64_CLAMP_I; 93 case NVPTX::SULD_2D_I8_CLAMP_R: 94 return NVPTX::SULD_2D_I8_CLAMP_I; 95 case NVPTX::SULD_2D_I16_CLAMP_R: 96 return NVPTX::SULD_2D_I16_CLAMP_I; 97 case NVPTX::SULD_2D_I32_CLAMP_R: 98 return NVPTX::SULD_2D_I32_CLAMP_I; 99 case NVPTX::SULD_2D_I64_CLAMP_R: 100 return NVPTX::SULD_2D_I64_CLAMP_I; 101 case NVPTX::SULD_2D_ARRAY_I8_CLAMP_R: 102 return NVPTX::SULD_2D_ARRAY_I8_CLAMP_I; 103 case NVPTX::SULD_2D_ARRAY_I16_CLAMP_R: 104 return NVPTX::SULD_2D_ARRAY_I16_CLAMP_I; 105 case NVPTX::SULD_2D_ARRAY_I32_CLAMP_R: 106 return NVPTX::SULD_2D_ARRAY_I32_CLAMP_I; 107 case NVPTX::SULD_2D_ARRAY_I64_CLAMP_R: 108 return NVPTX::SULD_2D_ARRAY_I64_CLAMP_I; 109 case NVPTX::SULD_3D_I8_CLAMP_R: 110 return NVPTX::SULD_3D_I8_CLAMP_I; 111 case NVPTX::SULD_3D_I16_CLAMP_R: 112 return NVPTX::SULD_3D_I16_CLAMP_I; 113 case NVPTX::SULD_3D_I32_CLAMP_R: 114 return NVPTX::SULD_3D_I32_CLAMP_I; 115 case NVPTX::SULD_3D_I64_CLAMP_R: 116 return NVPTX::SULD_3D_I64_CLAMP_I; 117 case NVPTX::SULD_1D_V2I8_CLAMP_R: 118 return NVPTX::SULD_1D_V2I8_CLAMP_I; 119 case NVPTX::SULD_1D_V2I16_CLAMP_R: 120 return NVPTX::SULD_1D_V2I16_CLAMP_I; 121 case NVPTX::SULD_1D_V2I32_CLAMP_R: 122 return NVPTX::SULD_1D_V2I32_CLAMP_I; 123 case NVPTX::SULD_1D_V2I64_CLAMP_R: 124 return NVPTX::SULD_1D_V2I64_CLAMP_I; 125 case NVPTX::SULD_1D_ARRAY_V2I8_CLAMP_R: 126 return NVPTX::SULD_1D_ARRAY_V2I8_CLAMP_I; 127 case NVPTX::SULD_1D_ARRAY_V2I16_CLAMP_R: 128 return NVPTX::SULD_1D_ARRAY_V2I16_CLAMP_I; 129 case NVPTX::SULD_1D_ARRAY_V2I32_CLAMP_R: 130 return NVPTX::SULD_1D_ARRAY_V2I32_CLAMP_I; 131 case NVPTX::SULD_1D_ARRAY_V2I64_CLAMP_R: 132 return NVPTX::SULD_1D_ARRAY_V2I64_CLAMP_I; 133 case NVPTX::SULD_2D_V2I8_CLAMP_R: 134 return NVPTX::SULD_2D_V2I8_CLAMP_I; 135 case NVPTX::SULD_2D_V2I16_CLAMP_R: 136 return NVPTX::SULD_2D_V2I16_CLAMP_I; 137 case NVPTX::SULD_2D_V2I32_CLAMP_R: 138 return NVPTX::SULD_2D_V2I32_CLAMP_I; 139 case NVPTX::SULD_2D_V2I64_CLAMP_R: 140 return NVPTX::SULD_2D_V2I64_CLAMP_I; 141 case NVPTX::SULD_2D_ARRAY_V2I8_CLAMP_R: 142 return NVPTX::SULD_2D_ARRAY_V2I8_CLAMP_I; 143 case NVPTX::SULD_2D_ARRAY_V2I16_CLAMP_R: 144 return NVPTX::SULD_2D_ARRAY_V2I16_CLAMP_I; 145 case NVPTX::SULD_2D_ARRAY_V2I32_CLAMP_R: 146 return NVPTX::SULD_2D_ARRAY_V2I32_CLAMP_I; 147 case NVPTX::SULD_2D_ARRAY_V2I64_CLAMP_R: 148 return NVPTX::SULD_2D_ARRAY_V2I64_CLAMP_I; 149 case NVPTX::SULD_3D_V2I8_CLAMP_R: 150 return NVPTX::SULD_3D_V2I8_CLAMP_I; 151 case NVPTX::SULD_3D_V2I16_CLAMP_R: 152 return NVPTX::SULD_3D_V2I16_CLAMP_I; 153 case NVPTX::SULD_3D_V2I32_CLAMP_R: 154 return NVPTX::SULD_3D_V2I32_CLAMP_I; 155 case NVPTX::SULD_3D_V2I64_CLAMP_R: 156 return NVPTX::SULD_3D_V2I64_CLAMP_I; 157 case NVPTX::SULD_1D_V4I8_CLAMP_R: 158 return NVPTX::SULD_1D_V4I8_CLAMP_I; 159 case NVPTX::SULD_1D_V4I16_CLAMP_R: 160 return NVPTX::SULD_1D_V4I16_CLAMP_I; 161 case NVPTX::SULD_1D_V4I32_CLAMP_R: 162 return NVPTX::SULD_1D_V4I32_CLAMP_I; 163 case NVPTX::SULD_1D_ARRAY_V4I8_CLAMP_R: 164 return NVPTX::SULD_1D_ARRAY_V4I8_CLAMP_I; 165 case NVPTX::SULD_1D_ARRAY_V4I16_CLAMP_R: 166 return NVPTX::SULD_1D_ARRAY_V4I16_CLAMP_I; 167 case NVPTX::SULD_1D_ARRAY_V4I32_CLAMP_R: 168 return NVPTX::SULD_1D_ARRAY_V4I32_CLAMP_I; 169 case NVPTX::SULD_2D_V4I8_CLAMP_R: 170 return NVPTX::SULD_2D_V4I8_CLAMP_I; 171 case NVPTX::SULD_2D_V4I16_CLAMP_R: 172 return NVPTX::SULD_2D_V4I16_CLAMP_I; 173 case NVPTX::SULD_2D_V4I32_CLAMP_R: 174 return NVPTX::SULD_2D_V4I32_CLAMP_I; 175 case NVPTX::SULD_2D_ARRAY_V4I8_CLAMP_R: 176 return NVPTX::SULD_2D_ARRAY_V4I8_CLAMP_I; 177 case NVPTX::SULD_2D_ARRAY_V4I16_CLAMP_R: 178 return NVPTX::SULD_2D_ARRAY_V4I16_CLAMP_I; 179 case NVPTX::SULD_2D_ARRAY_V4I32_CLAMP_R: 180 return NVPTX::SULD_2D_ARRAY_V4I32_CLAMP_I; 181 case NVPTX::SULD_3D_V4I8_CLAMP_R: 182 return NVPTX::SULD_3D_V4I8_CLAMP_I; 183 case NVPTX::SULD_3D_V4I16_CLAMP_R: 184 return NVPTX::SULD_3D_V4I16_CLAMP_I; 185 case NVPTX::SULD_3D_V4I32_CLAMP_R: 186 return NVPTX::SULD_3D_V4I32_CLAMP_I; 187 case NVPTX::SULD_1D_I8_TRAP_R: 188 return NVPTX::SULD_1D_I8_TRAP_I; 189 case NVPTX::SULD_1D_I16_TRAP_R: 190 return NVPTX::SULD_1D_I16_TRAP_I; 191 case NVPTX::SULD_1D_I32_TRAP_R: 192 return NVPTX::SULD_1D_I32_TRAP_I; 193 case NVPTX::SULD_1D_I64_TRAP_R: 194 return NVPTX::SULD_1D_I64_TRAP_I; 195 case NVPTX::SULD_1D_ARRAY_I8_TRAP_R: 196 return NVPTX::SULD_1D_ARRAY_I8_TRAP_I; 197 case NVPTX::SULD_1D_ARRAY_I16_TRAP_R: 198 return NVPTX::SULD_1D_ARRAY_I16_TRAP_I; 199 case NVPTX::SULD_1D_ARRAY_I32_TRAP_R: 200 return NVPTX::SULD_1D_ARRAY_I32_TRAP_I; 201 case NVPTX::SULD_1D_ARRAY_I64_TRAP_R: 202 return NVPTX::SULD_1D_ARRAY_I64_TRAP_I; 203 case NVPTX::SULD_2D_I8_TRAP_R: 204 return NVPTX::SULD_2D_I8_TRAP_I; 205 case NVPTX::SULD_2D_I16_TRAP_R: 206 return NVPTX::SULD_2D_I16_TRAP_I; 207 case NVPTX::SULD_2D_I32_TRAP_R: 208 return NVPTX::SULD_2D_I32_TRAP_I; 209 case NVPTX::SULD_2D_I64_TRAP_R: 210 return NVPTX::SULD_2D_I64_TRAP_I; 211 case NVPTX::SULD_2D_ARRAY_I8_TRAP_R: 212 return NVPTX::SULD_2D_ARRAY_I8_TRAP_I; 213 case NVPTX::SULD_2D_ARRAY_I16_TRAP_R: 214 return NVPTX::SULD_2D_ARRAY_I16_TRAP_I; 215 case NVPTX::SULD_2D_ARRAY_I32_TRAP_R: 216 return NVPTX::SULD_2D_ARRAY_I32_TRAP_I; 217 case NVPTX::SULD_2D_ARRAY_I64_TRAP_R: 218 return NVPTX::SULD_2D_ARRAY_I64_TRAP_I; 219 case NVPTX::SULD_3D_I8_TRAP_R: 220 return NVPTX::SULD_3D_I8_TRAP_I; 221 case NVPTX::SULD_3D_I16_TRAP_R: 222 return NVPTX::SULD_3D_I16_TRAP_I; 223 case NVPTX::SULD_3D_I32_TRAP_R: 224 return NVPTX::SULD_3D_I32_TRAP_I; 225 case NVPTX::SULD_3D_I64_TRAP_R: 226 return NVPTX::SULD_3D_I64_TRAP_I; 227 case NVPTX::SULD_1D_V2I8_TRAP_R: 228 return NVPTX::SULD_1D_V2I8_TRAP_I; 229 case NVPTX::SULD_1D_V2I16_TRAP_R: 230 return NVPTX::SULD_1D_V2I16_TRAP_I; 231 case NVPTX::SULD_1D_V2I32_TRAP_R: 232 return NVPTX::SULD_1D_V2I32_TRAP_I; 233 case NVPTX::SULD_1D_V2I64_TRAP_R: 234 return NVPTX::SULD_1D_V2I64_TRAP_I; 235 case NVPTX::SULD_1D_ARRAY_V2I8_TRAP_R: 236 return NVPTX::SULD_1D_ARRAY_V2I8_TRAP_I; 237 case NVPTX::SULD_1D_ARRAY_V2I16_TRAP_R: 238 return NVPTX::SULD_1D_ARRAY_V2I16_TRAP_I; 239 case NVPTX::SULD_1D_ARRAY_V2I32_TRAP_R: 240 return NVPTX::SULD_1D_ARRAY_V2I32_TRAP_I; 241 case NVPTX::SULD_1D_ARRAY_V2I64_TRAP_R: 242 return NVPTX::SULD_1D_ARRAY_V2I64_TRAP_I; 243 case NVPTX::SULD_2D_V2I8_TRAP_R: 244 return NVPTX::SULD_2D_V2I8_TRAP_I; 245 case NVPTX::SULD_2D_V2I16_TRAP_R: 246 return NVPTX::SULD_2D_V2I16_TRAP_I; 247 case NVPTX::SULD_2D_V2I32_TRAP_R: 248 return NVPTX::SULD_2D_V2I32_TRAP_I; 249 case NVPTX::SULD_2D_V2I64_TRAP_R: 250 return NVPTX::SULD_2D_V2I64_TRAP_I; 251 case NVPTX::SULD_2D_ARRAY_V2I8_TRAP_R: 252 return NVPTX::SULD_2D_ARRAY_V2I8_TRAP_I; 253 case NVPTX::SULD_2D_ARRAY_V2I16_TRAP_R: 254 return NVPTX::SULD_2D_ARRAY_V2I16_TRAP_I; 255 case NVPTX::SULD_2D_ARRAY_V2I32_TRAP_R: 256 return NVPTX::SULD_2D_ARRAY_V2I32_TRAP_I; 257 case NVPTX::SULD_2D_ARRAY_V2I64_TRAP_R: 258 return NVPTX::SULD_2D_ARRAY_V2I64_TRAP_I; 259 case NVPTX::SULD_3D_V2I8_TRAP_R: 260 return NVPTX::SULD_3D_V2I8_TRAP_I; 261 case NVPTX::SULD_3D_V2I16_TRAP_R: 262 return NVPTX::SULD_3D_V2I16_TRAP_I; 263 case NVPTX::SULD_3D_V2I32_TRAP_R: 264 return NVPTX::SULD_3D_V2I32_TRAP_I; 265 case NVPTX::SULD_3D_V2I64_TRAP_R: 266 return NVPTX::SULD_3D_V2I64_TRAP_I; 267 case NVPTX::SULD_1D_V4I8_TRAP_R: 268 return NVPTX::SULD_1D_V4I8_TRAP_I; 269 case NVPTX::SULD_1D_V4I16_TRAP_R: 270 return NVPTX::SULD_1D_V4I16_TRAP_I; 271 case NVPTX::SULD_1D_V4I32_TRAP_R: 272 return NVPTX::SULD_1D_V4I32_TRAP_I; 273 case NVPTX::SULD_1D_ARRAY_V4I8_TRAP_R: 274 return NVPTX::SULD_1D_ARRAY_V4I8_TRAP_I; 275 case NVPTX::SULD_1D_ARRAY_V4I16_TRAP_R: 276 return NVPTX::SULD_1D_ARRAY_V4I16_TRAP_I; 277 case NVPTX::SULD_1D_ARRAY_V4I32_TRAP_R: 278 return NVPTX::SULD_1D_ARRAY_V4I32_TRAP_I; 279 case NVPTX::SULD_2D_V4I8_TRAP_R: 280 return NVPTX::SULD_2D_V4I8_TRAP_I; 281 case NVPTX::SULD_2D_V4I16_TRAP_R: 282 return NVPTX::SULD_2D_V4I16_TRAP_I; 283 case NVPTX::SULD_2D_V4I32_TRAP_R: 284 return NVPTX::SULD_2D_V4I32_TRAP_I; 285 case NVPTX::SULD_2D_ARRAY_V4I8_TRAP_R: 286 return NVPTX::SULD_2D_ARRAY_V4I8_TRAP_I; 287 case NVPTX::SULD_2D_ARRAY_V4I16_TRAP_R: 288 return NVPTX::SULD_2D_ARRAY_V4I16_TRAP_I; 289 case NVPTX::SULD_2D_ARRAY_V4I32_TRAP_R: 290 return NVPTX::SULD_2D_ARRAY_V4I32_TRAP_I; 291 case NVPTX::SULD_3D_V4I8_TRAP_R: 292 return NVPTX::SULD_3D_V4I8_TRAP_I; 293 case NVPTX::SULD_3D_V4I16_TRAP_R: 294 return NVPTX::SULD_3D_V4I16_TRAP_I; 295 case NVPTX::SULD_3D_V4I32_TRAP_R: 296 return NVPTX::SULD_3D_V4I32_TRAP_I; 297 case NVPTX::SULD_1D_I8_ZERO_R: 298 return NVPTX::SULD_1D_I8_ZERO_I; 299 case NVPTX::SULD_1D_I16_ZERO_R: 300 return NVPTX::SULD_1D_I16_ZERO_I; 301 case NVPTX::SULD_1D_I32_ZERO_R: 302 return NVPTX::SULD_1D_I32_ZERO_I; 303 case NVPTX::SULD_1D_I64_ZERO_R: 304 return NVPTX::SULD_1D_I64_ZERO_I; 305 case NVPTX::SULD_1D_ARRAY_I8_ZERO_R: 306 return NVPTX::SULD_1D_ARRAY_I8_ZERO_I; 307 case NVPTX::SULD_1D_ARRAY_I16_ZERO_R: 308 return NVPTX::SULD_1D_ARRAY_I16_ZERO_I; 309 case NVPTX::SULD_1D_ARRAY_I32_ZERO_R: 310 return NVPTX::SULD_1D_ARRAY_I32_ZERO_I; 311 case NVPTX::SULD_1D_ARRAY_I64_ZERO_R: 312 return NVPTX::SULD_1D_ARRAY_I64_ZERO_I; 313 case NVPTX::SULD_2D_I8_ZERO_R: 314 return NVPTX::SULD_2D_I8_ZERO_I; 315 case NVPTX::SULD_2D_I16_ZERO_R: 316 return NVPTX::SULD_2D_I16_ZERO_I; 317 case NVPTX::SULD_2D_I32_ZERO_R: 318 return NVPTX::SULD_2D_I32_ZERO_I; 319 case NVPTX::SULD_2D_I64_ZERO_R: 320 return NVPTX::SULD_2D_I64_ZERO_I; 321 case NVPTX::SULD_2D_ARRAY_I8_ZERO_R: 322 return NVPTX::SULD_2D_ARRAY_I8_ZERO_I; 323 case NVPTX::SULD_2D_ARRAY_I16_ZERO_R: 324 return NVPTX::SULD_2D_ARRAY_I16_ZERO_I; 325 case NVPTX::SULD_2D_ARRAY_I32_ZERO_R: 326 return NVPTX::SULD_2D_ARRAY_I32_ZERO_I; 327 case NVPTX::SULD_2D_ARRAY_I64_ZERO_R: 328 return NVPTX::SULD_2D_ARRAY_I64_ZERO_I; 329 case NVPTX::SULD_3D_I8_ZERO_R: 330 return NVPTX::SULD_3D_I8_ZERO_I; 331 case NVPTX::SULD_3D_I16_ZERO_R: 332 return NVPTX::SULD_3D_I16_ZERO_I; 333 case NVPTX::SULD_3D_I32_ZERO_R: 334 return NVPTX::SULD_3D_I32_ZERO_I; 335 case NVPTX::SULD_3D_I64_ZERO_R: 336 return NVPTX::SULD_3D_I64_ZERO_I; 337 case NVPTX::SULD_1D_V2I8_ZERO_R: 338 return NVPTX::SULD_1D_V2I8_ZERO_I; 339 case NVPTX::SULD_1D_V2I16_ZERO_R: 340 return NVPTX::SULD_1D_V2I16_ZERO_I; 341 case NVPTX::SULD_1D_V2I32_ZERO_R: 342 return NVPTX::SULD_1D_V2I32_ZERO_I; 343 case NVPTX::SULD_1D_V2I64_ZERO_R: 344 return NVPTX::SULD_1D_V2I64_ZERO_I; 345 case NVPTX::SULD_1D_ARRAY_V2I8_ZERO_R: 346 return NVPTX::SULD_1D_ARRAY_V2I8_ZERO_I; 347 case NVPTX::SULD_1D_ARRAY_V2I16_ZERO_R: 348 return NVPTX::SULD_1D_ARRAY_V2I16_ZERO_I; 349 case NVPTX::SULD_1D_ARRAY_V2I32_ZERO_R: 350 return NVPTX::SULD_1D_ARRAY_V2I32_ZERO_I; 351 case NVPTX::SULD_1D_ARRAY_V2I64_ZERO_R: 352 return NVPTX::SULD_1D_ARRAY_V2I64_ZERO_I; 353 case NVPTX::SULD_2D_V2I8_ZERO_R: 354 return NVPTX::SULD_2D_V2I8_ZERO_I; 355 case NVPTX::SULD_2D_V2I16_ZERO_R: 356 return NVPTX::SULD_2D_V2I16_ZERO_I; 357 case NVPTX::SULD_2D_V2I32_ZERO_R: 358 return NVPTX::SULD_2D_V2I32_ZERO_I; 359 case NVPTX::SULD_2D_V2I64_ZERO_R: 360 return NVPTX::SULD_2D_V2I64_ZERO_I; 361 case NVPTX::SULD_2D_ARRAY_V2I8_ZERO_R: 362 return NVPTX::SULD_2D_ARRAY_V2I8_ZERO_I; 363 case NVPTX::SULD_2D_ARRAY_V2I16_ZERO_R: 364 return NVPTX::SULD_2D_ARRAY_V2I16_ZERO_I; 365 case NVPTX::SULD_2D_ARRAY_V2I32_ZERO_R: 366 return NVPTX::SULD_2D_ARRAY_V2I32_ZERO_I; 367 case NVPTX::SULD_2D_ARRAY_V2I64_ZERO_R: 368 return NVPTX::SULD_2D_ARRAY_V2I64_ZERO_I; 369 case NVPTX::SULD_3D_V2I8_ZERO_R: 370 return NVPTX::SULD_3D_V2I8_ZERO_I; 371 case NVPTX::SULD_3D_V2I16_ZERO_R: 372 return NVPTX::SULD_3D_V2I16_ZERO_I; 373 case NVPTX::SULD_3D_V2I32_ZERO_R: 374 return NVPTX::SULD_3D_V2I32_ZERO_I; 375 case NVPTX::SULD_3D_V2I64_ZERO_R: 376 return NVPTX::SULD_3D_V2I64_ZERO_I; 377 case NVPTX::SULD_1D_V4I8_ZERO_R: 378 return NVPTX::SULD_1D_V4I8_ZERO_I; 379 case NVPTX::SULD_1D_V4I16_ZERO_R: 380 return NVPTX::SULD_1D_V4I16_ZERO_I; 381 case NVPTX::SULD_1D_V4I32_ZERO_R: 382 return NVPTX::SULD_1D_V4I32_ZERO_I; 383 case NVPTX::SULD_1D_ARRAY_V4I8_ZERO_R: 384 return NVPTX::SULD_1D_ARRAY_V4I8_ZERO_I; 385 case NVPTX::SULD_1D_ARRAY_V4I16_ZERO_R: 386 return NVPTX::SULD_1D_ARRAY_V4I16_ZERO_I; 387 case NVPTX::SULD_1D_ARRAY_V4I32_ZERO_R: 388 return NVPTX::SULD_1D_ARRAY_V4I32_ZERO_I; 389 case NVPTX::SULD_2D_V4I8_ZERO_R: 390 return NVPTX::SULD_2D_V4I8_ZERO_I; 391 case NVPTX::SULD_2D_V4I16_ZERO_R: 392 return NVPTX::SULD_2D_V4I16_ZERO_I; 393 case NVPTX::SULD_2D_V4I32_ZERO_R: 394 return NVPTX::SULD_2D_V4I32_ZERO_I; 395 case NVPTX::SULD_2D_ARRAY_V4I8_ZERO_R: 396 return NVPTX::SULD_2D_ARRAY_V4I8_ZERO_I; 397 case NVPTX::SULD_2D_ARRAY_V4I16_ZERO_R: 398 return NVPTX::SULD_2D_ARRAY_V4I16_ZERO_I; 399 case NVPTX::SULD_2D_ARRAY_V4I32_ZERO_R: 400 return NVPTX::SULD_2D_ARRAY_V4I32_ZERO_I; 401 case NVPTX::SULD_3D_V4I8_ZERO_R: 402 return NVPTX::SULD_3D_V4I8_ZERO_I; 403 case NVPTX::SULD_3D_V4I16_ZERO_R: 404 return NVPTX::SULD_3D_V4I16_ZERO_I; 405 case NVPTX::SULD_3D_V4I32_ZERO_R: 406 return NVPTX::SULD_3D_V4I32_ZERO_I; 407 default: 408 llvm_unreachable("Unhandled SULD opcode"); 409 } 410 } 411 412 static unsigned sustRegisterToIndexOpcode(unsigned RegOC) { 413 switch (RegOC) { 414 case NVPTX::SUST_B_1D_B8_CLAMP_R: 415 return NVPTX::SUST_B_1D_B8_CLAMP_I; 416 case NVPTX::SUST_B_1D_B16_CLAMP_R: 417 return NVPTX::SUST_B_1D_B16_CLAMP_I; 418 case NVPTX::SUST_B_1D_B32_CLAMP_R: 419 return NVPTX::SUST_B_1D_B32_CLAMP_I; 420 case NVPTX::SUST_B_1D_B64_CLAMP_R: 421 return NVPTX::SUST_B_1D_B64_CLAMP_I; 422 case NVPTX::SUST_B_1D_V2B8_CLAMP_R: 423 return NVPTX::SUST_B_1D_V2B8_CLAMP_I; 424 case NVPTX::SUST_B_1D_V2B16_CLAMP_R: 425 return NVPTX::SUST_B_1D_V2B16_CLAMP_I; 426 case NVPTX::SUST_B_1D_V2B32_CLAMP_R: 427 return NVPTX::SUST_B_1D_V2B32_CLAMP_I; 428 case NVPTX::SUST_B_1D_V2B64_CLAMP_R: 429 return NVPTX::SUST_B_1D_V2B64_CLAMP_I; 430 case NVPTX::SUST_B_1D_V4B8_CLAMP_R: 431 return NVPTX::SUST_B_1D_V4B8_CLAMP_I; 432 case NVPTX::SUST_B_1D_V4B16_CLAMP_R: 433 return NVPTX::SUST_B_1D_V4B16_CLAMP_I; 434 case NVPTX::SUST_B_1D_V4B32_CLAMP_R: 435 return NVPTX::SUST_B_1D_V4B32_CLAMP_I; 436 case NVPTX::SUST_B_1D_ARRAY_B8_CLAMP_R: 437 return NVPTX::SUST_B_1D_ARRAY_B8_CLAMP_I; 438 case NVPTX::SUST_B_1D_ARRAY_B16_CLAMP_R: 439 return NVPTX::SUST_B_1D_ARRAY_B16_CLAMP_I; 440 case NVPTX::SUST_B_1D_ARRAY_B32_CLAMP_R: 441 return NVPTX::SUST_B_1D_ARRAY_B32_CLAMP_I; 442 case NVPTX::SUST_B_1D_ARRAY_B64_CLAMP_R: 443 return NVPTX::SUST_B_1D_ARRAY_B64_CLAMP_I; 444 case NVPTX::SUST_B_1D_ARRAY_V2B8_CLAMP_R: 445 return NVPTX::SUST_B_1D_ARRAY_V2B8_CLAMP_I; 446 case NVPTX::SUST_B_1D_ARRAY_V2B16_CLAMP_R: 447 return NVPTX::SUST_B_1D_ARRAY_V2B16_CLAMP_I; 448 case NVPTX::SUST_B_1D_ARRAY_V2B32_CLAMP_R: 449 return NVPTX::SUST_B_1D_ARRAY_V2B32_CLAMP_I; 450 case NVPTX::SUST_B_1D_ARRAY_V2B64_CLAMP_R: 451 return NVPTX::SUST_B_1D_ARRAY_V2B64_CLAMP_I; 452 case NVPTX::SUST_B_1D_ARRAY_V4B8_CLAMP_R: 453 return NVPTX::SUST_B_1D_ARRAY_V4B8_CLAMP_I; 454 case NVPTX::SUST_B_1D_ARRAY_V4B16_CLAMP_R: 455 return NVPTX::SUST_B_1D_ARRAY_V4B16_CLAMP_I; 456 case NVPTX::SUST_B_1D_ARRAY_V4B32_CLAMP_R: 457 return NVPTX::SUST_B_1D_ARRAY_V4B32_CLAMP_I; 458 case NVPTX::SUST_B_2D_B8_CLAMP_R: 459 return NVPTX::SUST_B_2D_B8_CLAMP_I; 460 case NVPTX::SUST_B_2D_B16_CLAMP_R: 461 return NVPTX::SUST_B_2D_B16_CLAMP_I; 462 case NVPTX::SUST_B_2D_B32_CLAMP_R: 463 return NVPTX::SUST_B_2D_B32_CLAMP_I; 464 case NVPTX::SUST_B_2D_B64_CLAMP_R: 465 return NVPTX::SUST_B_2D_B64_CLAMP_I; 466 case NVPTX::SUST_B_2D_V2B8_CLAMP_R: 467 return NVPTX::SUST_B_2D_V2B8_CLAMP_I; 468 case NVPTX::SUST_B_2D_V2B16_CLAMP_R: 469 return NVPTX::SUST_B_2D_V2B16_CLAMP_I; 470 case NVPTX::SUST_B_2D_V2B32_CLAMP_R: 471 return NVPTX::SUST_B_2D_V2B32_CLAMP_I; 472 case NVPTX::SUST_B_2D_V2B64_CLAMP_R: 473 return NVPTX::SUST_B_2D_V2B64_CLAMP_I; 474 case NVPTX::SUST_B_2D_V4B8_CLAMP_R: 475 return NVPTX::SUST_B_2D_V4B8_CLAMP_I; 476 case NVPTX::SUST_B_2D_V4B16_CLAMP_R: 477 return NVPTX::SUST_B_2D_V4B16_CLAMP_I; 478 case NVPTX::SUST_B_2D_V4B32_CLAMP_R: 479 return NVPTX::SUST_B_2D_V4B32_CLAMP_I; 480 case NVPTX::SUST_B_2D_ARRAY_B8_CLAMP_R: 481 return NVPTX::SUST_B_2D_ARRAY_B8_CLAMP_I; 482 case NVPTX::SUST_B_2D_ARRAY_B16_CLAMP_R: 483 return NVPTX::SUST_B_2D_ARRAY_B16_CLAMP_I; 484 case NVPTX::SUST_B_2D_ARRAY_B32_CLAMP_R: 485 return NVPTX::SUST_B_2D_ARRAY_B32_CLAMP_I; 486 case NVPTX::SUST_B_2D_ARRAY_B64_CLAMP_R: 487 return NVPTX::SUST_B_2D_ARRAY_B64_CLAMP_I; 488 case NVPTX::SUST_B_2D_ARRAY_V2B8_CLAMP_R: 489 return NVPTX::SUST_B_2D_ARRAY_V2B8_CLAMP_I; 490 case NVPTX::SUST_B_2D_ARRAY_V2B16_CLAMP_R: 491 return NVPTX::SUST_B_2D_ARRAY_V2B16_CLAMP_I; 492 case NVPTX::SUST_B_2D_ARRAY_V2B32_CLAMP_R: 493 return NVPTX::SUST_B_2D_ARRAY_V2B32_CLAMP_I; 494 case NVPTX::SUST_B_2D_ARRAY_V2B64_CLAMP_R: 495 return NVPTX::SUST_B_2D_ARRAY_V2B64_CLAMP_I; 496 case NVPTX::SUST_B_2D_ARRAY_V4B8_CLAMP_R: 497 return NVPTX::SUST_B_2D_ARRAY_V4B8_CLAMP_I; 498 case NVPTX::SUST_B_2D_ARRAY_V4B16_CLAMP_R: 499 return NVPTX::SUST_B_2D_ARRAY_V4B16_CLAMP_I; 500 case NVPTX::SUST_B_2D_ARRAY_V4B32_CLAMP_R: 501 return NVPTX::SUST_B_2D_ARRAY_V4B32_CLAMP_I; 502 case NVPTX::SUST_B_3D_B8_CLAMP_R: 503 return NVPTX::SUST_B_3D_B8_CLAMP_I; 504 case NVPTX::SUST_B_3D_B16_CLAMP_R: 505 return NVPTX::SUST_B_3D_B16_CLAMP_I; 506 case NVPTX::SUST_B_3D_B32_CLAMP_R: 507 return NVPTX::SUST_B_3D_B32_CLAMP_I; 508 case NVPTX::SUST_B_3D_B64_CLAMP_R: 509 return NVPTX::SUST_B_3D_B64_CLAMP_I; 510 case NVPTX::SUST_B_3D_V2B8_CLAMP_R: 511 return NVPTX::SUST_B_3D_V2B8_CLAMP_I; 512 case NVPTX::SUST_B_3D_V2B16_CLAMP_R: 513 return NVPTX::SUST_B_3D_V2B16_CLAMP_I; 514 case NVPTX::SUST_B_3D_V2B32_CLAMP_R: 515 return NVPTX::SUST_B_3D_V2B32_CLAMP_I; 516 case NVPTX::SUST_B_3D_V2B64_CLAMP_R: 517 return NVPTX::SUST_B_3D_V2B64_CLAMP_I; 518 case NVPTX::SUST_B_3D_V4B8_CLAMP_R: 519 return NVPTX::SUST_B_3D_V4B8_CLAMP_I; 520 case NVPTX::SUST_B_3D_V4B16_CLAMP_R: 521 return NVPTX::SUST_B_3D_V4B16_CLAMP_I; 522 case NVPTX::SUST_B_3D_V4B32_CLAMP_R: 523 return NVPTX::SUST_B_3D_V4B32_CLAMP_I; 524 case NVPTX::SUST_B_1D_B8_TRAP_R: 525 return NVPTX::SUST_B_1D_B8_TRAP_I; 526 case NVPTX::SUST_B_1D_B16_TRAP_R: 527 return NVPTX::SUST_B_1D_B16_TRAP_I; 528 case NVPTX::SUST_B_1D_B32_TRAP_R: 529 return NVPTX::SUST_B_1D_B32_TRAP_I; 530 case NVPTX::SUST_B_1D_B64_TRAP_R: 531 return NVPTX::SUST_B_1D_B64_TRAP_I; 532 case NVPTX::SUST_B_1D_V2B8_TRAP_R: 533 return NVPTX::SUST_B_1D_V2B8_TRAP_I; 534 case NVPTX::SUST_B_1D_V2B16_TRAP_R: 535 return NVPTX::SUST_B_1D_V2B16_TRAP_I; 536 case NVPTX::SUST_B_1D_V2B32_TRAP_R: 537 return NVPTX::SUST_B_1D_V2B32_TRAP_I; 538 case NVPTX::SUST_B_1D_V2B64_TRAP_R: 539 return NVPTX::SUST_B_1D_V2B64_TRAP_I; 540 case NVPTX::SUST_B_1D_V4B8_TRAP_R: 541 return NVPTX::SUST_B_1D_V4B8_TRAP_I; 542 case NVPTX::SUST_B_1D_V4B16_TRAP_R: 543 return NVPTX::SUST_B_1D_V4B16_TRAP_I; 544 case NVPTX::SUST_B_1D_V4B32_TRAP_R: 545 return NVPTX::SUST_B_1D_V4B32_TRAP_I; 546 case NVPTX::SUST_B_1D_ARRAY_B8_TRAP_R: 547 return NVPTX::SUST_B_1D_ARRAY_B8_TRAP_I; 548 case NVPTX::SUST_B_1D_ARRAY_B16_TRAP_R: 549 return NVPTX::SUST_B_1D_ARRAY_B16_TRAP_I; 550 case NVPTX::SUST_B_1D_ARRAY_B32_TRAP_R: 551 return NVPTX::SUST_B_1D_ARRAY_B32_TRAP_I; 552 case NVPTX::SUST_B_1D_ARRAY_B64_TRAP_R: 553 return NVPTX::SUST_B_1D_ARRAY_B64_TRAP_I; 554 case NVPTX::SUST_B_1D_ARRAY_V2B8_TRAP_R: 555 return NVPTX::SUST_B_1D_ARRAY_V2B8_TRAP_I; 556 case NVPTX::SUST_B_1D_ARRAY_V2B16_TRAP_R: 557 return NVPTX::SUST_B_1D_ARRAY_V2B16_TRAP_I; 558 case NVPTX::SUST_B_1D_ARRAY_V2B32_TRAP_R: 559 return NVPTX::SUST_B_1D_ARRAY_V2B32_TRAP_I; 560 case NVPTX::SUST_B_1D_ARRAY_V2B64_TRAP_R: 561 return NVPTX::SUST_B_1D_ARRAY_V2B64_TRAP_I; 562 case NVPTX::SUST_B_1D_ARRAY_V4B8_TRAP_R: 563 return NVPTX::SUST_B_1D_ARRAY_V4B8_TRAP_I; 564 case NVPTX::SUST_B_1D_ARRAY_V4B16_TRAP_R: 565 return NVPTX::SUST_B_1D_ARRAY_V4B16_TRAP_I; 566 case NVPTX::SUST_B_1D_ARRAY_V4B32_TRAP_R: 567 return NVPTX::SUST_B_1D_ARRAY_V4B32_TRAP_I; 568 case NVPTX::SUST_B_2D_B8_TRAP_R: 569 return NVPTX::SUST_B_2D_B8_TRAP_I; 570 case NVPTX::SUST_B_2D_B16_TRAP_R: 571 return NVPTX::SUST_B_2D_B16_TRAP_I; 572 case NVPTX::SUST_B_2D_B32_TRAP_R: 573 return NVPTX::SUST_B_2D_B32_TRAP_I; 574 case NVPTX::SUST_B_2D_B64_TRAP_R: 575 return NVPTX::SUST_B_2D_B64_TRAP_I; 576 case NVPTX::SUST_B_2D_V2B8_TRAP_R: 577 return NVPTX::SUST_B_2D_V2B8_TRAP_I; 578 case NVPTX::SUST_B_2D_V2B16_TRAP_R: 579 return NVPTX::SUST_B_2D_V2B16_TRAP_I; 580 case NVPTX::SUST_B_2D_V2B32_TRAP_R: 581 return NVPTX::SUST_B_2D_V2B32_TRAP_I; 582 case NVPTX::SUST_B_2D_V2B64_TRAP_R: 583 return NVPTX::SUST_B_2D_V2B64_TRAP_I; 584 case NVPTX::SUST_B_2D_V4B8_TRAP_R: 585 return NVPTX::SUST_B_2D_V4B8_TRAP_I; 586 case NVPTX::SUST_B_2D_V4B16_TRAP_R: 587 return NVPTX::SUST_B_2D_V4B16_TRAP_I; 588 case NVPTX::SUST_B_2D_V4B32_TRAP_R: 589 return NVPTX::SUST_B_2D_V4B32_TRAP_I; 590 case NVPTX::SUST_B_2D_ARRAY_B8_TRAP_R: 591 return NVPTX::SUST_B_2D_ARRAY_B8_TRAP_I; 592 case NVPTX::SUST_B_2D_ARRAY_B16_TRAP_R: 593 return NVPTX::SUST_B_2D_ARRAY_B16_TRAP_I; 594 case NVPTX::SUST_B_2D_ARRAY_B32_TRAP_R: 595 return NVPTX::SUST_B_2D_ARRAY_B32_TRAP_I; 596 case NVPTX::SUST_B_2D_ARRAY_B64_TRAP_R: 597 return NVPTX::SUST_B_2D_ARRAY_B64_TRAP_I; 598 case NVPTX::SUST_B_2D_ARRAY_V2B8_TRAP_R: 599 return NVPTX::SUST_B_2D_ARRAY_V2B8_TRAP_I; 600 case NVPTX::SUST_B_2D_ARRAY_V2B16_TRAP_R: 601 return NVPTX::SUST_B_2D_ARRAY_V2B16_TRAP_I; 602 case NVPTX::SUST_B_2D_ARRAY_V2B32_TRAP_R: 603 return NVPTX::SUST_B_2D_ARRAY_V2B32_TRAP_I; 604 case NVPTX::SUST_B_2D_ARRAY_V2B64_TRAP_R: 605 return NVPTX::SUST_B_2D_ARRAY_V2B64_TRAP_I; 606 case NVPTX::SUST_B_2D_ARRAY_V4B8_TRAP_R: 607 return NVPTX::SUST_B_2D_ARRAY_V4B8_TRAP_I; 608 case NVPTX::SUST_B_2D_ARRAY_V4B16_TRAP_R: 609 return NVPTX::SUST_B_2D_ARRAY_V4B16_TRAP_I; 610 case NVPTX::SUST_B_2D_ARRAY_V4B32_TRAP_R: 611 return NVPTX::SUST_B_2D_ARRAY_V4B32_TRAP_I; 612 case NVPTX::SUST_B_3D_B8_TRAP_R: 613 return NVPTX::SUST_B_3D_B8_TRAP_I; 614 case NVPTX::SUST_B_3D_B16_TRAP_R: 615 return NVPTX::SUST_B_3D_B16_TRAP_I; 616 case NVPTX::SUST_B_3D_B32_TRAP_R: 617 return NVPTX::SUST_B_3D_B32_TRAP_I; 618 case NVPTX::SUST_B_3D_B64_TRAP_R: 619 return NVPTX::SUST_B_3D_B64_TRAP_I; 620 case NVPTX::SUST_B_3D_V2B8_TRAP_R: 621 return NVPTX::SUST_B_3D_V2B8_TRAP_I; 622 case NVPTX::SUST_B_3D_V2B16_TRAP_R: 623 return NVPTX::SUST_B_3D_V2B16_TRAP_I; 624 case NVPTX::SUST_B_3D_V2B32_TRAP_R: 625 return NVPTX::SUST_B_3D_V2B32_TRAP_I; 626 case NVPTX::SUST_B_3D_V2B64_TRAP_R: 627 return NVPTX::SUST_B_3D_V2B64_TRAP_I; 628 case NVPTX::SUST_B_3D_V4B8_TRAP_R: 629 return NVPTX::SUST_B_3D_V4B8_TRAP_I; 630 case NVPTX::SUST_B_3D_V4B16_TRAP_R: 631 return NVPTX::SUST_B_3D_V4B16_TRAP_I; 632 case NVPTX::SUST_B_3D_V4B32_TRAP_R: 633 return NVPTX::SUST_B_3D_V4B32_TRAP_I; 634 case NVPTX::SUST_B_1D_B8_ZERO_R: 635 return NVPTX::SUST_B_1D_B8_ZERO_I; 636 case NVPTX::SUST_B_1D_B16_ZERO_R: 637 return NVPTX::SUST_B_1D_B16_ZERO_I; 638 case NVPTX::SUST_B_1D_B32_ZERO_R: 639 return NVPTX::SUST_B_1D_B32_ZERO_I; 640 case NVPTX::SUST_B_1D_B64_ZERO_R: 641 return NVPTX::SUST_B_1D_B64_ZERO_I; 642 case NVPTX::SUST_B_1D_V2B8_ZERO_R: 643 return NVPTX::SUST_B_1D_V2B8_ZERO_I; 644 case NVPTX::SUST_B_1D_V2B16_ZERO_R: 645 return NVPTX::SUST_B_1D_V2B16_ZERO_I; 646 case NVPTX::SUST_B_1D_V2B32_ZERO_R: 647 return NVPTX::SUST_B_1D_V2B32_ZERO_I; 648 case NVPTX::SUST_B_1D_V2B64_ZERO_R: 649 return NVPTX::SUST_B_1D_V2B64_ZERO_I; 650 case NVPTX::SUST_B_1D_V4B8_ZERO_R: 651 return NVPTX::SUST_B_1D_V4B8_ZERO_I; 652 case NVPTX::SUST_B_1D_V4B16_ZERO_R: 653 return NVPTX::SUST_B_1D_V4B16_ZERO_I; 654 case NVPTX::SUST_B_1D_V4B32_ZERO_R: 655 return NVPTX::SUST_B_1D_V4B32_ZERO_I; 656 case NVPTX::SUST_B_1D_ARRAY_B8_ZERO_R: 657 return NVPTX::SUST_B_1D_ARRAY_B8_ZERO_I; 658 case NVPTX::SUST_B_1D_ARRAY_B16_ZERO_R: 659 return NVPTX::SUST_B_1D_ARRAY_B16_ZERO_I; 660 case NVPTX::SUST_B_1D_ARRAY_B32_ZERO_R: 661 return NVPTX::SUST_B_1D_ARRAY_B32_ZERO_I; 662 case NVPTX::SUST_B_1D_ARRAY_B64_ZERO_R: 663 return NVPTX::SUST_B_1D_ARRAY_B64_ZERO_I; 664 case NVPTX::SUST_B_1D_ARRAY_V2B8_ZERO_R: 665 return NVPTX::SUST_B_1D_ARRAY_V2B8_ZERO_I; 666 case NVPTX::SUST_B_1D_ARRAY_V2B16_ZERO_R: 667 return NVPTX::SUST_B_1D_ARRAY_V2B16_ZERO_I; 668 case NVPTX::SUST_B_1D_ARRAY_V2B32_ZERO_R: 669 return NVPTX::SUST_B_1D_ARRAY_V2B32_ZERO_I; 670 case NVPTX::SUST_B_1D_ARRAY_V2B64_ZERO_R: 671 return NVPTX::SUST_B_1D_ARRAY_V2B64_ZERO_I; 672 case NVPTX::SUST_B_1D_ARRAY_V4B8_ZERO_R: 673 return NVPTX::SUST_B_1D_ARRAY_V4B8_ZERO_I; 674 case NVPTX::SUST_B_1D_ARRAY_V4B16_ZERO_R: 675 return NVPTX::SUST_B_1D_ARRAY_V4B16_ZERO_I; 676 case NVPTX::SUST_B_1D_ARRAY_V4B32_ZERO_R: 677 return NVPTX::SUST_B_1D_ARRAY_V4B32_ZERO_I; 678 case NVPTX::SUST_B_2D_B8_ZERO_R: 679 return NVPTX::SUST_B_2D_B8_ZERO_I; 680 case NVPTX::SUST_B_2D_B16_ZERO_R: 681 return NVPTX::SUST_B_2D_B16_ZERO_I; 682 case NVPTX::SUST_B_2D_B32_ZERO_R: 683 return NVPTX::SUST_B_2D_B32_ZERO_I; 684 case NVPTX::SUST_B_2D_B64_ZERO_R: 685 return NVPTX::SUST_B_2D_B64_ZERO_I; 686 case NVPTX::SUST_B_2D_V2B8_ZERO_R: 687 return NVPTX::SUST_B_2D_V2B8_ZERO_I; 688 case NVPTX::SUST_B_2D_V2B16_ZERO_R: 689 return NVPTX::SUST_B_2D_V2B16_ZERO_I; 690 case NVPTX::SUST_B_2D_V2B32_ZERO_R: 691 return NVPTX::SUST_B_2D_V2B32_ZERO_I; 692 case NVPTX::SUST_B_2D_V2B64_ZERO_R: 693 return NVPTX::SUST_B_2D_V2B64_ZERO_I; 694 case NVPTX::SUST_B_2D_V4B8_ZERO_R: 695 return NVPTX::SUST_B_2D_V4B8_ZERO_I; 696 case NVPTX::SUST_B_2D_V4B16_ZERO_R: 697 return NVPTX::SUST_B_2D_V4B16_ZERO_I; 698 case NVPTX::SUST_B_2D_V4B32_ZERO_R: 699 return NVPTX::SUST_B_2D_V4B32_ZERO_I; 700 case NVPTX::SUST_B_2D_ARRAY_B8_ZERO_R: 701 return NVPTX::SUST_B_2D_ARRAY_B8_ZERO_I; 702 case NVPTX::SUST_B_2D_ARRAY_B16_ZERO_R: 703 return NVPTX::SUST_B_2D_ARRAY_B16_ZERO_I; 704 case NVPTX::SUST_B_2D_ARRAY_B32_ZERO_R: 705 return NVPTX::SUST_B_2D_ARRAY_B32_ZERO_I; 706 case NVPTX::SUST_B_2D_ARRAY_B64_ZERO_R: 707 return NVPTX::SUST_B_2D_ARRAY_B64_ZERO_I; 708 case NVPTX::SUST_B_2D_ARRAY_V2B8_ZERO_R: 709 return NVPTX::SUST_B_2D_ARRAY_V2B8_ZERO_I; 710 case NVPTX::SUST_B_2D_ARRAY_V2B16_ZERO_R: 711 return NVPTX::SUST_B_2D_ARRAY_V2B16_ZERO_I; 712 case NVPTX::SUST_B_2D_ARRAY_V2B32_ZERO_R: 713 return NVPTX::SUST_B_2D_ARRAY_V2B32_ZERO_I; 714 case NVPTX::SUST_B_2D_ARRAY_V2B64_ZERO_R: 715 return NVPTX::SUST_B_2D_ARRAY_V2B64_ZERO_I; 716 case NVPTX::SUST_B_2D_ARRAY_V4B8_ZERO_R: 717 return NVPTX::SUST_B_2D_ARRAY_V4B8_ZERO_I; 718 case NVPTX::SUST_B_2D_ARRAY_V4B16_ZERO_R: 719 return NVPTX::SUST_B_2D_ARRAY_V4B16_ZERO_I; 720 case NVPTX::SUST_B_2D_ARRAY_V4B32_ZERO_R: 721 return NVPTX::SUST_B_2D_ARRAY_V4B32_ZERO_I; 722 case NVPTX::SUST_B_3D_B8_ZERO_R: 723 return NVPTX::SUST_B_3D_B8_ZERO_I; 724 case NVPTX::SUST_B_3D_B16_ZERO_R: 725 return NVPTX::SUST_B_3D_B16_ZERO_I; 726 case NVPTX::SUST_B_3D_B32_ZERO_R: 727 return NVPTX::SUST_B_3D_B32_ZERO_I; 728 case NVPTX::SUST_B_3D_B64_ZERO_R: 729 return NVPTX::SUST_B_3D_B64_ZERO_I; 730 case NVPTX::SUST_B_3D_V2B8_ZERO_R: 731 return NVPTX::SUST_B_3D_V2B8_ZERO_I; 732 case NVPTX::SUST_B_3D_V2B16_ZERO_R: 733 return NVPTX::SUST_B_3D_V2B16_ZERO_I; 734 case NVPTX::SUST_B_3D_V2B32_ZERO_R: 735 return NVPTX::SUST_B_3D_V2B32_ZERO_I; 736 case NVPTX::SUST_B_3D_V2B64_ZERO_R: 737 return NVPTX::SUST_B_3D_V2B64_ZERO_I; 738 case NVPTX::SUST_B_3D_V4B8_ZERO_R: 739 return NVPTX::SUST_B_3D_V4B8_ZERO_I; 740 case NVPTX::SUST_B_3D_V4B16_ZERO_R: 741 return NVPTX::SUST_B_3D_V4B16_ZERO_I; 742 case NVPTX::SUST_B_3D_V4B32_ZERO_R: 743 return NVPTX::SUST_B_3D_V4B32_ZERO_I; 744 case NVPTX::SUST_P_1D_B8_TRAP_R: 745 return NVPTX::SUST_P_1D_B8_TRAP_I; 746 case NVPTX::SUST_P_1D_B16_TRAP_R: 747 return NVPTX::SUST_P_1D_B16_TRAP_I; 748 case NVPTX::SUST_P_1D_B32_TRAP_R: 749 return NVPTX::SUST_P_1D_B32_TRAP_I; 750 case NVPTX::SUST_P_1D_V2B8_TRAP_R: 751 return NVPTX::SUST_P_1D_V2B8_TRAP_I; 752 case NVPTX::SUST_P_1D_V2B16_TRAP_R: 753 return NVPTX::SUST_P_1D_V2B16_TRAP_I; 754 case NVPTX::SUST_P_1D_V2B32_TRAP_R: 755 return NVPTX::SUST_P_1D_V2B32_TRAP_I; 756 case NVPTX::SUST_P_1D_V4B8_TRAP_R: 757 return NVPTX::SUST_P_1D_V4B8_TRAP_I; 758 case NVPTX::SUST_P_1D_V4B16_TRAP_R: 759 return NVPTX::SUST_P_1D_V4B16_TRAP_I; 760 case NVPTX::SUST_P_1D_V4B32_TRAP_R: 761 return NVPTX::SUST_P_1D_V4B32_TRAP_I; 762 case NVPTX::SUST_P_1D_ARRAY_B8_TRAP_R: 763 return NVPTX::SUST_P_1D_ARRAY_B8_TRAP_I; 764 case NVPTX::SUST_P_1D_ARRAY_B16_TRAP_R: 765 return NVPTX::SUST_P_1D_ARRAY_B16_TRAP_I; 766 case NVPTX::SUST_P_1D_ARRAY_B32_TRAP_R: 767 return NVPTX::SUST_P_1D_ARRAY_B32_TRAP_I; 768 case NVPTX::SUST_P_1D_ARRAY_V2B8_TRAP_R: 769 return NVPTX::SUST_P_1D_ARRAY_V2B8_TRAP_I; 770 case NVPTX::SUST_P_1D_ARRAY_V2B16_TRAP_R: 771 return NVPTX::SUST_P_1D_ARRAY_V2B16_TRAP_I; 772 case NVPTX::SUST_P_1D_ARRAY_V2B32_TRAP_R: 773 return NVPTX::SUST_P_1D_ARRAY_V2B32_TRAP_I; 774 case NVPTX::SUST_P_1D_ARRAY_V4B8_TRAP_R: 775 return NVPTX::SUST_P_1D_ARRAY_V4B8_TRAP_I; 776 case NVPTX::SUST_P_1D_ARRAY_V4B16_TRAP_R: 777 return NVPTX::SUST_P_1D_ARRAY_V4B16_TRAP_I; 778 case NVPTX::SUST_P_1D_ARRAY_V4B32_TRAP_R: 779 return NVPTX::SUST_P_1D_ARRAY_V4B32_TRAP_I; 780 case NVPTX::SUST_P_2D_B8_TRAP_R: 781 return NVPTX::SUST_P_2D_B8_TRAP_I; 782 case NVPTX::SUST_P_2D_B16_TRAP_R: 783 return NVPTX::SUST_P_2D_B16_TRAP_I; 784 case NVPTX::SUST_P_2D_B32_TRAP_R: 785 return NVPTX::SUST_P_2D_B32_TRAP_I; 786 case NVPTX::SUST_P_2D_V2B8_TRAP_R: 787 return NVPTX::SUST_P_2D_V2B8_TRAP_I; 788 case NVPTX::SUST_P_2D_V2B16_TRAP_R: 789 return NVPTX::SUST_P_2D_V2B16_TRAP_I; 790 case NVPTX::SUST_P_2D_V2B32_TRAP_R: 791 return NVPTX::SUST_P_2D_V2B32_TRAP_I; 792 case NVPTX::SUST_P_2D_V4B8_TRAP_R: 793 return NVPTX::SUST_P_2D_V4B8_TRAP_I; 794 case NVPTX::SUST_P_2D_V4B16_TRAP_R: 795 return NVPTX::SUST_P_2D_V4B16_TRAP_I; 796 case NVPTX::SUST_P_2D_V4B32_TRAP_R: 797 return NVPTX::SUST_P_2D_V4B32_TRAP_I; 798 case NVPTX::SUST_P_2D_ARRAY_B8_TRAP_R: 799 return NVPTX::SUST_P_2D_ARRAY_B8_TRAP_I; 800 case NVPTX::SUST_P_2D_ARRAY_B16_TRAP_R: 801 return NVPTX::SUST_P_2D_ARRAY_B16_TRAP_I; 802 case NVPTX::SUST_P_2D_ARRAY_B32_TRAP_R: 803 return NVPTX::SUST_P_2D_ARRAY_B32_TRAP_I; 804 case NVPTX::SUST_P_2D_ARRAY_V2B8_TRAP_R: 805 return NVPTX::SUST_P_2D_ARRAY_V2B8_TRAP_I; 806 case NVPTX::SUST_P_2D_ARRAY_V2B16_TRAP_R: 807 return NVPTX::SUST_P_2D_ARRAY_V2B16_TRAP_I; 808 case NVPTX::SUST_P_2D_ARRAY_V2B32_TRAP_R: 809 return NVPTX::SUST_P_2D_ARRAY_V2B32_TRAP_I; 810 case NVPTX::SUST_P_2D_ARRAY_V4B8_TRAP_R: 811 return NVPTX::SUST_P_2D_ARRAY_V4B8_TRAP_I; 812 case NVPTX::SUST_P_2D_ARRAY_V4B16_TRAP_R: 813 return NVPTX::SUST_P_2D_ARRAY_V4B16_TRAP_I; 814 case NVPTX::SUST_P_2D_ARRAY_V4B32_TRAP_R: 815 return NVPTX::SUST_P_2D_ARRAY_V4B32_TRAP_I; 816 case NVPTX::SUST_P_3D_B8_TRAP_R: 817 return NVPTX::SUST_P_3D_B8_TRAP_I; 818 case NVPTX::SUST_P_3D_B16_TRAP_R: 819 return NVPTX::SUST_P_3D_B16_TRAP_I; 820 case NVPTX::SUST_P_3D_B32_TRAP_R: 821 return NVPTX::SUST_P_3D_B32_TRAP_I; 822 case NVPTX::SUST_P_3D_V2B8_TRAP_R: 823 return NVPTX::SUST_P_3D_V2B8_TRAP_I; 824 case NVPTX::SUST_P_3D_V2B16_TRAP_R: 825 return NVPTX::SUST_P_3D_V2B16_TRAP_I; 826 case NVPTX::SUST_P_3D_V2B32_TRAP_R: 827 return NVPTX::SUST_P_3D_V2B32_TRAP_I; 828 case NVPTX::SUST_P_3D_V4B8_TRAP_R: 829 return NVPTX::SUST_P_3D_V4B8_TRAP_I; 830 case NVPTX::SUST_P_3D_V4B16_TRAP_R: 831 return NVPTX::SUST_P_3D_V4B16_TRAP_I; 832 case NVPTX::SUST_P_3D_V4B32_TRAP_R: 833 return NVPTX::SUST_P_3D_V4B32_TRAP_I; 834 default: 835 llvm_unreachable("Unhandled SUST opcode"); 836 } 837 } 838 839 static unsigned texRegisterToIndexOpcode(unsigned RegOC) { 840 switch (RegOC) { 841 case NVPTX::TEX_1D_F32_S32_RR: 842 return NVPTX::TEX_1D_F32_S32_IR; 843 case NVPTX::TEX_1D_F32_S32_RI: 844 return NVPTX::TEX_1D_F32_S32_II; 845 case NVPTX::TEX_1D_F32_F32_RR: 846 return NVPTX::TEX_1D_F32_F32_IR; 847 case NVPTX::TEX_1D_F32_F32_RI: 848 return NVPTX::TEX_1D_F32_F32_II; 849 case NVPTX::TEX_1D_F32_F32_LEVEL_RR: 850 return NVPTX::TEX_1D_F32_F32_LEVEL_IR; 851 case NVPTX::TEX_1D_F32_F32_LEVEL_RI: 852 return NVPTX::TEX_1D_F32_F32_LEVEL_II; 853 case NVPTX::TEX_1D_F32_F32_GRAD_RR: 854 return NVPTX::TEX_1D_F32_F32_GRAD_IR; 855 case NVPTX::TEX_1D_F32_F32_GRAD_RI: 856 return NVPTX::TEX_1D_F32_F32_GRAD_II; 857 case NVPTX::TEX_1D_S32_S32_RR: 858 return NVPTX::TEX_1D_S32_S32_IR; 859 case NVPTX::TEX_1D_S32_S32_RI: 860 return NVPTX::TEX_1D_S32_S32_II; 861 case NVPTX::TEX_1D_S32_F32_RR: 862 return NVPTX::TEX_1D_S32_F32_IR; 863 case NVPTX::TEX_1D_S32_F32_RI: 864 return NVPTX::TEX_1D_S32_F32_II; 865 case NVPTX::TEX_1D_S32_F32_LEVEL_RR: 866 return NVPTX::TEX_1D_S32_F32_LEVEL_IR; 867 case NVPTX::TEX_1D_S32_F32_LEVEL_RI: 868 return NVPTX::TEX_1D_S32_F32_LEVEL_II; 869 case NVPTX::TEX_1D_S32_F32_GRAD_RR: 870 return NVPTX::TEX_1D_S32_F32_GRAD_IR; 871 case NVPTX::TEX_1D_S32_F32_GRAD_RI: 872 return NVPTX::TEX_1D_S32_F32_GRAD_II; 873 case NVPTX::TEX_1D_U32_S32_RR: 874 return NVPTX::TEX_1D_U32_S32_IR; 875 case NVPTX::TEX_1D_U32_S32_RI: 876 return NVPTX::TEX_1D_U32_S32_II; 877 case NVPTX::TEX_1D_U32_F32_RR: 878 return NVPTX::TEX_1D_U32_F32_IR; 879 case NVPTX::TEX_1D_U32_F32_RI: 880 return NVPTX::TEX_1D_U32_F32_II; 881 case NVPTX::TEX_1D_U32_F32_LEVEL_RR: 882 return NVPTX::TEX_1D_U32_F32_LEVEL_IR; 883 case NVPTX::TEX_1D_U32_F32_LEVEL_RI: 884 return NVPTX::TEX_1D_U32_F32_LEVEL_II; 885 case NVPTX::TEX_1D_U32_F32_GRAD_RR: 886 return NVPTX::TEX_1D_U32_F32_GRAD_IR; 887 case NVPTX::TEX_1D_U32_F32_GRAD_RI: 888 return NVPTX::TEX_1D_U32_F32_GRAD_II; 889 case NVPTX::TEX_1D_ARRAY_F32_S32_RR: 890 return NVPTX::TEX_1D_ARRAY_F32_S32_IR; 891 case NVPTX::TEX_1D_ARRAY_F32_S32_RI: 892 return NVPTX::TEX_1D_ARRAY_F32_S32_II; 893 case NVPTX::TEX_1D_ARRAY_F32_F32_RR: 894 return NVPTX::TEX_1D_ARRAY_F32_F32_IR; 895 case NVPTX::TEX_1D_ARRAY_F32_F32_RI: 896 return NVPTX::TEX_1D_ARRAY_F32_F32_II; 897 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RR: 898 return NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_IR; 899 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RI: 900 return NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_II; 901 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RR: 902 return NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_IR; 903 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RI: 904 return NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_II; 905 case NVPTX::TEX_1D_ARRAY_S32_S32_RR: 906 return NVPTX::TEX_1D_ARRAY_S32_S32_IR; 907 case NVPTX::TEX_1D_ARRAY_S32_S32_RI: 908 return NVPTX::TEX_1D_ARRAY_S32_S32_II; 909 case NVPTX::TEX_1D_ARRAY_S32_F32_RR: 910 return NVPTX::TEX_1D_ARRAY_S32_F32_IR; 911 case NVPTX::TEX_1D_ARRAY_S32_F32_RI: 912 return NVPTX::TEX_1D_ARRAY_S32_F32_II; 913 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RR: 914 return NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_IR; 915 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RI: 916 return NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_II; 917 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RR: 918 return NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_IR; 919 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RI: 920 return NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_II; 921 case NVPTX::TEX_1D_ARRAY_U32_S32_RR: 922 return NVPTX::TEX_1D_ARRAY_U32_S32_IR; 923 case NVPTX::TEX_1D_ARRAY_U32_S32_RI: 924 return NVPTX::TEX_1D_ARRAY_U32_S32_II; 925 case NVPTX::TEX_1D_ARRAY_U32_F32_RR: 926 return NVPTX::TEX_1D_ARRAY_U32_F32_IR; 927 case NVPTX::TEX_1D_ARRAY_U32_F32_RI: 928 return NVPTX::TEX_1D_ARRAY_U32_F32_II; 929 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RR: 930 return NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_IR; 931 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RI: 932 return NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_II; 933 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RR: 934 return NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_IR; 935 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RI: 936 return NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_II; 937 case NVPTX::TEX_2D_F32_S32_RR: 938 return NVPTX::TEX_2D_F32_S32_IR; 939 case NVPTX::TEX_2D_F32_S32_RI: 940 return NVPTX::TEX_2D_F32_S32_II; 941 case NVPTX::TEX_2D_F32_F32_RR: 942 return NVPTX::TEX_2D_F32_F32_IR; 943 case NVPTX::TEX_2D_F32_F32_RI: 944 return NVPTX::TEX_2D_F32_F32_II; 945 case NVPTX::TEX_2D_F32_F32_LEVEL_RR: 946 return NVPTX::TEX_2D_F32_F32_LEVEL_IR; 947 case NVPTX::TEX_2D_F32_F32_LEVEL_RI: 948 return NVPTX::TEX_2D_F32_F32_LEVEL_II; 949 case NVPTX::TEX_2D_F32_F32_GRAD_RR: 950 return NVPTX::TEX_2D_F32_F32_GRAD_IR; 951 case NVPTX::TEX_2D_F32_F32_GRAD_RI: 952 return NVPTX::TEX_2D_F32_F32_GRAD_II; 953 case NVPTX::TEX_2D_S32_S32_RR: 954 return NVPTX::TEX_2D_S32_S32_IR; 955 case NVPTX::TEX_2D_S32_S32_RI: 956 return NVPTX::TEX_2D_S32_S32_II; 957 case NVPTX::TEX_2D_S32_F32_RR: 958 return NVPTX::TEX_2D_S32_F32_IR; 959 case NVPTX::TEX_2D_S32_F32_RI: 960 return NVPTX::TEX_2D_S32_F32_II; 961 case NVPTX::TEX_2D_S32_F32_LEVEL_RR: 962 return NVPTX::TEX_2D_S32_F32_LEVEL_IR; 963 case NVPTX::TEX_2D_S32_F32_LEVEL_RI: 964 return NVPTX::TEX_2D_S32_F32_LEVEL_II; 965 case NVPTX::TEX_2D_S32_F32_GRAD_RR: 966 return NVPTX::TEX_2D_S32_F32_GRAD_IR; 967 case NVPTX::TEX_2D_S32_F32_GRAD_RI: 968 return NVPTX::TEX_2D_S32_F32_GRAD_II; 969 case NVPTX::TEX_2D_U32_S32_RR: 970 return NVPTX::TEX_2D_U32_S32_IR; 971 case NVPTX::TEX_2D_U32_S32_RI: 972 return NVPTX::TEX_2D_U32_S32_II; 973 case NVPTX::TEX_2D_U32_F32_RR: 974 return NVPTX::TEX_2D_U32_F32_IR; 975 case NVPTX::TEX_2D_U32_F32_RI: 976 return NVPTX::TEX_2D_U32_F32_II; 977 case NVPTX::TEX_2D_U32_F32_LEVEL_RR: 978 return NVPTX::TEX_2D_U32_F32_LEVEL_IR; 979 case NVPTX::TEX_2D_U32_F32_LEVEL_RI: 980 return NVPTX::TEX_2D_U32_F32_LEVEL_II; 981 case NVPTX::TEX_2D_U32_F32_GRAD_RR: 982 return NVPTX::TEX_2D_U32_F32_GRAD_IR; 983 case NVPTX::TEX_2D_U32_F32_GRAD_RI: 984 return NVPTX::TEX_2D_U32_F32_GRAD_II; 985 case NVPTX::TEX_2D_ARRAY_F32_S32_RR: 986 return NVPTX::TEX_2D_ARRAY_F32_S32_IR; 987 case NVPTX::TEX_2D_ARRAY_F32_S32_RI: 988 return NVPTX::TEX_2D_ARRAY_F32_S32_II; 989 case NVPTX::TEX_2D_ARRAY_F32_F32_RR: 990 return NVPTX::TEX_2D_ARRAY_F32_F32_IR; 991 case NVPTX::TEX_2D_ARRAY_F32_F32_RI: 992 return NVPTX::TEX_2D_ARRAY_F32_F32_II; 993 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RR: 994 return NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_IR; 995 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RI: 996 return NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_II; 997 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RR: 998 return NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_IR; 999 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RI: 1000 return NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_II; 1001 case NVPTX::TEX_2D_ARRAY_S32_S32_RR: 1002 return NVPTX::TEX_2D_ARRAY_S32_S32_IR; 1003 case NVPTX::TEX_2D_ARRAY_S32_S32_RI: 1004 return NVPTX::TEX_2D_ARRAY_S32_S32_II; 1005 case NVPTX::TEX_2D_ARRAY_S32_F32_RR: 1006 return NVPTX::TEX_2D_ARRAY_S32_F32_IR; 1007 case NVPTX::TEX_2D_ARRAY_S32_F32_RI: 1008 return NVPTX::TEX_2D_ARRAY_S32_F32_II; 1009 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RR: 1010 return NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_IR; 1011 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RI: 1012 return NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_II; 1013 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RR: 1014 return NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_IR; 1015 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RI: 1016 return NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_II; 1017 case NVPTX::TEX_2D_ARRAY_U32_S32_RR: 1018 return NVPTX::TEX_2D_ARRAY_U32_S32_IR; 1019 case NVPTX::TEX_2D_ARRAY_U32_S32_RI: 1020 return NVPTX::TEX_2D_ARRAY_U32_S32_II; 1021 case NVPTX::TEX_2D_ARRAY_U32_F32_RR: 1022 return NVPTX::TEX_2D_ARRAY_U32_F32_IR; 1023 case NVPTX::TEX_2D_ARRAY_U32_F32_RI: 1024 return NVPTX::TEX_2D_ARRAY_U32_F32_II; 1025 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RR: 1026 return NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_IR; 1027 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RI: 1028 return NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_II; 1029 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RR: 1030 return NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_IR; 1031 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RI: 1032 return NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_II; 1033 case NVPTX::TEX_3D_F32_S32_RR: 1034 return NVPTX::TEX_3D_F32_S32_IR; 1035 case NVPTX::TEX_3D_F32_S32_RI: 1036 return NVPTX::TEX_3D_F32_S32_II; 1037 case NVPTX::TEX_3D_F32_F32_RR: 1038 return NVPTX::TEX_3D_F32_F32_IR; 1039 case NVPTX::TEX_3D_F32_F32_RI: 1040 return NVPTX::TEX_3D_F32_F32_II; 1041 case NVPTX::TEX_3D_F32_F32_LEVEL_RR: 1042 return NVPTX::TEX_3D_F32_F32_LEVEL_IR; 1043 case NVPTX::TEX_3D_F32_F32_LEVEL_RI: 1044 return NVPTX::TEX_3D_F32_F32_LEVEL_II; 1045 case NVPTX::TEX_3D_F32_F32_GRAD_RR: 1046 return NVPTX::TEX_3D_F32_F32_GRAD_IR; 1047 case NVPTX::TEX_3D_F32_F32_GRAD_RI: 1048 return NVPTX::TEX_3D_F32_F32_GRAD_II; 1049 case NVPTX::TEX_3D_S32_S32_RR: 1050 return NVPTX::TEX_3D_S32_S32_IR; 1051 case NVPTX::TEX_3D_S32_S32_RI: 1052 return NVPTX::TEX_3D_S32_S32_II; 1053 case NVPTX::TEX_3D_S32_F32_RR: 1054 return NVPTX::TEX_3D_S32_F32_IR; 1055 case NVPTX::TEX_3D_S32_F32_RI: 1056 return NVPTX::TEX_3D_S32_F32_II; 1057 case NVPTX::TEX_3D_S32_F32_LEVEL_RR: 1058 return NVPTX::TEX_3D_S32_F32_LEVEL_IR; 1059 case NVPTX::TEX_3D_S32_F32_LEVEL_RI: 1060 return NVPTX::TEX_3D_S32_F32_LEVEL_II; 1061 case NVPTX::TEX_3D_S32_F32_GRAD_RR: 1062 return NVPTX::TEX_3D_S32_F32_GRAD_IR; 1063 case NVPTX::TEX_3D_S32_F32_GRAD_RI: 1064 return NVPTX::TEX_3D_S32_F32_GRAD_II; 1065 case NVPTX::TEX_3D_U32_S32_RR: 1066 return NVPTX::TEX_3D_U32_S32_IR; 1067 case NVPTX::TEX_3D_U32_S32_RI: 1068 return NVPTX::TEX_3D_U32_S32_II; 1069 case NVPTX::TEX_3D_U32_F32_RR: 1070 return NVPTX::TEX_3D_U32_F32_IR; 1071 case NVPTX::TEX_3D_U32_F32_RI: 1072 return NVPTX::TEX_3D_U32_F32_II; 1073 case NVPTX::TEX_3D_U32_F32_LEVEL_RR: 1074 return NVPTX::TEX_3D_U32_F32_LEVEL_IR; 1075 case NVPTX::TEX_3D_U32_F32_LEVEL_RI: 1076 return NVPTX::TEX_3D_U32_F32_LEVEL_II; 1077 case NVPTX::TEX_3D_U32_F32_GRAD_RR: 1078 return NVPTX::TEX_3D_U32_F32_GRAD_IR; 1079 case NVPTX::TEX_3D_U32_F32_GRAD_RI: 1080 return NVPTX::TEX_3D_U32_F32_GRAD_II; 1081 case NVPTX::TEX_CUBE_F32_F32_RR: 1082 return NVPTX::TEX_CUBE_F32_F32_IR; 1083 case NVPTX::TEX_CUBE_F32_F32_RI: 1084 return NVPTX::TEX_CUBE_F32_F32_II; 1085 case NVPTX::TEX_CUBE_F32_F32_LEVEL_RR: 1086 return NVPTX::TEX_CUBE_F32_F32_LEVEL_IR; 1087 case NVPTX::TEX_CUBE_F32_F32_LEVEL_RI: 1088 return NVPTX::TEX_CUBE_F32_F32_LEVEL_II; 1089 case NVPTX::TEX_CUBE_S32_F32_RR: 1090 return NVPTX::TEX_CUBE_S32_F32_IR; 1091 case NVPTX::TEX_CUBE_S32_F32_RI: 1092 return NVPTX::TEX_CUBE_S32_F32_II; 1093 case NVPTX::TEX_CUBE_S32_F32_LEVEL_RR: 1094 return NVPTX::TEX_CUBE_S32_F32_LEVEL_IR; 1095 case NVPTX::TEX_CUBE_S32_F32_LEVEL_RI: 1096 return NVPTX::TEX_CUBE_S32_F32_LEVEL_II; 1097 case NVPTX::TEX_CUBE_U32_F32_RR: 1098 return NVPTX::TEX_CUBE_U32_F32_IR; 1099 case NVPTX::TEX_CUBE_U32_F32_RI: 1100 return NVPTX::TEX_CUBE_U32_F32_II; 1101 case NVPTX::TEX_CUBE_U32_F32_LEVEL_RR: 1102 return NVPTX::TEX_CUBE_U32_F32_LEVEL_IR; 1103 case NVPTX::TEX_CUBE_U32_F32_LEVEL_RI: 1104 return NVPTX::TEX_CUBE_U32_F32_LEVEL_II; 1105 case NVPTX::TEX_CUBE_ARRAY_F32_F32_RR: 1106 return NVPTX::TEX_CUBE_ARRAY_F32_F32_IR; 1107 case NVPTX::TEX_CUBE_ARRAY_F32_F32_RI: 1108 return NVPTX::TEX_CUBE_ARRAY_F32_F32_II; 1109 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RR: 1110 return NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_IR; 1111 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RI: 1112 return NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_II; 1113 case NVPTX::TEX_CUBE_ARRAY_S32_F32_RR: 1114 return NVPTX::TEX_CUBE_ARRAY_S32_F32_IR; 1115 case NVPTX::TEX_CUBE_ARRAY_S32_F32_RI: 1116 return NVPTX::TEX_CUBE_ARRAY_S32_F32_II; 1117 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RR: 1118 return NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_IR; 1119 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RI: 1120 return NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_II; 1121 case NVPTX::TEX_CUBE_ARRAY_U32_F32_RR: 1122 return NVPTX::TEX_CUBE_ARRAY_U32_F32_IR; 1123 case NVPTX::TEX_CUBE_ARRAY_U32_F32_RI: 1124 return NVPTX::TEX_CUBE_ARRAY_U32_F32_II; 1125 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RR: 1126 return NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_IR; 1127 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RI: 1128 return NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_II; 1129 case NVPTX::TLD4_R_2D_F32_F32_RR: 1130 return NVPTX::TLD4_R_2D_F32_F32_IR; 1131 case NVPTX::TLD4_R_2D_F32_F32_RI: 1132 return NVPTX::TLD4_R_2D_F32_F32_II; 1133 case NVPTX::TLD4_G_2D_F32_F32_RR: 1134 return NVPTX::TLD4_G_2D_F32_F32_IR; 1135 case NVPTX::TLD4_G_2D_F32_F32_RI: 1136 return NVPTX::TLD4_G_2D_F32_F32_II; 1137 case NVPTX::TLD4_B_2D_F32_F32_RR: 1138 return NVPTX::TLD4_B_2D_F32_F32_IR; 1139 case NVPTX::TLD4_B_2D_F32_F32_RI: 1140 return NVPTX::TLD4_B_2D_F32_F32_II; 1141 case NVPTX::TLD4_A_2D_F32_F32_RR: 1142 return NVPTX::TLD4_A_2D_F32_F32_IR; 1143 case NVPTX::TLD4_A_2D_F32_F32_RI: 1144 return NVPTX::TLD4_A_2D_F32_F32_II; 1145 case NVPTX::TLD4_R_2D_S32_F32_RR: 1146 return NVPTX::TLD4_R_2D_S32_F32_IR; 1147 case NVPTX::TLD4_R_2D_S32_F32_RI: 1148 return NVPTX::TLD4_R_2D_S32_F32_II; 1149 case NVPTX::TLD4_G_2D_S32_F32_RR: 1150 return NVPTX::TLD4_G_2D_S32_F32_IR; 1151 case NVPTX::TLD4_G_2D_S32_F32_RI: 1152 return NVPTX::TLD4_G_2D_S32_F32_II; 1153 case NVPTX::TLD4_B_2D_S32_F32_RR: 1154 return NVPTX::TLD4_B_2D_S32_F32_IR; 1155 case NVPTX::TLD4_B_2D_S32_F32_RI: 1156 return NVPTX::TLD4_B_2D_S32_F32_II; 1157 case NVPTX::TLD4_A_2D_S32_F32_RR: 1158 return NVPTX::TLD4_A_2D_S32_F32_IR; 1159 case NVPTX::TLD4_A_2D_S32_F32_RI: 1160 return NVPTX::TLD4_A_2D_S32_F32_II; 1161 case NVPTX::TLD4_R_2D_U32_F32_RR: 1162 return NVPTX::TLD4_R_2D_U32_F32_IR; 1163 case NVPTX::TLD4_R_2D_U32_F32_RI: 1164 return NVPTX::TLD4_R_2D_U32_F32_II; 1165 case NVPTX::TLD4_G_2D_U32_F32_RR: 1166 return NVPTX::TLD4_G_2D_U32_F32_IR; 1167 case NVPTX::TLD4_G_2D_U32_F32_RI: 1168 return NVPTX::TLD4_G_2D_U32_F32_II; 1169 case NVPTX::TLD4_B_2D_U32_F32_RR: 1170 return NVPTX::TLD4_B_2D_U32_F32_IR; 1171 case NVPTX::TLD4_B_2D_U32_F32_RI: 1172 return NVPTX::TLD4_B_2D_U32_F32_II; 1173 case NVPTX::TLD4_A_2D_U32_F32_RR: 1174 return NVPTX::TLD4_A_2D_U32_F32_IR; 1175 case NVPTX::TLD4_A_2D_U32_F32_RI: 1176 return NVPTX::TLD4_A_2D_U32_F32_II; 1177 case NVPTX::TEX_UNIFIED_1D_F32_S32_R: 1178 return NVPTX::TEX_UNIFIED_1D_F32_S32_I; 1179 case NVPTX::TEX_UNIFIED_1D_F32_F32_R: 1180 return NVPTX::TEX_UNIFIED_1D_F32_F32_I; 1181 case NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL_R: 1182 return NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL_I; 1183 case NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD_R: 1184 return NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD_I; 1185 case NVPTX::TEX_UNIFIED_1D_S32_S32_R: 1186 return NVPTX::TEX_UNIFIED_1D_S32_S32_I; 1187 case NVPTX::TEX_UNIFIED_1D_S32_F32_R: 1188 return NVPTX::TEX_UNIFIED_1D_S32_F32_I; 1189 case NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL_R: 1190 return NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL_I; 1191 case NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD_R: 1192 return NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD_I; 1193 case NVPTX::TEX_UNIFIED_1D_U32_S32_R: 1194 return NVPTX::TEX_UNIFIED_1D_U32_S32_I; 1195 case NVPTX::TEX_UNIFIED_1D_U32_F32_R: 1196 return NVPTX::TEX_UNIFIED_1D_U32_F32_I; 1197 case NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL_R: 1198 return NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL_I; 1199 case NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD_R: 1200 return NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD_I; 1201 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32_R: 1202 return NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32_I; 1203 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_R: 1204 return NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_I; 1205 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL_R: 1206 return NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL_I; 1207 case NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD_R: 1208 return NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD_I; 1209 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32_R: 1210 return NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32_I; 1211 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_R: 1212 return NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_I; 1213 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL_R: 1214 return NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL_I; 1215 case NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD_R: 1216 return NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD_I; 1217 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32_R: 1218 return NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32_I; 1219 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_R: 1220 return NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_I; 1221 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL_R: 1222 return NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL_I; 1223 case NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD_R: 1224 return NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD_I; 1225 case NVPTX::TEX_UNIFIED_2D_F32_S32_R: 1226 return NVPTX::TEX_UNIFIED_2D_F32_S32_I; 1227 case NVPTX::TEX_UNIFIED_2D_F32_F32_R: 1228 return NVPTX::TEX_UNIFIED_2D_F32_F32_I; 1229 case NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL_R: 1230 return NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL_I; 1231 case NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD_R: 1232 return NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD_I; 1233 case NVPTX::TEX_UNIFIED_2D_S32_S32_R: 1234 return NVPTX::TEX_UNIFIED_2D_S32_S32_I; 1235 case NVPTX::TEX_UNIFIED_2D_S32_F32_R: 1236 return NVPTX::TEX_UNIFIED_2D_S32_F32_I; 1237 case NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL_R: 1238 return NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL_I; 1239 case NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD_R: 1240 return NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD_I; 1241 case NVPTX::TEX_UNIFIED_2D_U32_S32_R: 1242 return NVPTX::TEX_UNIFIED_2D_U32_S32_I; 1243 case NVPTX::TEX_UNIFIED_2D_U32_F32_R: 1244 return NVPTX::TEX_UNIFIED_2D_U32_F32_I; 1245 case NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL_R: 1246 return NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL_I; 1247 case NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD_R: 1248 return NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD_I; 1249 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32_R: 1250 return NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32_I; 1251 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_R: 1252 return NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_I; 1253 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL_R: 1254 return NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL_I; 1255 case NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD_R: 1256 return NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD_I; 1257 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32_R: 1258 return NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32_I; 1259 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_R: 1260 return NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_I; 1261 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL_R: 1262 return NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL_I; 1263 case NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD_R: 1264 return NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD_I; 1265 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32_R: 1266 return NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32_I; 1267 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_R: 1268 return NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_I; 1269 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL_R: 1270 return NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL_I; 1271 case NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD_R: 1272 return NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD_I; 1273 case NVPTX::TEX_UNIFIED_3D_F32_S32_R: 1274 return NVPTX::TEX_UNIFIED_3D_F32_S32_I; 1275 case NVPTX::TEX_UNIFIED_3D_F32_F32_R: 1276 return NVPTX::TEX_UNIFIED_3D_F32_F32_I; 1277 case NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL_R: 1278 return NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL_I; 1279 case NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD_R: 1280 return NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD_I; 1281 case NVPTX::TEX_UNIFIED_3D_S32_S32_R: 1282 return NVPTX::TEX_UNIFIED_3D_S32_S32_I; 1283 case NVPTX::TEX_UNIFIED_3D_S32_F32_R: 1284 return NVPTX::TEX_UNIFIED_3D_S32_F32_I; 1285 case NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL_R: 1286 return NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL_I; 1287 case NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD_R: 1288 return NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD_I; 1289 case NVPTX::TEX_UNIFIED_3D_U32_S32_R: 1290 return NVPTX::TEX_UNIFIED_3D_U32_S32_I; 1291 case NVPTX::TEX_UNIFIED_3D_U32_F32_R: 1292 return NVPTX::TEX_UNIFIED_3D_U32_F32_I; 1293 case NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL_R: 1294 return NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL_I; 1295 case NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD_R: 1296 return NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD_I; 1297 case NVPTX::TEX_UNIFIED_CUBE_F32_F32_R: 1298 return NVPTX::TEX_UNIFIED_CUBE_F32_F32_I; 1299 case NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL_R: 1300 return NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL_I; 1301 case NVPTX::TEX_UNIFIED_CUBE_S32_F32_R: 1302 return NVPTX::TEX_UNIFIED_CUBE_S32_F32_I; 1303 case NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL_R: 1304 return NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL_I; 1305 case NVPTX::TEX_UNIFIED_CUBE_U32_F32_R: 1306 return NVPTX::TEX_UNIFIED_CUBE_U32_F32_I; 1307 case NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL_R: 1308 return NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL_I; 1309 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_R: 1310 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_I; 1311 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL_R: 1312 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL_I; 1313 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_R: 1314 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_I; 1315 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL_R: 1316 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL_I; 1317 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_R: 1318 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_I; 1319 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_R: 1320 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_I; 1321 case NVPTX::TEX_UNIFIED_CUBE_F32_F32_GRAD_R: 1322 return NVPTX::TEX_UNIFIED_CUBE_F32_F32_GRAD_I; 1323 case NVPTX::TEX_UNIFIED_CUBE_S32_F32_GRAD_R: 1324 return NVPTX::TEX_UNIFIED_CUBE_S32_F32_GRAD_I; 1325 case NVPTX::TEX_UNIFIED_CUBE_U32_F32_GRAD_R: 1326 return NVPTX::TEX_UNIFIED_CUBE_U32_F32_GRAD_I; 1327 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_R: 1328 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_I; 1329 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_R: 1330 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_I; 1331 case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_R: 1332 return NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_I; 1333 case NVPTX::TLD4_UNIFIED_R_2D_F32_F32_R: 1334 return NVPTX::TLD4_UNIFIED_R_2D_F32_F32_I; 1335 case NVPTX::TLD4_UNIFIED_G_2D_F32_F32_R: 1336 return NVPTX::TLD4_UNIFIED_G_2D_F32_F32_I; 1337 case NVPTX::TLD4_UNIFIED_B_2D_F32_F32_R: 1338 return NVPTX::TLD4_UNIFIED_B_2D_F32_F32_I; 1339 case NVPTX::TLD4_UNIFIED_A_2D_F32_F32_R: 1340 return NVPTX::TLD4_UNIFIED_A_2D_F32_F32_I; 1341 case NVPTX::TLD4_UNIFIED_R_2D_S32_F32_R: 1342 return NVPTX::TLD4_UNIFIED_R_2D_S32_F32_I; 1343 case NVPTX::TLD4_UNIFIED_G_2D_S32_F32_R: 1344 return NVPTX::TLD4_UNIFIED_G_2D_S32_F32_I; 1345 case NVPTX::TLD4_UNIFIED_B_2D_S32_F32_R: 1346 return NVPTX::TLD4_UNIFIED_B_2D_S32_F32_I; 1347 case NVPTX::TLD4_UNIFIED_A_2D_S32_F32_R: 1348 return NVPTX::TLD4_UNIFIED_A_2D_S32_F32_I; 1349 case NVPTX::TLD4_UNIFIED_R_2D_U32_F32_R: 1350 return NVPTX::TLD4_UNIFIED_R_2D_U32_F32_I; 1351 case NVPTX::TLD4_UNIFIED_G_2D_U32_F32_R: 1352 return NVPTX::TLD4_UNIFIED_G_2D_U32_F32_I; 1353 case NVPTX::TLD4_UNIFIED_B_2D_U32_F32_R: 1354 return NVPTX::TLD4_UNIFIED_B_2D_U32_F32_I; 1355 case NVPTX::TLD4_UNIFIED_A_2D_U32_F32_R: 1356 return NVPTX::TLD4_UNIFIED_A_2D_U32_F32_I; 1357 default: 1358 llvm_unreachable("Unhandled TEX opcode"); 1359 }; 1360 } 1361 1362 static unsigned samplerRegisterToIndexOpcode(unsigned RegOC) { 1363 switch (RegOC) { 1364 case NVPTX::TEX_1D_F32_S32_RR: 1365 return NVPTX::TEX_1D_F32_S32_RI; 1366 case NVPTX::TEX_1D_F32_S32_IR: 1367 return NVPTX::TEX_1D_F32_S32_II; 1368 case NVPTX::TEX_1D_F32_F32_RR: 1369 return NVPTX::TEX_1D_F32_F32_RI; 1370 case NVPTX::TEX_1D_F32_F32_IR: 1371 return NVPTX::TEX_1D_F32_F32_II; 1372 case NVPTX::TEX_1D_F32_F32_LEVEL_RR: 1373 return NVPTX::TEX_1D_F32_F32_LEVEL_RI; 1374 case NVPTX::TEX_1D_F32_F32_LEVEL_IR: 1375 return NVPTX::TEX_1D_F32_F32_LEVEL_II; 1376 case NVPTX::TEX_1D_F32_F32_GRAD_RR: 1377 return NVPTX::TEX_1D_F32_F32_GRAD_RI; 1378 case NVPTX::TEX_1D_F32_F32_GRAD_IR: 1379 return NVPTX::TEX_1D_F32_F32_GRAD_II; 1380 case NVPTX::TEX_1D_S32_S32_RR: 1381 return NVPTX::TEX_1D_S32_S32_RI; 1382 case NVPTX::TEX_1D_S32_S32_IR: 1383 return NVPTX::TEX_1D_S32_S32_II; 1384 case NVPTX::TEX_1D_S32_F32_RR: 1385 return NVPTX::TEX_1D_S32_F32_RI; 1386 case NVPTX::TEX_1D_S32_F32_IR: 1387 return NVPTX::TEX_1D_S32_F32_II; 1388 case NVPTX::TEX_1D_S32_F32_LEVEL_RR: 1389 return NVPTX::TEX_1D_S32_F32_LEVEL_RI; 1390 case NVPTX::TEX_1D_S32_F32_LEVEL_IR: 1391 return NVPTX::TEX_1D_S32_F32_LEVEL_II; 1392 case NVPTX::TEX_1D_S32_F32_GRAD_RR: 1393 return NVPTX::TEX_1D_S32_F32_GRAD_RI; 1394 case NVPTX::TEX_1D_S32_F32_GRAD_IR: 1395 return NVPTX::TEX_1D_S32_F32_GRAD_II; 1396 case NVPTX::TEX_1D_U32_S32_RR: 1397 return NVPTX::TEX_1D_U32_S32_RI; 1398 case NVPTX::TEX_1D_U32_S32_IR: 1399 return NVPTX::TEX_1D_U32_S32_II; 1400 case NVPTX::TEX_1D_U32_F32_RR: 1401 return NVPTX::TEX_1D_U32_F32_RI; 1402 case NVPTX::TEX_1D_U32_F32_IR: 1403 return NVPTX::TEX_1D_U32_F32_II; 1404 case NVPTX::TEX_1D_U32_F32_LEVEL_RR: 1405 return NVPTX::TEX_1D_U32_F32_LEVEL_RI; 1406 case NVPTX::TEX_1D_U32_F32_LEVEL_IR: 1407 return NVPTX::TEX_1D_U32_F32_LEVEL_II; 1408 case NVPTX::TEX_1D_U32_F32_GRAD_RR: 1409 return NVPTX::TEX_1D_U32_F32_GRAD_RI; 1410 case NVPTX::TEX_1D_U32_F32_GRAD_IR: 1411 return NVPTX::TEX_1D_U32_F32_GRAD_II; 1412 case NVPTX::TEX_1D_ARRAY_F32_S32_RR: 1413 return NVPTX::TEX_1D_ARRAY_F32_S32_RI; 1414 case NVPTX::TEX_1D_ARRAY_F32_S32_IR: 1415 return NVPTX::TEX_1D_ARRAY_F32_S32_II; 1416 case NVPTX::TEX_1D_ARRAY_F32_F32_RR: 1417 return NVPTX::TEX_1D_ARRAY_F32_F32_RI; 1418 case NVPTX::TEX_1D_ARRAY_F32_F32_IR: 1419 return NVPTX::TEX_1D_ARRAY_F32_F32_II; 1420 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RR: 1421 return NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RI; 1422 case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_IR: 1423 return NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_II; 1424 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RR: 1425 return NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RI; 1426 case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_IR: 1427 return NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_II; 1428 case NVPTX::TEX_1D_ARRAY_S32_S32_RR: 1429 return NVPTX::TEX_1D_ARRAY_S32_S32_RI; 1430 case NVPTX::TEX_1D_ARRAY_S32_S32_IR: 1431 return NVPTX::TEX_1D_ARRAY_S32_S32_II; 1432 case NVPTX::TEX_1D_ARRAY_S32_F32_RR: 1433 return NVPTX::TEX_1D_ARRAY_S32_F32_RI; 1434 case NVPTX::TEX_1D_ARRAY_S32_F32_IR: 1435 return NVPTX::TEX_1D_ARRAY_S32_F32_II; 1436 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RR: 1437 return NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RI; 1438 case NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_IR: 1439 return NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_II; 1440 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RR: 1441 return NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RI; 1442 case NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_IR: 1443 return NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_II; 1444 case NVPTX::TEX_1D_ARRAY_U32_S32_RR: 1445 return NVPTX::TEX_1D_ARRAY_U32_S32_RI; 1446 case NVPTX::TEX_1D_ARRAY_U32_S32_IR: 1447 return NVPTX::TEX_1D_ARRAY_U32_S32_II; 1448 case NVPTX::TEX_1D_ARRAY_U32_F32_RR: 1449 return NVPTX::TEX_1D_ARRAY_U32_F32_RI; 1450 case NVPTX::TEX_1D_ARRAY_U32_F32_IR: 1451 return NVPTX::TEX_1D_ARRAY_U32_F32_II; 1452 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RR: 1453 return NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RI; 1454 case NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_IR: 1455 return NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_II; 1456 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RR: 1457 return NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RI; 1458 case NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_IR: 1459 return NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_II; 1460 case NVPTX::TEX_2D_F32_S32_RR: 1461 return NVPTX::TEX_2D_F32_S32_RI; 1462 case NVPTX::TEX_2D_F32_S32_IR: 1463 return NVPTX::TEX_2D_F32_S32_II; 1464 case NVPTX::TEX_2D_F32_F32_RR: 1465 return NVPTX::TEX_2D_F32_F32_RI; 1466 case NVPTX::TEX_2D_F32_F32_IR: 1467 return NVPTX::TEX_2D_F32_F32_II; 1468 case NVPTX::TEX_2D_F32_F32_LEVEL_RR: 1469 return NVPTX::TEX_2D_F32_F32_LEVEL_RI; 1470 case NVPTX::TEX_2D_F32_F32_LEVEL_IR: 1471 return NVPTX::TEX_2D_F32_F32_LEVEL_II; 1472 case NVPTX::TEX_2D_F32_F32_GRAD_RR: 1473 return NVPTX::TEX_2D_F32_F32_GRAD_RI; 1474 case NVPTX::TEX_2D_F32_F32_GRAD_IR: 1475 return NVPTX::TEX_2D_F32_F32_GRAD_II; 1476 case NVPTX::TEX_2D_S32_S32_RR: 1477 return NVPTX::TEX_2D_S32_S32_RI; 1478 case NVPTX::TEX_2D_S32_S32_IR: 1479 return NVPTX::TEX_2D_S32_S32_II; 1480 case NVPTX::TEX_2D_S32_F32_RR: 1481 return NVPTX::TEX_2D_S32_F32_RI; 1482 case NVPTX::TEX_2D_S32_F32_IR: 1483 return NVPTX::TEX_2D_S32_F32_II; 1484 case NVPTX::TEX_2D_S32_F32_LEVEL_RR: 1485 return NVPTX::TEX_2D_S32_F32_LEVEL_RI; 1486 case NVPTX::TEX_2D_S32_F32_LEVEL_IR: 1487 return NVPTX::TEX_2D_S32_F32_LEVEL_II; 1488 case NVPTX::TEX_2D_S32_F32_GRAD_RR: 1489 return NVPTX::TEX_2D_S32_F32_GRAD_RI; 1490 case NVPTX::TEX_2D_S32_F32_GRAD_IR: 1491 return NVPTX::TEX_2D_S32_F32_GRAD_II; 1492 case NVPTX::TEX_2D_U32_S32_RR: 1493 return NVPTX::TEX_2D_U32_S32_RI; 1494 case NVPTX::TEX_2D_U32_S32_IR: 1495 return NVPTX::TEX_2D_U32_S32_II; 1496 case NVPTX::TEX_2D_U32_F32_RR: 1497 return NVPTX::TEX_2D_U32_F32_RI; 1498 case NVPTX::TEX_2D_U32_F32_IR: 1499 return NVPTX::TEX_2D_U32_F32_II; 1500 case NVPTX::TEX_2D_U32_F32_LEVEL_RR: 1501 return NVPTX::TEX_2D_U32_F32_LEVEL_RI; 1502 case NVPTX::TEX_2D_U32_F32_LEVEL_IR: 1503 return NVPTX::TEX_2D_U32_F32_LEVEL_II; 1504 case NVPTX::TEX_2D_U32_F32_GRAD_RR: 1505 return NVPTX::TEX_2D_U32_F32_GRAD_RI; 1506 case NVPTX::TEX_2D_U32_F32_GRAD_IR: 1507 return NVPTX::TEX_2D_U32_F32_GRAD_II; 1508 case NVPTX::TEX_2D_ARRAY_F32_S32_RR: 1509 return NVPTX::TEX_2D_ARRAY_F32_S32_RI; 1510 case NVPTX::TEX_2D_ARRAY_F32_S32_IR: 1511 return NVPTX::TEX_2D_ARRAY_F32_S32_II; 1512 case NVPTX::TEX_2D_ARRAY_F32_F32_RR: 1513 return NVPTX::TEX_2D_ARRAY_F32_F32_RI; 1514 case NVPTX::TEX_2D_ARRAY_F32_F32_IR: 1515 return NVPTX::TEX_2D_ARRAY_F32_F32_II; 1516 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RR: 1517 return NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RI; 1518 case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_IR: 1519 return NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_II; 1520 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RR: 1521 return NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RI; 1522 case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_IR: 1523 return NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_II; 1524 case NVPTX::TEX_2D_ARRAY_S32_S32_RR: 1525 return NVPTX::TEX_2D_ARRAY_S32_S32_RI; 1526 case NVPTX::TEX_2D_ARRAY_S32_S32_IR: 1527 return NVPTX::TEX_2D_ARRAY_S32_S32_II; 1528 case NVPTX::TEX_2D_ARRAY_S32_F32_RR: 1529 return NVPTX::TEX_2D_ARRAY_S32_F32_RI; 1530 case NVPTX::TEX_2D_ARRAY_S32_F32_IR: 1531 return NVPTX::TEX_2D_ARRAY_S32_F32_II; 1532 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RR: 1533 return NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RI; 1534 case NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_IR: 1535 return NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_II; 1536 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RR: 1537 return NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RI; 1538 case NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_IR: 1539 return NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_II; 1540 case NVPTX::TEX_2D_ARRAY_U32_S32_RR: 1541 return NVPTX::TEX_2D_ARRAY_U32_S32_RI; 1542 case NVPTX::TEX_2D_ARRAY_U32_S32_IR: 1543 return NVPTX::TEX_2D_ARRAY_U32_S32_II; 1544 case NVPTX::TEX_2D_ARRAY_U32_F32_RR: 1545 return NVPTX::TEX_2D_ARRAY_U32_F32_RI; 1546 case NVPTX::TEX_2D_ARRAY_U32_F32_IR: 1547 return NVPTX::TEX_2D_ARRAY_U32_F32_II; 1548 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RR: 1549 return NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RI; 1550 case NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_IR: 1551 return NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_II; 1552 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RR: 1553 return NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RI; 1554 case NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_IR: 1555 return NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_II; 1556 case NVPTX::TEX_3D_F32_S32_RR: 1557 return NVPTX::TEX_3D_F32_S32_RI; 1558 case NVPTX::TEX_3D_F32_S32_IR: 1559 return NVPTX::TEX_3D_F32_S32_II; 1560 case NVPTX::TEX_3D_F32_F32_RR: 1561 return NVPTX::TEX_3D_F32_F32_RI; 1562 case NVPTX::TEX_3D_F32_F32_IR: 1563 return NVPTX::TEX_3D_F32_F32_II; 1564 case NVPTX::TEX_3D_F32_F32_LEVEL_RR: 1565 return NVPTX::TEX_3D_F32_F32_LEVEL_RI; 1566 case NVPTX::TEX_3D_F32_F32_LEVEL_IR: 1567 return NVPTX::TEX_3D_F32_F32_LEVEL_II; 1568 case NVPTX::TEX_3D_F32_F32_GRAD_RR: 1569 return NVPTX::TEX_3D_F32_F32_GRAD_RI; 1570 case NVPTX::TEX_3D_F32_F32_GRAD_IR: 1571 return NVPTX::TEX_3D_F32_F32_GRAD_II; 1572 case NVPTX::TEX_3D_S32_S32_RR: 1573 return NVPTX::TEX_3D_S32_S32_RI; 1574 case NVPTX::TEX_3D_S32_S32_IR: 1575 return NVPTX::TEX_3D_S32_S32_II; 1576 case NVPTX::TEX_3D_S32_F32_RR: 1577 return NVPTX::TEX_3D_S32_F32_RI; 1578 case NVPTX::TEX_3D_S32_F32_IR: 1579 return NVPTX::TEX_3D_S32_F32_II; 1580 case NVPTX::TEX_3D_S32_F32_LEVEL_RR: 1581 return NVPTX::TEX_3D_S32_F32_LEVEL_RI; 1582 case NVPTX::TEX_3D_S32_F32_LEVEL_IR: 1583 return NVPTX::TEX_3D_S32_F32_LEVEL_II; 1584 case NVPTX::TEX_3D_S32_F32_GRAD_RR: 1585 return NVPTX::TEX_3D_S32_F32_GRAD_RI; 1586 case NVPTX::TEX_3D_S32_F32_GRAD_IR: 1587 return NVPTX::TEX_3D_S32_F32_GRAD_II; 1588 case NVPTX::TEX_3D_U32_S32_RR: 1589 return NVPTX::TEX_3D_U32_S32_RI; 1590 case NVPTX::TEX_3D_U32_S32_IR: 1591 return NVPTX::TEX_3D_U32_S32_II; 1592 case NVPTX::TEX_3D_U32_F32_RR: 1593 return NVPTX::TEX_3D_U32_F32_RI; 1594 case NVPTX::TEX_3D_U32_F32_IR: 1595 return NVPTX::TEX_3D_U32_F32_II; 1596 case NVPTX::TEX_3D_U32_F32_LEVEL_RR: 1597 return NVPTX::TEX_3D_U32_F32_LEVEL_RI; 1598 case NVPTX::TEX_3D_U32_F32_LEVEL_IR: 1599 return NVPTX::TEX_3D_U32_F32_LEVEL_II; 1600 case NVPTX::TEX_3D_U32_F32_GRAD_RR: 1601 return NVPTX::TEX_3D_U32_F32_GRAD_RI; 1602 case NVPTX::TEX_3D_U32_F32_GRAD_IR: 1603 return NVPTX::TEX_3D_U32_F32_GRAD_II; 1604 case NVPTX::TEX_CUBE_F32_F32_RR: 1605 return NVPTX::TEX_CUBE_F32_F32_RI; 1606 case NVPTX::TEX_CUBE_F32_F32_IR: 1607 return NVPTX::TEX_CUBE_F32_F32_II; 1608 case NVPTX::TEX_CUBE_F32_F32_LEVEL_RR: 1609 return NVPTX::TEX_CUBE_F32_F32_LEVEL_RI; 1610 case NVPTX::TEX_CUBE_F32_F32_LEVEL_IR: 1611 return NVPTX::TEX_CUBE_F32_F32_LEVEL_II; 1612 case NVPTX::TEX_CUBE_S32_F32_RR: 1613 return NVPTX::TEX_CUBE_S32_F32_RI; 1614 case NVPTX::TEX_CUBE_S32_F32_IR: 1615 return NVPTX::TEX_CUBE_S32_F32_II; 1616 case NVPTX::TEX_CUBE_S32_F32_LEVEL_RR: 1617 return NVPTX::TEX_CUBE_S32_F32_LEVEL_RI; 1618 case NVPTX::TEX_CUBE_S32_F32_LEVEL_IR: 1619 return NVPTX::TEX_CUBE_S32_F32_LEVEL_II; 1620 case NVPTX::TEX_CUBE_U32_F32_RR: 1621 return NVPTX::TEX_CUBE_U32_F32_RI; 1622 case NVPTX::TEX_CUBE_U32_F32_IR: 1623 return NVPTX::TEX_CUBE_U32_F32_II; 1624 case NVPTX::TEX_CUBE_U32_F32_LEVEL_RR: 1625 return NVPTX::TEX_CUBE_U32_F32_LEVEL_RI; 1626 case NVPTX::TEX_CUBE_U32_F32_LEVEL_IR: 1627 return NVPTX::TEX_CUBE_U32_F32_LEVEL_II; 1628 case NVPTX::TEX_CUBE_ARRAY_F32_F32_RR: 1629 return NVPTX::TEX_CUBE_ARRAY_F32_F32_RI; 1630 case NVPTX::TEX_CUBE_ARRAY_F32_F32_IR: 1631 return NVPTX::TEX_CUBE_ARRAY_F32_F32_II; 1632 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RR: 1633 return NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RI; 1634 case NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_IR: 1635 return NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_II; 1636 case NVPTX::TEX_CUBE_ARRAY_S32_F32_RR: 1637 return NVPTX::TEX_CUBE_ARRAY_S32_F32_RI; 1638 case NVPTX::TEX_CUBE_ARRAY_S32_F32_IR: 1639 return NVPTX::TEX_CUBE_ARRAY_S32_F32_II; 1640 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RR: 1641 return NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RI; 1642 case NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_IR: 1643 return NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_II; 1644 case NVPTX::TEX_CUBE_ARRAY_U32_F32_RR: 1645 return NVPTX::TEX_CUBE_ARRAY_U32_F32_RI; 1646 case NVPTX::TEX_CUBE_ARRAY_U32_F32_IR: 1647 return NVPTX::TEX_CUBE_ARRAY_U32_F32_II; 1648 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RR: 1649 return NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RI; 1650 case NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_IR: 1651 return NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_II; 1652 case NVPTX::TLD4_R_2D_F32_F32_RR: 1653 return NVPTX::TLD4_R_2D_F32_F32_RI; 1654 case NVPTX::TLD4_R_2D_F32_F32_IR: 1655 return NVPTX::TLD4_R_2D_F32_F32_II; 1656 case NVPTX::TLD4_G_2D_F32_F32_RR: 1657 return NVPTX::TLD4_G_2D_F32_F32_RI; 1658 case NVPTX::TLD4_G_2D_F32_F32_IR: 1659 return NVPTX::TLD4_G_2D_F32_F32_II; 1660 case NVPTX::TLD4_B_2D_F32_F32_RR: 1661 return NVPTX::TLD4_B_2D_F32_F32_RI; 1662 case NVPTX::TLD4_B_2D_F32_F32_IR: 1663 return NVPTX::TLD4_B_2D_F32_F32_II; 1664 case NVPTX::TLD4_A_2D_F32_F32_RR: 1665 return NVPTX::TLD4_A_2D_F32_F32_RI; 1666 case NVPTX::TLD4_A_2D_F32_F32_IR: 1667 return NVPTX::TLD4_A_2D_F32_F32_II; 1668 case NVPTX::TLD4_R_2D_S32_F32_RR: 1669 return NVPTX::TLD4_R_2D_S32_F32_RI; 1670 case NVPTX::TLD4_R_2D_S32_F32_IR: 1671 return NVPTX::TLD4_R_2D_S32_F32_II; 1672 case NVPTX::TLD4_G_2D_S32_F32_RR: 1673 return NVPTX::TLD4_G_2D_S32_F32_RI; 1674 case NVPTX::TLD4_G_2D_S32_F32_IR: 1675 return NVPTX::TLD4_G_2D_S32_F32_II; 1676 case NVPTX::TLD4_B_2D_S32_F32_RR: 1677 return NVPTX::TLD4_B_2D_S32_F32_RI; 1678 case NVPTX::TLD4_B_2D_S32_F32_IR: 1679 return NVPTX::TLD4_B_2D_S32_F32_II; 1680 case NVPTX::TLD4_A_2D_S32_F32_RR: 1681 return NVPTX::TLD4_A_2D_S32_F32_RI; 1682 case NVPTX::TLD4_A_2D_S32_F32_IR: 1683 return NVPTX::TLD4_A_2D_S32_F32_II; 1684 case NVPTX::TLD4_R_2D_U32_F32_RR: 1685 return NVPTX::TLD4_R_2D_U32_F32_RI; 1686 case NVPTX::TLD4_R_2D_U32_F32_IR: 1687 return NVPTX::TLD4_R_2D_U32_F32_II; 1688 case NVPTX::TLD4_G_2D_U32_F32_RR: 1689 return NVPTX::TLD4_G_2D_U32_F32_RI; 1690 case NVPTX::TLD4_G_2D_U32_F32_IR: 1691 return NVPTX::TLD4_G_2D_U32_F32_II; 1692 case NVPTX::TLD4_B_2D_U32_F32_RR: 1693 return NVPTX::TLD4_B_2D_U32_F32_RI; 1694 case NVPTX::TLD4_B_2D_U32_F32_IR: 1695 return NVPTX::TLD4_B_2D_U32_F32_II; 1696 case NVPTX::TLD4_A_2D_U32_F32_RR: 1697 return NVPTX::TLD4_A_2D_U32_F32_RI; 1698 case NVPTX::TLD4_A_2D_U32_F32_IR: 1699 return NVPTX::TLD4_A_2D_U32_F32_II; 1700 default: 1701 llvm_unreachable("Unhandled TEX opcode"); 1702 }; 1703 } 1704 1705 static unsigned queryRegisterToIndexOpcode(unsigned RegOC) { 1706 switch (RegOC) { 1707 case NVPTX::TXQ_CHANNEL_ORDER_R: 1708 return NVPTX::TXQ_CHANNEL_ORDER_I; 1709 case NVPTX::TXQ_CHANNEL_DATA_TYPE_R: 1710 return NVPTX::TXQ_CHANNEL_DATA_TYPE_I; 1711 case NVPTX::TXQ_WIDTH_R: 1712 return NVPTX::TXQ_WIDTH_I; 1713 case NVPTX::TXQ_HEIGHT_R: 1714 return NVPTX::TXQ_HEIGHT_I; 1715 case NVPTX::TXQ_DEPTH_R: 1716 return NVPTX::TXQ_DEPTH_I; 1717 case NVPTX::TXQ_ARRAY_SIZE_R: 1718 return NVPTX::TXQ_ARRAY_SIZE_I; 1719 case NVPTX::TXQ_NUM_SAMPLES_R: 1720 return NVPTX::TXQ_NUM_SAMPLES_I; 1721 case NVPTX::TXQ_NUM_MIPMAP_LEVELS_R: 1722 return NVPTX::TXQ_NUM_MIPMAP_LEVELS_I; 1723 case NVPTX::SUQ_CHANNEL_ORDER_R: 1724 return NVPTX::SUQ_CHANNEL_ORDER_I; 1725 case NVPTX::SUQ_CHANNEL_DATA_TYPE_R: 1726 return NVPTX::SUQ_CHANNEL_DATA_TYPE_I; 1727 case NVPTX::SUQ_WIDTH_R: 1728 return NVPTX::SUQ_WIDTH_I; 1729 case NVPTX::SUQ_HEIGHT_R: 1730 return NVPTX::SUQ_HEIGHT_I; 1731 case NVPTX::SUQ_DEPTH_R: 1732 return NVPTX::SUQ_DEPTH_I; 1733 case NVPTX::SUQ_ARRAY_SIZE_R: 1734 return NVPTX::SUQ_ARRAY_SIZE_I; 1735 default: 1736 llvm_unreachable("Unhandled TXQ/SUQ opcode"); 1737 }; 1738 } 1739 1740 bool NVPTXReplaceImageHandles::processInstr(MachineInstr &MI) { 1741 MachineFunction &MF = *MI.getParent()->getParent(); 1742 const MCInstrDesc &MCID = MI.getDesc(); 1743 const NVPTXInstrInfo *TII = MF.getSubtarget<NVPTXSubtarget>().getInstrInfo(); 1744 1745 if (MCID.TSFlags & NVPTXII::IsTexFlag) { 1746 // This is a texture fetch, so operand 4 is a texref and operand 5 is 1747 // a samplerref 1748 MachineOperand &TexHandle = MI.getOperand(4); 1749 if (replaceImageHandle(TexHandle, MF)) 1750 MI.setDesc(TII->get(texRegisterToIndexOpcode(MI.getOpcode()))); 1751 1752 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { 1753 MachineOperand &SampHandle = MI.getOperand(5); 1754 if (replaceImageHandle(SampHandle, MF)) 1755 MI.setDesc(TII->get(samplerRegisterToIndexOpcode(MI.getOpcode()))); 1756 } 1757 1758 return true; 1759 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { 1760 unsigned VecSize = 1761 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); 1762 1763 // For a surface load of vector size N, the Nth operand will be the surfref 1764 MachineOperand &SurfHandle = MI.getOperand(VecSize); 1765 1766 if (replaceImageHandle(SurfHandle, MF)) 1767 MI.setDesc(TII->get(suldRegisterToIndexOpcode(MI.getOpcode()))); 1768 1769 return true; 1770 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { 1771 // This is a surface store, so operand 0 is a surfref 1772 MachineOperand &SurfHandle = MI.getOperand(0); 1773 1774 if (replaceImageHandle(SurfHandle, MF)) 1775 MI.setDesc(TII->get(sustRegisterToIndexOpcode(MI.getOpcode()))); 1776 1777 return true; 1778 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { 1779 // This is a query, so operand 1 is a surfref/texref 1780 MachineOperand &Handle = MI.getOperand(1); 1781 1782 if (replaceImageHandle(Handle, MF)) 1783 MI.setDesc(TII->get(queryRegisterToIndexOpcode(MI.getOpcode()))); 1784 1785 return true; 1786 } 1787 1788 return false; 1789 } 1790 1791 bool NVPTXReplaceImageHandles::replaceImageHandle(MachineOperand &Op, 1792 MachineFunction &MF) { 1793 unsigned Idx; 1794 if (findIndexForHandle(Op, MF, Idx)) { 1795 Op.ChangeToImmediate(Idx); 1796 return true; 1797 } 1798 return false; 1799 } 1800 1801 bool NVPTXReplaceImageHandles:: 1802 findIndexForHandle(MachineOperand &Op, MachineFunction &MF, unsigned &Idx) { 1803 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1804 NVPTXMachineFunctionInfo *MFI = MF.getInfo<NVPTXMachineFunctionInfo>(); 1805 1806 assert(Op.isReg() && "Handle is not in a reg?"); 1807 1808 // Which instruction defines the handle? 1809 MachineInstr &TexHandleDef = *MRI.getVRegDef(Op.getReg()); 1810 1811 switch (TexHandleDef.getOpcode()) { 1812 case NVPTX::LD_i64_avar: { 1813 // The handle is a parameter value being loaded, replace with the 1814 // parameter symbol 1815 const NVPTXTargetMachine &TM = 1816 static_cast<const NVPTXTargetMachine &>(MF.getTarget()); 1817 if (TM.getDrvInterface() == NVPTX::CUDA) { 1818 // For CUDA, we preserve the param loads coming from function arguments 1819 return false; 1820 } 1821 1822 assert(TexHandleDef.getOperand(7).isSymbol() && "Load is not a symbol!"); 1823 StringRef Sym = TexHandleDef.getOperand(7).getSymbolName(); 1824 std::string ParamBaseName = std::string(MF.getName()); 1825 ParamBaseName += "_param_"; 1826 assert(Sym.starts_with(ParamBaseName) && "Invalid symbol reference"); 1827 unsigned Param = atoi(Sym.data()+ParamBaseName.size()); 1828 std::string NewSym; 1829 raw_string_ostream NewSymStr(NewSym); 1830 NewSymStr << MF.getName() << "_param_" << Param; 1831 1832 InstrsToRemove.insert(&TexHandleDef); 1833 Idx = MFI->getImageHandleSymbolIndex(NewSymStr.str()); 1834 return true; 1835 } 1836 case NVPTX::texsurf_handles: { 1837 // The handle is a global variable, replace with the global variable name 1838 assert(TexHandleDef.getOperand(1).isGlobal() && "Load is not a global!"); 1839 const GlobalValue *GV = TexHandleDef.getOperand(1).getGlobal(); 1840 assert(GV->hasName() && "Global sampler must be named!"); 1841 InstrsToRemove.insert(&TexHandleDef); 1842 Idx = MFI->getImageHandleSymbolIndex(GV->getName()); 1843 return true; 1844 } 1845 case NVPTX::nvvm_move_i64: 1846 case TargetOpcode::COPY: { 1847 bool Res = findIndexForHandle(TexHandleDef.getOperand(1), MF, Idx); 1848 if (Res) { 1849 InstrsToRemove.insert(&TexHandleDef); 1850 } 1851 return Res; 1852 } 1853 default: 1854 llvm_unreachable("Unknown instruction operating on handle"); 1855 } 1856 } 1857 1858 MachineFunctionPass *llvm::createNVPTXReplaceImageHandlesPass() { 1859 return new NVPTXReplaceImageHandles(); 1860 } 1861