1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the Mips specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSubtarget.h" 15 #include "Mips.h" 16 #include "MipsMachineFunction.h" 17 #include "MipsRegisterInfo.h" 18 #include "MipsTargetMachine.h" 19 #include "MipsCallLowering.h" 20 #include "MipsLegalizerInfo.h" 21 #include "MipsRegisterBankInfo.h" 22 #include "llvm/IR/Attributes.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "mips-subtarget" 32 33 #define GET_SUBTARGETINFO_TARGET_DESC 34 #define GET_SUBTARGETINFO_CTOR 35 #include "MipsGenSubtargetInfo.inc" 36 37 // FIXME: Maybe this should be on by default when Mips16 is specified 38 // 39 static cl::opt<bool> 40 Mixed16_32("mips-mixed-16-32", cl::init(false), 41 cl::desc("Allow for a mixture of Mips16 " 42 "and Mips32 code in a single output file"), 43 cl::Hidden); 44 45 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false), 46 cl::desc("Compile all functions that don't use " 47 "floating point as Mips 16"), 48 cl::Hidden); 49 50 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden, 51 cl::desc("Enable mips16 hard float."), 52 cl::init(false)); 53 54 static cl::opt<bool> 55 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden, 56 cl::desc("Enable mips16 constant islands."), 57 cl::init(true)); 58 59 static cl::opt<bool> 60 GPOpt("mgpopt", cl::Hidden, 61 cl::desc("Enable gp-relative addressing of mips small data items")); 62 63 bool MipsSubtarget::DspWarningPrinted = false; 64 65 bool MipsSubtarget::MSAWarningPrinted = false; 66 67 void MipsSubtarget::anchor() {} 68 69 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, 70 bool little, const MipsTargetMachine &TM, 71 unsigned StackAlignOverride) 72 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), 73 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), 74 NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), 75 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), 76 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), 77 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), 78 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), 79 HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), 80 Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), 81 HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false), 82 HasVirt(false), UseIndirectJumpsHazard(false), 83 StackAlignOverride(StackAlignOverride), 84 TM(TM), TargetTriple(TT), TSInfo(), 85 InstrInfo( 86 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), 87 FrameLowering(MipsFrameLowering::create(*this)), 88 TLInfo(MipsTargetLowering::create(TM, *this)) { 89 90 if (MipsArchVersion == MipsDefault) 91 MipsArchVersion = Mips32; 92 93 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not 94 // been tested and currently exist for the integrated assembler only. 95 if (MipsArchVersion == Mips1) 96 report_fatal_error("Code generation for MIPS-I is not implemented", false); 97 if (MipsArchVersion == Mips5) 98 report_fatal_error("Code generation for MIPS-V is not implemented", false); 99 100 // Check if Architecture and ABI are compatible. 101 assert(((!isGP64bit() && isABI_O32()) || 102 (isGP64bit() && (isABI_N32() || isABI_N64()))) && 103 "Invalid Arch & ABI pair."); 104 105 if (hasMSA() && !isFP64bit()) 106 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). " 107 "See -mattr=+fp64.", 108 false); 109 110 if (!isABI_O32() && !useOddSPReg()) 111 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); 112 113 if (IsFPXX && (isABI_N32() || isABI_N64())) 114 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); 115 116 if (hasMips64r6() && InMicroMipsMode) 117 report_fatal_error("microMIPS64R6 is not supported", false); 118 119 120 if (UseIndirectJumpsHazard) { 121 if (InMicroMipsMode) 122 report_fatal_error( 123 "cannot combine indirect jumps with hazard barriers and microMIPS"); 124 if (!hasMips32r2()) 125 report_fatal_error( 126 "indirect jumps with hazard barriers requires MIPS32R2 or later"); 127 } 128 if (hasMips32r6()) { 129 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; 130 131 assert(isFP64bit()); 132 assert(isNaN2008()); 133 if (hasDSP()) 134 report_fatal_error(ISA + " is not compatible with the DSP ASE", false); 135 } 136 137 if (NoABICalls && TM.isPositionIndependent()) 138 report_fatal_error("position-independent code requires '-mabicalls'"); 139 140 if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32()) 141 NoABICalls = true; 142 143 // Set UseSmallSection. 144 UseSmallSection = GPOpt; 145 if (!NoABICalls && GPOpt) { 146 errs() << "warning: cannot use small-data accesses for '-mabicalls'" 147 << "\n"; 148 UseSmallSection = false; 149 } 150 151 if (hasDSPR2() && !DspWarningPrinted) { 152 if (hasMips64() && !hasMips64r2()) { 153 errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or " 154 << "greater\n"; 155 DspWarningPrinted = true; 156 } else if (hasMips32() && !hasMips32r2()) { 157 errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or " 158 << "greater\n"; 159 DspWarningPrinted = true; 160 } 161 } else if (hasDSP() && !DspWarningPrinted) { 162 if (hasMips64() && !hasMips64r2()) { 163 errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or " 164 << "greater\n"; 165 DspWarningPrinted = true; 166 } else if (hasMips32() && !hasMips32r2()) { 167 errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or " 168 << "greater\n"; 169 DspWarningPrinted = true; 170 } 171 } 172 173 if (hasMSA() && !MSAWarningPrinted) { 174 if (hasMips64() && !hasMips64r5()) { 175 errs() << "warning: the 'msa' ASE requires MIPS64 revision 5 or " 176 << "greater\n"; 177 MSAWarningPrinted = true; 178 } else if (hasMips32() && !hasMips32r5()) { 179 errs() << "warning: the 'msa' ASE requires MIPS32 revision 5 or " 180 << "greater\n"; 181 MSAWarningPrinted = true; 182 } 183 } 184 185 CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering())); 186 Legalizer.reset(new MipsLegalizerInfo(*this)); 187 188 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); 189 RegBankInfo.reset(RBI); 190 InstSelector.reset(createMipsInstructionSelector( 191 *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI)); 192 } 193 194 bool MipsSubtarget::isPositionIndependent() const { 195 return TM.isPositionIndependent(); 196 } 197 198 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. 199 bool MipsSubtarget::enablePostRAScheduler() const { return true; } 200 201 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 202 CriticalPathRCs.clear(); 203 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass 204 : &Mips::GPR32RegClass); 205 } 206 207 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { 208 return CodeGenOpt::Aggressive; 209 } 210 211 MipsSubtarget & 212 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, 213 const TargetMachine &TM) { 214 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); 215 216 // Parse features string. 217 ParseSubtargetFeatures(CPUName, FS); 218 // Initialize scheduling itinerary for the specified CPU. 219 InstrItins = getInstrItineraryForCPU(CPUName); 220 221 if (InMips16Mode && !IsSoftFloat) 222 InMips16HardFloat = true; 223 224 if (StackAlignOverride) 225 stackAlignment = StackAlignOverride; 226 else if (isABI_N32() || isABI_N64()) 227 stackAlignment = 16; 228 else { 229 assert(isABI_O32() && "Unknown ABI for stack alignment!"); 230 stackAlignment = 8; 231 } 232 233 return *this; 234 } 235 236 bool MipsSubtarget::useConstantIslands() { 237 LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands 238 << "\n"); 239 return Mips16ConstantIslands; 240 } 241 242 Reloc::Model MipsSubtarget::getRelocationModel() const { 243 return TM.getRelocationModel(); 244 } 245 246 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } 247 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } 248 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } 249 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); } 250 251 const CallLowering *MipsSubtarget::getCallLowering() const { 252 return CallLoweringInfo.get(); 253 } 254 255 const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const { 256 return Legalizer.get(); 257 } 258 259 const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const { 260 return RegBankInfo.get(); 261 } 262 263 const InstructionSelector *MipsSubtarget::getInstructionSelector() const { 264 return InstSelector.get(); 265 } 266