1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the Mips specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSubtarget.h" 15 #include "Mips.h" 16 #include "MipsMachineFunction.h" 17 #include "MipsRegisterInfo.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 26 using namespace llvm; 27 28 #define DEBUG_TYPE "mips-subtarget" 29 30 #define GET_SUBTARGETINFO_TARGET_DESC 31 #define GET_SUBTARGETINFO_CTOR 32 #include "MipsGenSubtargetInfo.inc" 33 34 // FIXME: Maybe this should be on by default when Mips16 is specified 35 // 36 static cl::opt<bool> 37 Mixed16_32("mips-mixed-16-32", cl::init(false), 38 cl::desc("Allow for a mixture of Mips16 " 39 "and Mips32 code in a single output file"), 40 cl::Hidden); 41 42 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false), 43 cl::desc("Compile all functions that don't use " 44 "floating point as Mips 16"), 45 cl::Hidden); 46 47 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden, 48 cl::desc("Enable mips16 hard float."), 49 cl::init(false)); 50 51 static cl::opt<bool> 52 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden, 53 cl::desc("Enable mips16 constant islands."), 54 cl::init(true)); 55 56 static cl::opt<bool> 57 GPOpt("mgpopt", cl::Hidden, 58 cl::desc("Enable gp-relative addressing of mips small data items")); 59 60 void MipsSubtarget::anchor() {} 61 62 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, 63 bool little, const MipsTargetMachine &TM, 64 unsigned StackAlignOverride) 65 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), 66 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), 67 NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), 68 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), 69 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), 70 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), 71 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), 72 HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), 73 Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), 74 HasEVA(false), DisableMadd4(false), HasMT(false), 75 StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT), 76 TSInfo(), InstrInfo(MipsInstrInfo::create( 77 initializeSubtargetDependencies(CPU, FS, TM))), 78 FrameLowering(MipsFrameLowering::create(*this)), 79 TLInfo(MipsTargetLowering::create(TM, *this)) { 80 81 if (MipsArchVersion == MipsDefault) 82 MipsArchVersion = Mips32; 83 84 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not 85 // been tested and currently exist for the integrated assembler only. 86 if (MipsArchVersion == Mips1) 87 report_fatal_error("Code generation for MIPS-I is not implemented", false); 88 if (MipsArchVersion == Mips5) 89 report_fatal_error("Code generation for MIPS-V is not implemented", false); 90 91 // Check if Architecture and ABI are compatible. 92 assert(((!isGP64bit() && isABI_O32()) || 93 (isGP64bit() && (isABI_N32() || isABI_N64()))) && 94 "Invalid Arch & ABI pair."); 95 96 if (hasMSA() && !isFP64bit()) 97 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). " 98 "See -mattr=+fp64.", 99 false); 100 101 if (!isABI_O32() && !useOddSPReg()) 102 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); 103 104 if (IsFPXX && (isABI_N32() || isABI_N64())) 105 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); 106 107 if (hasMips32r6()) { 108 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; 109 110 assert(isFP64bit()); 111 assert(isNaN2008()); 112 if (hasDSP()) 113 report_fatal_error(ISA + " is not compatible with the DSP ASE", false); 114 } 115 116 if (NoABICalls && TM.isPositionIndependent()) 117 report_fatal_error("position-independent code requires '-mabicalls'"); 118 119 if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32()) 120 NoABICalls = true; 121 122 // Set UseSmallSection. 123 UseSmallSection = GPOpt; 124 if (!NoABICalls && GPOpt) { 125 errs() << "warning: cannot use small-data accesses for '-mabicalls'" 126 << "\n"; 127 UseSmallSection = false; 128 } 129 } 130 131 bool MipsSubtarget::isPositionIndependent() const { 132 return TM.isPositionIndependent(); 133 } 134 135 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. 136 bool MipsSubtarget::enablePostRAScheduler() const { return true; } 137 138 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 139 CriticalPathRCs.clear(); 140 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass 141 : &Mips::GPR32RegClass); 142 } 143 144 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { 145 return CodeGenOpt::Aggressive; 146 } 147 148 MipsSubtarget & 149 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, 150 const TargetMachine &TM) { 151 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); 152 153 // Parse features string. 154 ParseSubtargetFeatures(CPUName, FS); 155 // Initialize scheduling itinerary for the specified CPU. 156 InstrItins = getInstrItineraryForCPU(CPUName); 157 158 if (InMips16Mode && !IsSoftFloat) 159 InMips16HardFloat = true; 160 161 if (StackAlignOverride) 162 stackAlignment = StackAlignOverride; 163 else if (isABI_N32() || isABI_N64()) 164 stackAlignment = 16; 165 else { 166 assert(isABI_O32() && "Unknown ABI for stack alignment!"); 167 stackAlignment = 8; 168 } 169 170 return *this; 171 } 172 173 bool MipsSubtarget::useConstantIslands() { 174 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); 175 return Mips16ConstantIslands; 176 } 177 178 Reloc::Model MipsSubtarget::getRelocationModel() const { 179 return TM.getRelocationModel(); 180 } 181 182 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } 183 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } 184 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } 185 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); } 186