1 //===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsFrameLowering.h" 15 #include "MipsAnalyzeImmediate.h" 16 #include "MipsInstrInfo.h" 17 #include "MipsMachineFunction.h" 18 #include "MCTargetDesc/MipsBaseInfo.h" 19 #include "llvm/Function.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/Target/TargetData.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 29 using namespace llvm; 30 31 32 //===----------------------------------------------------------------------===// 33 // 34 // Stack Frame Processing methods 35 // +----------------------------+ 36 // 37 // The stack is allocated decrementing the stack pointer on 38 // the first instruction of a function prologue. Once decremented, 39 // all stack references are done thought a positive offset 40 // from the stack/frame pointer, so the stack is considering 41 // to grow up! Otherwise terrible hacks would have to be made 42 // to get this stack ABI compliant :) 43 // 44 // The stack frame required by the ABI (after call): 45 // Offset 46 // 47 // 0 ---------- 48 // 4 Args to pass 49 // . saved $GP (used in PIC) 50 // . Alloca allocations 51 // . Local Area 52 // . CPU "Callee Saved" Registers 53 // . saved FP 54 // . saved RA 55 // . FPU "Callee Saved" Registers 56 // StackSize ----------- 57 // 58 // Offset - offset from sp after stack allocation on function prologue 59 // 60 // The sp is the stack pointer subtracted/added from the stack size 61 // at the Prologue/Epilogue 62 // 63 // References to the previous stack (to obtain arguments) are done 64 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 65 // 66 // Examples: 67 // - reference to the actual stack frame 68 // for any local area var there is smt like : FI >= 0, StackOffset: 4 69 // sw REGX, 4(SP) 70 // 71 // - reference to previous stack frame 72 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 73 // The emitted instruction will be something like: 74 // lw REGX, 16+StackSize(SP) 75 // 76 // Since the total stack size is unknown on LowerFormalArguments, all 77 // stack references (ObjectOffset) created to reference the function 78 // arguments, are negative numbers. This way, on eliminateFrameIndex it's 79 // possible to detect those references and the offsets are adjusted to 80 // their real location. 81 // 82 //===----------------------------------------------------------------------===// 83 84 // hasFP - Return true if the specified function should have a dedicated frame 85 // pointer register. This is true if the function has variable sized allocas or 86 // if frame pointer elimination is disabled. 87 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 88 const MachineFrameInfo *MFI = MF.getFrameInfo(); 89 return MF.getTarget().Options.DisableFramePointerElim(MF) || 90 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 91 } 92 93 bool MipsFrameLowering::targetHandlesStackFrameRounding() const { 94 return true; 95 } 96 97 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 98 MachineBasicBlock &MBB = MF.front(); 99 MachineFrameInfo *MFI = MF.getFrameInfo(); 100 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 101 const MipsRegisterInfo *RegInfo = 102 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 103 const MipsInstrInfo &TII = 104 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 105 MachineBasicBlock::iterator MBBI = MBB.begin(); 106 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 107 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 108 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 109 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 110 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 111 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 112 113 // First, compute final stack size. 114 unsigned StackAlign = getStackAlignment(); 115 uint64_t StackSize = RoundUpToAlignment(MFI->getStackSize(), StackAlign); 116 117 if (MipsFI->globalBaseRegSet()) 118 StackSize += MFI->getObjectOffset(MipsFI->getGlobalRegFI()) + StackAlign; 119 else 120 StackSize += RoundUpToAlignment(MipsFI->getMaxCallFrameSize(), StackAlign); 121 122 // Update stack size 123 MFI->setStackSize(StackSize); 124 125 // No need to allocate space on the stack. 126 if (StackSize == 0 && !MFI->adjustsStack()) return; 127 128 MachineModuleInfo &MMI = MF.getMMI(); 129 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 130 MachineLocation DstML, SrcML; 131 132 // Adjust stack. 133 if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize) 134 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize); 135 else { // Expand immediate that doesn't fit in 16-bit. 136 unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT; 137 138 MF.getInfo<MipsFunctionInfo>()->setEmitNOAT(); 139 Mips::loadImmediate(-StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false, 140 0); 141 BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg); 142 } 143 144 // emit ".cfi_def_cfa_offset StackSize" 145 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 146 BuildMI(MBB, MBBI, dl, 147 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 148 DstML = MachineLocation(MachineLocation::VirtualFP); 149 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); 150 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); 151 152 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 153 154 if (CSI.size()) { 155 // Find the instruction past the last instruction that saves a callee-saved 156 // register to the stack. 157 for (unsigned i = 0; i < CSI.size(); ++i) 158 ++MBBI; 159 160 // Iterate over list of callee-saved registers and emit .cfi_offset 161 // directives. 162 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 163 BuildMI(MBB, MBBI, dl, 164 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 165 166 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 167 E = CSI.end(); I != E; ++I) { 168 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 169 unsigned Reg = I->getReg(); 170 171 // If Reg is a double precision register, emit two cfa_offsets, 172 // one for each of the paired single precision registers. 173 if (Mips::AFGR64RegClass.contains(Reg)) { 174 MachineLocation DstML0(MachineLocation::VirtualFP, Offset); 175 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); 176 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven)); 177 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd)); 178 179 if (!STI.isLittle()) 180 std::swap(SrcML0, SrcML1); 181 182 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); 183 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); 184 } else { 185 // Reg is either in CPURegs or FGR32. 186 DstML = MachineLocation(MachineLocation::VirtualFP, Offset); 187 SrcML = MachineLocation(Reg); 188 Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); 189 } 190 } 191 } 192 193 // if framepointer enabled, set it to point to the stack pointer. 194 if (hasFP(MF)) { 195 // Insert instruction "move $fp, $sp" at this location. 196 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 197 198 // emit ".cfi_def_cfa_register $fp" 199 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 200 BuildMI(MBB, MBBI, dl, 201 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 202 DstML = MachineLocation(FP); 203 SrcML = MachineLocation(MachineLocation::VirtualFP); 204 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); 205 } 206 } 207 208 void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 209 MachineBasicBlock &MBB) const { 210 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 211 MachineFrameInfo *MFI = MF.getFrameInfo(); 212 const MipsInstrInfo &TII = 213 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 214 DebugLoc dl = MBBI->getDebugLoc(); 215 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 216 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 217 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 218 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 219 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 220 221 // if framepointer enabled, restore the stack pointer. 222 if (hasFP(MF)) { 223 // Find the first instruction that restores a callee-saved register. 224 MachineBasicBlock::iterator I = MBBI; 225 226 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 227 --I; 228 229 // Insert instruction "move $sp, $fp" at this location. 230 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 231 } 232 233 // Get the number of bytes from FrameInfo 234 uint64_t StackSize = MFI->getStackSize(); 235 236 if (!StackSize) 237 return; 238 239 // Adjust stack. 240 if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize) 241 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize); 242 else { // Expand immediate that doesn't fit in 16-bit. 243 unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT; 244 245 MF.getInfo<MipsFunctionInfo>()->setEmitNOAT(); 246 Mips::loadImmediate(StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false, 247 0); 248 BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg); 249 } 250 } 251 252 void MipsFrameLowering:: 253 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 254 RegScavenger *RS) const { 255 MachineRegisterInfo &MRI = MF.getRegInfo(); 256 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 257 258 // FIXME: remove this code if register allocator can correctly mark 259 // $fp and $ra used or unused. 260 261 // Mark $fp and $ra as used or unused. 262 if (hasFP(MF)) 263 MRI.setPhysRegUsed(FP); 264 } 265 266 bool MipsFrameLowering:: 267 spillCalleeSavedRegisters(MachineBasicBlock &MBB, 268 MachineBasicBlock::iterator MI, 269 const std::vector<CalleeSavedInfo> &CSI, 270 const TargetRegisterInfo *TRI) const { 271 MachineFunction *MF = MBB.getParent(); 272 MachineBasicBlock *EntryBlock = MF->begin(); 273 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 274 275 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 276 // Add the callee-saved register as live-in. Do not add if the register is 277 // RA and return address is taken, because it has already been added in 278 // method MipsTargetLowering::LowerRETURNADDR. 279 // It's killed at the spill, unless the register is RA and return address 280 // is taken. 281 unsigned Reg = CSI[i].getReg(); 282 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) 283 && MF->getFrameInfo()->isReturnAddressTaken(); 284 if (!IsRAAndRetAddrIsTaken) 285 EntryBlock->addLiveIn(Reg); 286 287 // Insert the spill to the stack frame. 288 bool IsKill = !IsRAAndRetAddrIsTaken; 289 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 290 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, 291 CSI[i].getFrameIdx(), RC, TRI); 292 } 293 294 return true; 295 } 296