1 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsFrameLowering.h" 15 #include "MipsInstrInfo.h" 16 #include "MipsMachineFunction.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "llvm/Function.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineModuleInfo.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/Target/TargetData.h" 25 #include "llvm/Target/TargetOptions.h" 26 #include "llvm/Support/CommandLine.h" 27 28 using namespace llvm; 29 30 31 //===----------------------------------------------------------------------===// 32 // 33 // Stack Frame Processing methods 34 // +----------------------------+ 35 // 36 // The stack is allocated decrementing the stack pointer on 37 // the first instruction of a function prologue. Once decremented, 38 // all stack references are done thought a positive offset 39 // from the stack/frame pointer, so the stack is considering 40 // to grow up! Otherwise terrible hacks would have to be made 41 // to get this stack ABI compliant :) 42 // 43 // The stack frame required by the ABI (after call): 44 // Offset 45 // 46 // 0 ---------- 47 // 4 Args to pass 48 // . saved $GP (used in PIC) 49 // . Alloca allocations 50 // . Local Area 51 // . CPU "Callee Saved" Registers 52 // . saved FP 53 // . saved RA 54 // . FPU "Callee Saved" Registers 55 // StackSize ----------- 56 // 57 // Offset - offset from sp after stack allocation on function prologue 58 // 59 // The sp is the stack pointer subtracted/added from the stack size 60 // at the Prologue/Epilogue 61 // 62 // References to the previous stack (to obtain arguments) are done 63 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 64 // 65 // Examples: 66 // - reference to the actual stack frame 67 // for any local area var there is smt like : FI >= 0, StackOffset: 4 68 // sw REGX, 4(SP) 69 // 70 // - reference to previous stack frame 71 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 72 // The emitted instruction will be something like: 73 // lw REGX, 16+StackSize(SP) 74 // 75 // Since the total stack size is unknown on LowerFormalArguments, all 76 // stack references (ObjectOffset) created to reference the function 77 // arguments, are negative numbers. This way, on eliminateFrameIndex it's 78 // possible to detect those references and the offsets are adjusted to 79 // their real location. 80 // 81 //===----------------------------------------------------------------------===// 82 83 // hasFP - Return true if the specified function should have a dedicated frame 84 // pointer register. This is true if the function has variable sized allocas or 85 // if frame pointer elimination is disabled. 86 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 87 const MachineFrameInfo *MFI = MF.getFrameInfo(); 88 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() 89 || MFI->isFrameAddressTaken(); 90 } 91 92 bool MipsFrameLowering::targetHandlesStackFrameRounding() const { 93 return true; 94 } 95 96 static unsigned AlignOffset(unsigned Offset, unsigned Align) { 97 return (Offset + Align - 1) / Align * Align; 98 } 99 100 // expand pair of register and immediate if the immediate doesn't fit in the 101 // 16-bit offset field. 102 // e.g. 103 // if OrigImm = 0x10000, OrigReg = $sp: 104 // generate the following sequence of instrs: 105 // lui $at, hi(0x10000) 106 // addu $at, $sp, $at 107 // 108 // (NewReg, NewImm) = ($at, lo(Ox10000)) 109 // return true 110 static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm, 111 unsigned& NewReg, int& NewImm, 112 MachineBasicBlock& MBB, 113 MachineBasicBlock::iterator I) { 114 // OrigImm fits in the 16-bit field 115 if (OrigImm < 0x8000 && OrigImm >= -0x8000) { 116 NewReg = OrigReg; 117 NewImm = OrigImm; 118 return false; 119 } 120 121 MachineFunction* MF = MBB.getParent(); 122 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 123 DebugLoc DL = I->getDebugLoc(); 124 int ImmLo = (short)(OrigImm & 0xffff); 125 int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + 126 ((OrigImm & 0x8000) != 0); 127 128 // FIXME: change this when mips goes MC". 129 BuildMI(MBB, I, DL, TII->get(Mips::NOAT)); 130 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi); 131 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg) 132 .addReg(Mips::AT); 133 NewReg = Mips::AT; 134 NewImm = ImmLo; 135 136 return true; 137 } 138 139 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 140 MachineBasicBlock &MBB = MF.front(); 141 MachineFrameInfo *MFI = MF.getFrameInfo(); 142 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 143 const MipsRegisterInfo *RegInfo = 144 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 145 const MipsInstrInfo &TII = 146 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 147 MachineBasicBlock::iterator MBBI = MBB.begin(); 148 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 149 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); 150 unsigned NewReg = 0; 151 int NewImm = 0; 152 bool ATUsed; 153 unsigned GP = STI.isABI_N64() ? Mips::GP_64 : Mips::GP; 154 unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9; 155 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 156 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 157 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 158 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 159 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 160 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 161 162 // First, compute final stack size. 163 unsigned RegSize = STI.isGP32bit() ? 4 : 8; 164 unsigned StackAlign = getStackAlignment(); 165 unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ? 166 (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) : 167 MipsFI->getMaxCallFrameSize(); 168 unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) + 169 AlignOffset(MFI->getStackSize(), StackAlign); 170 171 // Update stack size 172 MFI->setStackSize(StackSize); 173 174 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); 175 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 176 177 // Emit instructions that set $gp using the the value of $t9. 178 // O32 uses the directive .cpload while N32/64 requires three instructions to 179 // do this. 180 // TODO: Do not emit these instructions if no instructions use $gp. 181 if (isPIC && STI.isABI_O32()) 182 BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::CPLOAD)) 183 .addReg(RegInfo->getPICCallReg()); 184 else if (STI.isABI_N64() || (isPIC && STI.isABI_N32())) { 185 // lui $28,%hi(%neg(%gp_rel(fname))) 186 // addu $28,$28,$25 187 // addiu $28,$28,%lo(%neg(%gp_rel(fname))) 188 const GlobalValue *FName = MF.getFunction(); 189 BuildMI(MBB, MBBI, dl, TII.get(LUi), GP) 190 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 191 BuildMI(MBB, MBBI, dl, TII.get(ADDu), GP).addReg(GP).addReg(T9); 192 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), GP).addReg(GP) 193 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 194 } 195 196 // No need to allocate space on the stack. 197 if (StackSize == 0 && !MFI->adjustsStack()) return; 198 199 MachineModuleInfo &MMI = MF.getMMI(); 200 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 201 MachineLocation DstML, SrcML; 202 203 // Adjust stack : addi sp, sp, (-imm) 204 ATUsed = expandRegLargeImmPair(SP, -StackSize, NewReg, NewImm, MBB, MBBI); 205 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm); 206 207 // FIXME: change this when mips goes MC". 208 if (ATUsed) 209 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 210 211 // emit ".cfi_def_cfa_offset StackSize" 212 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 213 BuildMI(MBB, MBBI, dl, 214 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 215 DstML = MachineLocation(MachineLocation::VirtualFP); 216 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); 217 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); 218 219 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 220 221 if (CSI.size()) { 222 // Find the instruction past the last instruction that saves a callee-saved 223 // register to the stack. 224 for (unsigned i = 0; i < CSI.size(); ++i) 225 ++MBBI; 226 227 // Iterate over list of callee-saved registers and emit .cfi_offset 228 // directives. 229 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 230 BuildMI(MBB, MBBI, dl, 231 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 232 233 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 234 E = CSI.end(); I != E; ++I) { 235 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 236 unsigned Reg = I->getReg(); 237 238 // If Reg is a double precision register, emit two cfa_offsets, 239 // one for each of the paired single precision registers. 240 if (Mips::AFGR64RegisterClass->contains(Reg)) { 241 const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 242 MachineLocation DstML0(MachineLocation::VirtualFP, Offset); 243 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); 244 MachineLocation SrcML0(*SubRegs); 245 MachineLocation SrcML1(*(SubRegs + 1)); 246 247 if (!STI.isLittle()) 248 std::swap(SrcML0, SrcML1); 249 250 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); 251 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); 252 } 253 else { 254 // Reg is either in CPURegs or FGR32. 255 DstML = MachineLocation(MachineLocation::VirtualFP, Offset); 256 SrcML = MachineLocation(Reg); 257 Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); 258 } 259 } 260 } 261 262 // if framepointer enabled, set it to point to the stack pointer. 263 if (hasFP(MF)) { 264 // Insert instruction "move $fp, $sp" at this location. 265 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 266 267 // emit ".cfi_def_cfa_register $fp" 268 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 269 BuildMI(MBB, MBBI, dl, 270 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 271 DstML = MachineLocation(FP); 272 SrcML = MachineLocation(MachineLocation::VirtualFP); 273 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); 274 } 275 276 // Restore GP from the saved stack location 277 if (MipsFI->needGPSaveRestore()) { 278 unsigned Offset = MFI->getObjectOffset(MipsFI->getGPFI()); 279 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset); 280 281 if (Offset >= 0x8000) { 282 BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::MACRO)); 283 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 284 } 285 } 286 } 287 288 void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 289 MachineBasicBlock &MBB) const { 290 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 291 MachineFrameInfo *MFI = MF.getFrameInfo(); 292 const MipsInstrInfo &TII = 293 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 294 DebugLoc dl = MBBI->getDebugLoc(); 295 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 296 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 297 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 298 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 299 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 300 301 // Get the number of bytes from FrameInfo 302 unsigned StackSize = MFI->getStackSize(); 303 304 unsigned NewReg = 0; 305 int NewImm = 0; 306 bool ATUsed = false; 307 308 // if framepointer enabled, restore the stack pointer. 309 if (hasFP(MF)) { 310 // Find the first instruction that restores a callee-saved register. 311 MachineBasicBlock::iterator I = MBBI; 312 313 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 314 --I; 315 316 // Insert instruction "move $sp, $fp" at this location. 317 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 318 } 319 320 // adjust stack : insert addi sp, sp, (imm) 321 if (StackSize) { 322 ATUsed = expandRegLargeImmPair(SP, StackSize, NewReg, NewImm, MBB, MBBI); 323 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm); 324 325 // FIXME: change this when mips goes MC". 326 if (ATUsed) 327 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 328 } 329 } 330 331 void MipsFrameLowering:: 332 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 333 RegScavenger *RS) const { 334 MachineRegisterInfo& MRI = MF.getRegInfo(); 335 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA; 336 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 337 338 // FIXME: remove this code if register allocator can correctly mark 339 // $fp and $ra used or unused. 340 341 // Mark $fp and $ra as used or unused. 342 if (hasFP(MF)) 343 MRI.setPhysRegUsed(FP); 344 345 // The register allocator might determine $ra is used after seeing 346 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert 347 // instructions to save/restore $ra unless there is a function call. 348 // To correct this, $ra is explicitly marked unused if there is no 349 // function call. 350 if (MF.getFrameInfo()->hasCalls()) 351 MRI.setPhysRegUsed(RA); 352 else 353 MRI.setPhysRegUnused(RA); 354 } 355