1 //===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsAnalyzeImmediate.h" 15 #include "MipsFrameLowering.h" 16 #include "MipsInstrInfo.h" 17 #include "MipsMachineFunction.h" 18 #include "MCTargetDesc/MipsBaseInfo.h" 19 #include "llvm/Function.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/Target/TargetData.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 29 using namespace llvm; 30 31 32 //===----------------------------------------------------------------------===// 33 // 34 // Stack Frame Processing methods 35 // +----------------------------+ 36 // 37 // The stack is allocated decrementing the stack pointer on 38 // the first instruction of a function prologue. Once decremented, 39 // all stack references are done thought a positive offset 40 // from the stack/frame pointer, so the stack is considering 41 // to grow up! Otherwise terrible hacks would have to be made 42 // to get this stack ABI compliant :) 43 // 44 // The stack frame required by the ABI (after call): 45 // Offset 46 // 47 // 0 ---------- 48 // 4 Args to pass 49 // . saved $GP (used in PIC) 50 // . Alloca allocations 51 // . Local Area 52 // . CPU "Callee Saved" Registers 53 // . saved FP 54 // . saved RA 55 // . FPU "Callee Saved" Registers 56 // StackSize ----------- 57 // 58 // Offset - offset from sp after stack allocation on function prologue 59 // 60 // The sp is the stack pointer subtracted/added from the stack size 61 // at the Prologue/Epilogue 62 // 63 // References to the previous stack (to obtain arguments) are done 64 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 65 // 66 // Examples: 67 // - reference to the actual stack frame 68 // for any local area var there is smt like : FI >= 0, StackOffset: 4 69 // sw REGX, 4(SP) 70 // 71 // - reference to previous stack frame 72 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 73 // The emitted instruction will be something like: 74 // lw REGX, 16+StackSize(SP) 75 // 76 // Since the total stack size is unknown on LowerFormalArguments, all 77 // stack references (ObjectOffset) created to reference the function 78 // arguments, are negative numbers. This way, on eliminateFrameIndex it's 79 // possible to detect those references and the offsets are adjusted to 80 // their real location. 81 // 82 //===----------------------------------------------------------------------===// 83 84 // hasFP - Return true if the specified function should have a dedicated frame 85 // pointer register. This is true if the function has variable sized allocas or 86 // if frame pointer elimination is disabled. 87 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 88 const MachineFrameInfo *MFI = MF.getFrameInfo(); 89 return MF.getTarget().Options.DisableFramePointerElim(MF) || 90 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 91 } 92 93 bool MipsFrameLowering::targetHandlesStackFrameRounding() const { 94 return true; 95 } 96 97 // Build an instruction sequence to load an immediate that is too large to fit 98 // in 16-bit and add the result to Reg. 99 static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64, 100 const MipsInstrInfo &TII, MachineBasicBlock& MBB, 101 MachineBasicBlock::iterator II, DebugLoc DL) { 102 unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi; 103 unsigned ADDu = IsN64 ? Mips::DADDu : Mips::ADDu; 104 unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO; 105 unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT; 106 MipsAnalyzeImmediate AnalyzeImm; 107 const MipsAnalyzeImmediate::InstSeq &Seq = 108 AnalyzeImm.Analyze(Imm, IsN64 ? 64 : 32, false /* LastInstrIsADDiu */); 109 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 110 111 // FIXME: change this when mips goes MC". 112 BuildMI(MBB, II, DL, TII.get(Mips::NOAT)); 113 114 // The first instruction can be a LUi, which is different from other 115 // instructions (ADDiu, ORI and SLL) in that it does not have a register 116 // operand. 117 if (Inst->Opc == LUi) 118 BuildMI(MBB, II, DL, TII.get(LUi), ATReg) 119 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 120 else 121 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg) 122 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 123 124 // Build the remaining instructions in Seq. 125 for (++Inst; Inst != Seq.end(); ++Inst) 126 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg) 127 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 128 129 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg); 130 BuildMI(MBB, II, DL, TII.get(Mips::ATMACRO)); 131 } 132 133 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 134 MachineBasicBlock &MBB = MF.front(); 135 MachineFrameInfo *MFI = MF.getFrameInfo(); 136 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 137 const MipsRegisterInfo *RegInfo = 138 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 139 const MipsInstrInfo &TII = 140 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 141 MachineBasicBlock::iterator MBBI = MBB.begin(); 142 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 143 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); 144 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 145 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 146 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 147 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 148 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 149 150 // First, compute final stack size. 151 unsigned RegSize = STI.isGP32bit() ? 4 : 8; 152 unsigned StackAlign = getStackAlignment(); 153 unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ? 154 (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) : 155 MipsFI->getMaxCallFrameSize(); 156 uint64_t StackSize = RoundUpToAlignment(LocalVarAreaOffset, StackAlign) + 157 RoundUpToAlignment(MFI->getStackSize(), StackAlign); 158 159 // Update stack size 160 MFI->setStackSize(StackSize); 161 162 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); 163 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 164 165 // Emit instructions that set the global base register if the target ABI is 166 // O32. 167 if (isPIC && MipsFI->globalBaseRegSet() && STI.isABI_O32()) { 168 if (MipsFI->globalBaseRegFixed()) 169 BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::CPLOAD)) 170 .addReg(RegInfo->getPICCallReg()); 171 else 172 // See MipsInstrInfo.td for explanation. 173 BuildMI(MBB, MBBI, dl, TII.get(Mips:: SETGP01), Mips::V0); 174 } 175 176 // No need to allocate space on the stack. 177 if (StackSize == 0 && !MFI->adjustsStack()) return; 178 179 MachineModuleInfo &MMI = MF.getMMI(); 180 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 181 MachineLocation DstML, SrcML; 182 183 // Adjust stack. 184 if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize) 185 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize); 186 else // Expand immediate that doesn't fit in 16-bit. 187 expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 188 189 // emit ".cfi_def_cfa_offset StackSize" 190 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 191 BuildMI(MBB, MBBI, dl, 192 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 193 DstML = MachineLocation(MachineLocation::VirtualFP); 194 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); 195 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); 196 197 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 198 199 if (CSI.size()) { 200 // Find the instruction past the last instruction that saves a callee-saved 201 // register to the stack. 202 for (unsigned i = 0; i < CSI.size(); ++i) 203 ++MBBI; 204 205 // Iterate over list of callee-saved registers and emit .cfi_offset 206 // directives. 207 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 208 BuildMI(MBB, MBBI, dl, 209 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 210 211 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 212 E = CSI.end(); I != E; ++I) { 213 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 214 unsigned Reg = I->getReg(); 215 216 // If Reg is a double precision register, emit two cfa_offsets, 217 // one for each of the paired single precision registers. 218 if (Mips::AFGR64RegisterClass->contains(Reg)) { 219 const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg); 220 MachineLocation DstML0(MachineLocation::VirtualFP, Offset); 221 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); 222 MachineLocation SrcML0(*SubRegs); 223 MachineLocation SrcML1(*(SubRegs + 1)); 224 225 if (!STI.isLittle()) 226 std::swap(SrcML0, SrcML1); 227 228 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); 229 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); 230 } 231 else { 232 // Reg is either in CPURegs or FGR32. 233 DstML = MachineLocation(MachineLocation::VirtualFP, Offset); 234 SrcML = MachineLocation(Reg); 235 Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); 236 } 237 } 238 } 239 240 // if framepointer enabled, set it to point to the stack pointer. 241 if (hasFP(MF)) { 242 // Insert instruction "move $fp, $sp" at this location. 243 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 244 245 // emit ".cfi_def_cfa_register $fp" 246 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 247 BuildMI(MBB, MBBI, dl, 248 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 249 DstML = MachineLocation(FP); 250 SrcML = MachineLocation(MachineLocation::VirtualFP); 251 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); 252 } 253 254 // Restore GP from the saved stack location 255 if (MipsFI->needGPSaveRestore()) { 256 unsigned Offset = MFI->getObjectOffset(MipsFI->getGPFI()); 257 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset); 258 259 if (Offset >= 0x8000) { 260 BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::MACRO)); 261 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 262 } 263 } 264 } 265 266 void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 267 MachineBasicBlock &MBB) const { 268 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 269 MachineFrameInfo *MFI = MF.getFrameInfo(); 270 const MipsInstrInfo &TII = 271 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 272 DebugLoc dl = MBBI->getDebugLoc(); 273 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 274 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 275 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 276 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 277 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 278 279 // if framepointer enabled, restore the stack pointer. 280 if (hasFP(MF)) { 281 // Find the first instruction that restores a callee-saved register. 282 MachineBasicBlock::iterator I = MBBI; 283 284 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 285 --I; 286 287 // Insert instruction "move $sp, $fp" at this location. 288 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 289 } 290 291 // Get the number of bytes from FrameInfo 292 uint64_t StackSize = MFI->getStackSize(); 293 294 if (!StackSize) 295 return; 296 297 // Adjust stack. 298 if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize) 299 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize); 300 else // Expand immediate that doesn't fit in 16-bit. 301 expandLargeImm(SP, StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 302 } 303 304 void MipsFrameLowering:: 305 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 306 RegScavenger *RS) const { 307 MachineRegisterInfo& MRI = MF.getRegInfo(); 308 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 309 310 // FIXME: remove this code if register allocator can correctly mark 311 // $fp and $ra used or unused. 312 313 // Mark $fp and $ra as used or unused. 314 if (hasFP(MF)) 315 MRI.setPhysRegUsed(FP); 316 317 // The register allocator might determine $ra is used after seeing 318 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert 319 // instructions to save/restore $ra unless there is a function call. 320 // To correct this, $ra is explicitly marked unused if there is no 321 // function call. 322 if (MF.getFrameInfo()->hasCalls()) 323 MRI.setPhysRegUsed(Mips::RA); 324 else { 325 MRI.setPhysRegUnused(Mips::RA); 326 MRI.setPhysRegUnused(Mips::RA_64); 327 } 328 } 329