1 //===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsFrameLowering.h" 15 #include "MipsAnalyzeImmediate.h" 16 #include "MipsInstrInfo.h" 17 #include "MipsMachineFunction.h" 18 #include "MCTargetDesc/MipsBaseInfo.h" 19 #include "llvm/Function.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/Target/TargetData.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 29 using namespace llvm; 30 31 32 //===----------------------------------------------------------------------===// 33 // 34 // Stack Frame Processing methods 35 // +----------------------------+ 36 // 37 // The stack is allocated decrementing the stack pointer on 38 // the first instruction of a function prologue. Once decremented, 39 // all stack references are done thought a positive offset 40 // from the stack/frame pointer, so the stack is considering 41 // to grow up! Otherwise terrible hacks would have to be made 42 // to get this stack ABI compliant :) 43 // 44 // The stack frame required by the ABI (after call): 45 // Offset 46 // 47 // 0 ---------- 48 // 4 Args to pass 49 // . saved $GP (used in PIC) 50 // . Alloca allocations 51 // . Local Area 52 // . CPU "Callee Saved" Registers 53 // . saved FP 54 // . saved RA 55 // . FPU "Callee Saved" Registers 56 // StackSize ----------- 57 // 58 // Offset - offset from sp after stack allocation on function prologue 59 // 60 // The sp is the stack pointer subtracted/added from the stack size 61 // at the Prologue/Epilogue 62 // 63 // References to the previous stack (to obtain arguments) are done 64 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 65 // 66 // Examples: 67 // - reference to the actual stack frame 68 // for any local area var there is smt like : FI >= 0, StackOffset: 4 69 // sw REGX, 4(SP) 70 // 71 // - reference to previous stack frame 72 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 73 // The emitted instruction will be something like: 74 // lw REGX, 16+StackSize(SP) 75 // 76 // Since the total stack size is unknown on LowerFormalArguments, all 77 // stack references (ObjectOffset) created to reference the function 78 // arguments, are negative numbers. This way, on eliminateFrameIndex it's 79 // possible to detect those references and the offsets are adjusted to 80 // their real location. 81 // 82 //===----------------------------------------------------------------------===// 83 84 // hasFP - Return true if the specified function should have a dedicated frame 85 // pointer register. This is true if the function has variable sized allocas or 86 // if frame pointer elimination is disabled. 87 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 88 const MachineFrameInfo *MFI = MF.getFrameInfo(); 89 return MF.getTarget().Options.DisableFramePointerElim(MF) || 90 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 91 } 92 93 bool MipsFrameLowering::targetHandlesStackFrameRounding() const { 94 return true; 95 } 96 97 // Build an instruction sequence to load an immediate that is too large to fit 98 // in 16-bit and add the result to Reg. 99 static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64, 100 const MipsInstrInfo &TII, MachineBasicBlock& MBB, 101 MachineBasicBlock::iterator II, DebugLoc DL) { 102 unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi; 103 unsigned ADDu = IsN64 ? Mips::DADDu : Mips::ADDu; 104 unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO; 105 unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT; 106 MipsAnalyzeImmediate AnalyzeImm; 107 const MipsAnalyzeImmediate::InstSeq &Seq = 108 AnalyzeImm.Analyze(Imm, IsN64 ? 64 : 32, false /* LastInstrIsADDiu */); 109 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 110 111 // The first instruction can be a LUi, which is different from other 112 // instructions (ADDiu, ORI and SLL) in that it does not have a register 113 // operand. 114 if (Inst->Opc == LUi) 115 BuildMI(MBB, II, DL, TII.get(LUi), ATReg) 116 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 117 else 118 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg) 119 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 120 121 // Build the remaining instructions in Seq. 122 for (++Inst; Inst != Seq.end(); ++Inst) 123 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg) 124 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 125 126 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg); 127 } 128 129 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 130 MachineBasicBlock &MBB = MF.front(); 131 MachineFrameInfo *MFI = MF.getFrameInfo(); 132 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 133 const MipsRegisterInfo *RegInfo = 134 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 135 const MipsInstrInfo &TII = 136 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 137 MachineBasicBlock::iterator MBBI = MBB.begin(); 138 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 139 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); 140 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 141 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 142 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 143 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 144 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 145 146 // First, compute final stack size. 147 unsigned RegSize = STI.isGP32bit() ? 4 : 8; 148 unsigned StackAlign = getStackAlignment(); 149 unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ? 150 (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) : 151 MipsFI->getMaxCallFrameSize(); 152 uint64_t StackSize = RoundUpToAlignment(LocalVarAreaOffset, StackAlign) + 153 RoundUpToAlignment(MFI->getStackSize(), StackAlign); 154 155 // Update stack size 156 MFI->setStackSize(StackSize); 157 158 // Emit instructions that set the global base register if the target ABI is 159 // O32. 160 if (isPIC && MipsFI->globalBaseRegSet() && STI.isABI_O32() && 161 !MipsFI->globalBaseRegFixed()) { 162 // See MipsInstrInfo.td for explanation. 163 MachineBasicBlock *NewEntry = MF.CreateMachineBasicBlock(); 164 MF.insert(&MBB, NewEntry); 165 NewEntry->addSuccessor(&MBB); 166 167 // Copy live in registers. 168 for (MachineBasicBlock::livein_iterator R = MBB.livein_begin(); 169 R != MBB.livein_end(); ++R) 170 NewEntry->addLiveIn(*R); 171 172 BuildMI(*NewEntry, NewEntry->begin(), dl, TII.get(Mips:: SETGP01), 173 Mips::V0); 174 } 175 176 // No need to allocate space on the stack. 177 if (StackSize == 0 && !MFI->adjustsStack()) return; 178 179 MachineModuleInfo &MMI = MF.getMMI(); 180 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 181 MachineLocation DstML, SrcML; 182 183 // Adjust stack. 184 if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize) 185 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize); 186 else { // Expand immediate that doesn't fit in 16-bit. 187 MipsFI->setEmitNOAT(); 188 expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 189 } 190 191 // emit ".cfi_def_cfa_offset StackSize" 192 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 193 BuildMI(MBB, MBBI, dl, 194 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 195 DstML = MachineLocation(MachineLocation::VirtualFP); 196 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); 197 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); 198 199 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 200 201 if (CSI.size()) { 202 // Find the instruction past the last instruction that saves a callee-saved 203 // register to the stack. 204 for (unsigned i = 0; i < CSI.size(); ++i) 205 ++MBBI; 206 207 // Iterate over list of callee-saved registers and emit .cfi_offset 208 // directives. 209 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 210 BuildMI(MBB, MBBI, dl, 211 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 212 213 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 214 E = CSI.end(); I != E; ++I) { 215 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 216 unsigned Reg = I->getReg(); 217 218 // If Reg is a double precision register, emit two cfa_offsets, 219 // one for each of the paired single precision registers. 220 if (Mips::AFGR64RegisterClass->contains(Reg)) { 221 const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg); 222 MachineLocation DstML0(MachineLocation::VirtualFP, Offset); 223 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); 224 MachineLocation SrcML0(*SubRegs); 225 MachineLocation SrcML1(*(SubRegs + 1)); 226 227 if (!STI.isLittle()) 228 std::swap(SrcML0, SrcML1); 229 230 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); 231 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); 232 } 233 else { 234 // Reg is either in CPURegs or FGR32. 235 DstML = MachineLocation(MachineLocation::VirtualFP, Offset); 236 SrcML = MachineLocation(Reg); 237 Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); 238 } 239 } 240 } 241 242 // if framepointer enabled, set it to point to the stack pointer. 243 if (hasFP(MF)) { 244 // Insert instruction "move $fp, $sp" at this location. 245 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 246 247 // emit ".cfi_def_cfa_register $fp" 248 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 249 BuildMI(MBB, MBBI, dl, 250 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 251 DstML = MachineLocation(FP); 252 SrcML = MachineLocation(MachineLocation::VirtualFP); 253 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); 254 } 255 256 // Restore GP from the saved stack location 257 if (MipsFI->needGPSaveRestore()) { 258 unsigned Offset = MFI->getObjectOffset(MipsFI->getGPFI()); 259 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset) 260 .addReg(Mips::GP); 261 } 262 } 263 264 void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 265 MachineBasicBlock &MBB) const { 266 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 267 MachineFrameInfo *MFI = MF.getFrameInfo(); 268 const MipsInstrInfo &TII = 269 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 270 DebugLoc dl = MBBI->getDebugLoc(); 271 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 272 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 273 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 274 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 275 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 276 277 // if framepointer enabled, restore the stack pointer. 278 if (hasFP(MF)) { 279 // Find the first instruction that restores a callee-saved register. 280 MachineBasicBlock::iterator I = MBBI; 281 282 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 283 --I; 284 285 // Insert instruction "move $sp, $fp" at this location. 286 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 287 } 288 289 // Get the number of bytes from FrameInfo 290 uint64_t StackSize = MFI->getStackSize(); 291 292 if (!StackSize) 293 return; 294 295 // Adjust stack. 296 if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize) 297 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize); 298 else // Expand immediate that doesn't fit in 16-bit. 299 expandLargeImm(SP, StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 300 } 301 302 void MipsFrameLowering:: 303 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 304 RegScavenger *RS) const { 305 MachineRegisterInfo& MRI = MF.getRegInfo(); 306 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 307 308 // FIXME: remove this code if register allocator can correctly mark 309 // $fp and $ra used or unused. 310 311 // Mark $fp and $ra as used or unused. 312 if (hasFP(MF)) 313 MRI.setPhysRegUsed(FP); 314 315 // The register allocator might determine $ra is used after seeing 316 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert 317 // instructions to save/restore $ra unless there is a function call. 318 // To correct this, $ra is explicitly marked unused if there is no 319 // function call. 320 if (MF.getFrameInfo()->hasCalls()) 321 MRI.setPhysRegUsed(Mips::RA); 322 else { 323 MRI.setPhysRegUnused(Mips::RA); 324 MRI.setPhysRegUnused(Mips::RA_64); 325 } 326 } 327