1 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsFrameLowering.h" 15 #include "MipsInstrInfo.h" 16 #include "MipsMachineFunction.h" 17 #include "llvm/Function.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineModuleInfo.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/Target/TargetData.h" 24 #include "llvm/Target/TargetOptions.h" 25 #include "llvm/Support/CommandLine.h" 26 27 using namespace llvm; 28 29 30 //===----------------------------------------------------------------------===// 31 // 32 // Stack Frame Processing methods 33 // +----------------------------+ 34 // 35 // The stack is allocated decrementing the stack pointer on 36 // the first instruction of a function prologue. Once decremented, 37 // all stack references are done thought a positive offset 38 // from the stack/frame pointer, so the stack is considering 39 // to grow up! Otherwise terrible hacks would have to be made 40 // to get this stack ABI compliant :) 41 // 42 // The stack frame required by the ABI (after call): 43 // Offset 44 // 45 // 0 ---------- 46 // 4 Args to pass 47 // . saved $GP (used in PIC) 48 // . Alloca allocations 49 // . Local Area 50 // . CPU "Callee Saved" Registers 51 // . saved FP 52 // . saved RA 53 // . FPU "Callee Saved" Registers 54 // StackSize ----------- 55 // 56 // Offset - offset from sp after stack allocation on function prologue 57 // 58 // The sp is the stack pointer subtracted/added from the stack size 59 // at the Prologue/Epilogue 60 // 61 // References to the previous stack (to obtain arguments) are done 62 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 63 // 64 // Examples: 65 // - reference to the actual stack frame 66 // for any local area var there is smt like : FI >= 0, StackOffset: 4 67 // sw REGX, 4(SP) 68 // 69 // - reference to previous stack frame 70 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 71 // The emitted instruction will be something like: 72 // lw REGX, 16+StackSize(SP) 73 // 74 // Since the total stack size is unknown on LowerFormalArguments, all 75 // stack references (ObjectOffset) created to reference the function 76 // arguments, are negative numbers. This way, on eliminateFrameIndex it's 77 // possible to detect those references and the offsets are adjusted to 78 // their real location. 79 // 80 //===----------------------------------------------------------------------===// 81 82 // hasFP - Return true if the specified function should have a dedicated frame 83 // pointer register. This is true if the function has variable sized allocas or 84 // if frame pointer elimination is disabled. 85 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 86 const MachineFrameInfo *MFI = MF.getFrameInfo(); 87 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); 88 } 89 90 void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const { 91 MachineFrameInfo *MFI = MF.getFrameInfo(); 92 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 93 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 94 unsigned StackAlign = getStackAlignment(); 95 unsigned RegSize = STI.isGP32bit() ? 4 : 8; 96 bool HasGP = MipsFI->needGPSaveRestore(); 97 98 // Min and Max CSI FrameIndex. 99 int MinCSFI = -1, MaxCSFI = -1; 100 101 // See the description at MipsMachineFunction.h 102 int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1; 103 104 // Replace the dummy '0' SPOffset by the negative offsets, as explained on 105 // LowerFormalArguments. Leaving '0' for while is necessary to avoid the 106 // approach done by calculateFrameObjectOffsets to the stack frame. 107 MipsFI->adjustLoadArgsFI(MFI); 108 MipsFI->adjustStoreVarArgsFI(MFI); 109 110 // It happens that the default stack frame allocation order does not directly 111 // map to the convention used for mips. So we must fix it. We move the callee 112 // save register slots after the local variables area, as described in the 113 // stack frame above. 114 unsigned CalleeSavedAreaSize = 0; 115 if (!CSI.empty()) { 116 MinCSFI = CSI[0].getFrameIdx(); 117 MaxCSFI = CSI[CSI.size()-1].getFrameIdx(); 118 } 119 for (unsigned i = 0, e = CSI.size(); i != e; ++i) 120 CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx()); 121 122 unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize) 123 : (STI.isABI_O32() ? 16 : 0); 124 125 // Adjust local variables. They should come on the stack right 126 // after the arguments. 127 int LastOffsetFI = -1; 128 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { 129 if (i >= MinCSFI && i <= MaxCSFI) 130 continue; 131 if (MFI->isDeadObjectIndex(i)) 132 continue; 133 unsigned Offset = 134 StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize; 135 if (LastOffsetFI == -1) 136 LastOffsetFI = i; 137 if (Offset > MFI->getObjectOffset(LastOffsetFI)) 138 LastOffsetFI = i; 139 MFI->setObjectOffset(i, Offset); 140 } 141 142 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must 143 // be saved in this CPU Area. This whole area must be aligned to the 144 // default Stack Alignment requirements. 145 if (LastOffsetFI >= 0) 146 StackOffset = MFI->getObjectOffset(LastOffsetFI)+ 147 MFI->getObjectSize(LastOffsetFI); 148 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); 149 150 for (unsigned i = 0, e = CSI.size(); i != e ; ++i) { 151 unsigned Reg = CSI[i].getReg(); 152 if (!Mips::CPURegsRegisterClass->contains(Reg)) 153 break; 154 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset); 155 TopCPUSavedRegOff = StackOffset; 156 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx()); 157 } 158 159 // Stack locations for FP and RA. If only one of them is used, 160 // the space must be allocated for both, otherwise no space at all. 161 if (hasFP(MF) || MFI->adjustsStack()) { 162 // FP stack location 163 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true), 164 StackOffset); 165 MipsFI->setFPStackOffset(StackOffset); 166 TopCPUSavedRegOff = StackOffset; 167 StackOffset += RegSize; 168 169 // SP stack location 170 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true), 171 StackOffset); 172 MipsFI->setRAStackOffset(StackOffset); 173 StackOffset += RegSize; 174 175 if (MFI->adjustsStack()) 176 TopCPUSavedRegOff += RegSize; 177 } 178 179 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); 180 181 // Adjust FPU Callee Saved Registers Area. This Area must be 182 // aligned to the default Stack Alignment requirements. 183 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 184 unsigned Reg = CSI[i].getReg(); 185 if (Mips::CPURegsRegisterClass->contains(Reg)) 186 continue; 187 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset); 188 TopFPUSavedRegOff = StackOffset; 189 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx()); 190 } 191 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); 192 193 // Update frame info 194 MFI->setStackSize(StackOffset); 195 196 // Recalculate the final tops offset. The final values must be '0' 197 // if there isn't a callee saved register for CPU or FPU, otherwise 198 // a negative offset is needed. 199 if (TopCPUSavedRegOff >= 0) 200 MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset); 201 202 if (TopFPUSavedRegOff >= 0) 203 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset); 204 } 205 206 207 // expand pair of register and immediate if the immediate doesn't fit in the 16-bit 208 // offset field. 209 // e.g. 210 // if OrigImm = 0x10000, OrigReg = $sp: 211 // generate the following sequence of instrs: 212 // lui $at, hi(0x10000) 213 // addu $at, $sp, $at 214 // 215 // (NewReg, NewImm) = ($at, lo(Ox10000)) 216 // return true 217 static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm, 218 unsigned& NewReg, int& NewImm, 219 MachineBasicBlock& MBB, MachineBasicBlock::iterator I) { 220 // OrigImm fits in the 16-bit field 221 if (OrigImm < 0x8000 && OrigImm >= -0x8000) { 222 NewReg = OrigReg; 223 NewImm = OrigImm; 224 return false; 225 } 226 227 MachineFunction* MF = MBB.getParent(); 228 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 229 DebugLoc DL = I->getDebugLoc(); 230 int ImmLo = OrigImm & 0xffff; 231 int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + ((OrigImm & 0x8000) != 0); 232 233 // FIXME: change this when mips goes MC". 234 BuildMI(MBB, I, DL, TII->get(Mips::NOAT)); 235 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi); 236 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg).addReg(Mips::AT); 237 NewReg = Mips::AT; 238 NewImm = ImmLo; 239 240 return true; 241 } 242 243 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 244 MachineBasicBlock &MBB = MF.front(); 245 MachineFrameInfo *MFI = MF.getFrameInfo(); 246 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 247 const MipsRegisterInfo *RegInfo = 248 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 249 const MipsInstrInfo &TII = 250 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 251 MachineBasicBlock::iterator MBBI = MBB.begin(); 252 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 253 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); 254 unsigned NewReg = 0; 255 int NewImm = 0; 256 bool ATUsed; 257 258 // Get the right frame order for Mips. 259 adjustMipsStackFrame(MF); 260 261 // Get the number of bytes to allocate from the FrameInfo. 262 unsigned StackSize = MFI->getStackSize(); 263 264 // No need to allocate space on the stack. 265 if (StackSize == 0 && !MFI->adjustsStack()) return; 266 267 int FPOffset = MipsFI->getFPStackOffset(); 268 int RAOffset = MipsFI->getRAStackOffset(); 269 270 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); 271 272 // TODO: check need from GP here. 273 if (isPIC && STI.isABI_O32()) 274 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)) 275 .addReg(RegInfo->getPICCallReg()); 276 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 277 278 // Adjust stack : addi sp, sp, (-imm) 279 ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB, 280 MBBI); 281 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) 282 .addReg(NewReg).addImm(NewImm); 283 284 // FIXME: change this when mips goes MC". 285 if (ATUsed) 286 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 287 288 // Save the return address only if the function isn't a leaf one. 289 // sw $ra, stack_loc($sp) 290 if (MFI->adjustsStack()) { 291 ATUsed = expandRegLargeImmPair(Mips::SP, RAOffset, NewReg, NewImm, MBB, 292 MBBI); 293 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) 294 .addReg(Mips::RA).addImm(NewImm).addReg(NewReg); 295 296 // FIXME: change this when mips goes MC". 297 if (ATUsed) 298 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 299 } 300 301 // if framepointer enabled, save it and set it 302 // to point to the stack pointer 303 if (hasFP(MF)) { 304 // sw $fp,stack_loc($sp) 305 ATUsed = expandRegLargeImmPair(Mips::SP, FPOffset, NewReg, NewImm, MBB, 306 MBBI); 307 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) 308 .addReg(Mips::FP).addImm(NewImm).addReg(NewReg); 309 310 // FIXME: change this when mips goes MC". 311 if (ATUsed) 312 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 313 314 // move $fp, $sp 315 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP) 316 .addReg(Mips::SP).addReg(Mips::ZERO); 317 } 318 319 // Restore GP from the saved stack location 320 if (MipsFI->needGPSaveRestore()) 321 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)) 322 .addImm(MipsFI->getGPStackOffset()); 323 } 324 325 void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 326 MachineBasicBlock &MBB) const { 327 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 328 MachineFrameInfo *MFI = MF.getFrameInfo(); 329 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 330 const MipsInstrInfo &TII = 331 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 332 DebugLoc dl = MBBI->getDebugLoc(); 333 334 // Get the number of bytes from FrameInfo 335 int NumBytes = (int) MFI->getStackSize(); 336 337 // Get the FI's where RA and FP are saved. 338 int FPOffset = MipsFI->getFPStackOffset(); 339 int RAOffset = MipsFI->getRAStackOffset(); 340 341 unsigned NewReg = 0; 342 int NewImm = 0; 343 bool ATUsed = false; 344 345 // if framepointer enabled, restore it and restore the 346 // stack pointer 347 if (hasFP(MF)) { 348 // move $sp, $fp 349 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP) 350 .addReg(Mips::FP).addReg(Mips::ZERO); 351 352 // lw $fp,stack_loc($sp) 353 ATUsed = expandRegLargeImmPair(Mips::SP, FPOffset, NewReg, NewImm, MBB, 354 MBBI); 355 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP) 356 .addImm(NewImm).addReg(NewReg); 357 358 // FIXME: change this when mips goes MC". 359 if (ATUsed) 360 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 361 } 362 363 // Restore the return address only if the function isn't a leaf one. 364 // lw $ra, stack_loc($sp) 365 if (MFI->adjustsStack()) { 366 ATUsed = expandRegLargeImmPair(Mips::SP, RAOffset, NewReg, NewImm, MBB, 367 MBBI); 368 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA) 369 .addImm(NewImm).addReg(NewReg); 370 371 // FIXME: change this when mips goes MC". 372 if (ATUsed) 373 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 374 } 375 376 // adjust stack : insert addi sp, sp, (imm) 377 if (NumBytes) { 378 ATUsed = expandRegLargeImmPair(Mips::SP, NumBytes, NewReg, NewImm, MBB, 379 MBBI); 380 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) 381 .addReg(NewReg).addImm(NewImm); 382 383 // FIXME: change this when mips goes MC". 384 if (ATUsed) 385 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); 386 } 387 } 388 389 void MipsFrameLowering:: 390 processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 391 const MipsRegisterInfo *RegInfo = 392 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 393 RegInfo->processFunctionBeforeFrameFinalized(MF); 394 } 395