1 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsAnalyzeImmediate.h" 15 #include "MipsFrameLowering.h" 16 #include "MipsInstrInfo.h" 17 #include "MipsMachineFunction.h" 18 #include "MCTargetDesc/MipsBaseInfo.h" 19 #include "llvm/Function.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/Target/TargetData.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 29 using namespace llvm; 30 31 32 //===----------------------------------------------------------------------===// 33 // 34 // Stack Frame Processing methods 35 // +----------------------------+ 36 // 37 // The stack is allocated decrementing the stack pointer on 38 // the first instruction of a function prologue. Once decremented, 39 // all stack references are done thought a positive offset 40 // from the stack/frame pointer, so the stack is considering 41 // to grow up! Otherwise terrible hacks would have to be made 42 // to get this stack ABI compliant :) 43 // 44 // The stack frame required by the ABI (after call): 45 // Offset 46 // 47 // 0 ---------- 48 // 4 Args to pass 49 // . saved $GP (used in PIC) 50 // . Alloca allocations 51 // . Local Area 52 // . CPU "Callee Saved" Registers 53 // . saved FP 54 // . saved RA 55 // . FPU "Callee Saved" Registers 56 // StackSize ----------- 57 // 58 // Offset - offset from sp after stack allocation on function prologue 59 // 60 // The sp is the stack pointer subtracted/added from the stack size 61 // at the Prologue/Epilogue 62 // 63 // References to the previous stack (to obtain arguments) are done 64 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 65 // 66 // Examples: 67 // - reference to the actual stack frame 68 // for any local area var there is smt like : FI >= 0, StackOffset: 4 69 // sw REGX, 4(SP) 70 // 71 // - reference to previous stack frame 72 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 73 // The emitted instruction will be something like: 74 // lw REGX, 16+StackSize(SP) 75 // 76 // Since the total stack size is unknown on LowerFormalArguments, all 77 // stack references (ObjectOffset) created to reference the function 78 // arguments, are negative numbers. This way, on eliminateFrameIndex it's 79 // possible to detect those references and the offsets are adjusted to 80 // their real location. 81 // 82 //===----------------------------------------------------------------------===// 83 84 // hasFP - Return true if the specified function should have a dedicated frame 85 // pointer register. This is true if the function has variable sized allocas or 86 // if frame pointer elimination is disabled. 87 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 88 const MachineFrameInfo *MFI = MF.getFrameInfo(); 89 return MF.getTarget().Options.DisableFramePointerElim(MF) || 90 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 91 } 92 93 bool MipsFrameLowering::targetHandlesStackFrameRounding() const { 94 return true; 95 } 96 97 // Build an instruction sequence to load an immediate that is too large to fit 98 // in 16-bit and add the result to Reg. 99 static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64, 100 const MipsInstrInfo &TII, MachineBasicBlock& MBB, 101 MachineBasicBlock::iterator II, DebugLoc DL) { 102 unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi; 103 unsigned ADDu = IsN64 ? Mips::DADDu : Mips::ADDu; 104 unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO; 105 unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT; 106 MipsAnalyzeImmediate AnalyzeImm; 107 const MipsAnalyzeImmediate::InstSeq &Seq = 108 AnalyzeImm.Analyze(Imm, IsN64 ? 64 : 32, false /* LastInstrIsADDiu */); 109 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 110 111 // FIXME: change this when mips goes MC". 112 BuildMI(MBB, II, DL, TII.get(Mips::NOAT)); 113 114 // The first instruction can be a LUi, which is different from other 115 // instructions (ADDiu, ORI and SLL) in that it does not have a register 116 // operand. 117 if (Inst->Opc == LUi) 118 BuildMI(MBB, II, DL, TII.get(LUi), ATReg) 119 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 120 else 121 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg) 122 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 123 124 // Build the remaining instructions in Seq. 125 for (++Inst; Inst != Seq.end(); ++Inst) 126 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg) 127 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 128 129 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg); 130 BuildMI(MBB, II, DL, TII.get(Mips::ATMACRO)); 131 } 132 133 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 134 MachineBasicBlock &MBB = MF.front(); 135 MachineFrameInfo *MFI = MF.getFrameInfo(); 136 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 137 const MipsRegisterInfo *RegInfo = 138 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 139 MachineRegisterInfo& MRI = MF.getRegInfo(); 140 const MipsInstrInfo &TII = 141 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 142 MachineBasicBlock::iterator MBBI = MBB.begin(); 143 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 144 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); 145 unsigned GP = STI.isABI_N64() ? Mips::GP_64 : Mips::GP; 146 unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9; 147 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 148 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 149 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 150 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 151 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 152 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 153 154 // First, compute final stack size. 155 unsigned RegSize = STI.isGP32bit() ? 4 : 8; 156 unsigned StackAlign = getStackAlignment(); 157 unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ? 158 (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) : 159 MipsFI->getMaxCallFrameSize(); 160 uint64_t StackSize = RoundUpToAlignment(LocalVarAreaOffset, StackAlign) + 161 RoundUpToAlignment(MFI->getStackSize(), StackAlign); 162 163 // Update stack size 164 MFI->setStackSize(StackSize); 165 166 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); 167 168 // Emit instructions that set $gp using the the value of $t9. 169 // O32 uses the directive .cpload while N32/64 requires three instructions to 170 // do this. 171 // TODO: Do not emit these instructions if no instructions use $gp. 172 if (isPIC && STI.isABI_O32()) 173 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)) 174 .addReg(RegInfo->getPICCallReg()); 175 176 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 177 178 // No need to allocate space on the stack. 179 if (StackSize == 0 && !MFI->adjustsStack()) return; 180 181 MachineModuleInfo &MMI = MF.getMMI(); 182 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 183 MachineLocation DstML, SrcML; 184 185 // Adjust stack. 186 if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize) 187 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize); 188 else // Expand immediate that doesn't fit in 16-bit. 189 expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 190 191 // emit ".cfi_def_cfa_offset StackSize" 192 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 193 BuildMI(MBB, MBBI, dl, 194 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 195 DstML = MachineLocation(MachineLocation::VirtualFP); 196 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); 197 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); 198 199 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 200 201 if (CSI.size()) { 202 // Find the instruction past the last instruction that saves a callee-saved 203 // register to the stack. 204 for (unsigned i = 0; i < CSI.size(); ++i) 205 ++MBBI; 206 207 // Iterate over list of callee-saved registers and emit .cfi_offset 208 // directives. 209 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 210 BuildMI(MBB, MBBI, dl, 211 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 212 213 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 214 E = CSI.end(); I != E; ++I) { 215 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 216 unsigned Reg = I->getReg(); 217 218 // If Reg is a double precision register, emit two cfa_offsets, 219 // one for each of the paired single precision registers. 220 if (Mips::AFGR64RegisterClass->contains(Reg)) { 221 const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 222 MachineLocation DstML0(MachineLocation::VirtualFP, Offset); 223 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); 224 MachineLocation SrcML0(*SubRegs); 225 MachineLocation SrcML1(*(SubRegs + 1)); 226 227 if (!STI.isLittle()) 228 std::swap(SrcML0, SrcML1); 229 230 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); 231 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); 232 } 233 else { 234 // Reg is either in CPURegs or FGR32. 235 DstML = MachineLocation(MachineLocation::VirtualFP, Offset); 236 SrcML = MachineLocation(Reg); 237 Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); 238 } 239 } 240 } 241 242 if ((STI.isABI_N64() || (isPIC && STI.isABI_N32())) && 243 MRI.isPhysRegUsed(GP)) { 244 // lui $28,%hi(%neg(%gp_rel(fname))) 245 // addu $28,$28,$25 246 // addiu $28,$28,%lo(%neg(%gp_rel(fname))) 247 MachineBasicBlock::iterator InsPos = llvm::prior(MBBI); 248 const GlobalValue *FName = MF.getFunction(); 249 BuildMI(MBB, MBBI, dl, TII.get(LUi), GP) 250 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 251 BuildMI(MBB, MBBI, dl, TII.get(ADDu), GP).addReg(GP).addReg(T9); 252 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), GP).addReg(GP) 253 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 254 MBBI = ++InsPos; 255 } 256 257 // if framepointer enabled, set it to point to the stack pointer. 258 if (hasFP(MF)) { 259 // Insert instruction "move $fp, $sp" at this location. 260 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 261 262 // emit ".cfi_def_cfa_register $fp" 263 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 264 BuildMI(MBB, MBBI, dl, 265 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 266 DstML = MachineLocation(FP); 267 SrcML = MachineLocation(MachineLocation::VirtualFP); 268 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); 269 } 270 271 // Restore GP from the saved stack location 272 if (MipsFI->needGPSaveRestore()) { 273 unsigned Offset = MFI->getObjectOffset(MipsFI->getGPFI()); 274 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset); 275 276 if (Offset >= 0x8000) { 277 BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::MACRO)); 278 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 279 } 280 } 281 } 282 283 void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 284 MachineBasicBlock &MBB) const { 285 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 286 MachineFrameInfo *MFI = MF.getFrameInfo(); 287 const MipsInstrInfo &TII = 288 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 289 DebugLoc dl = MBBI->getDebugLoc(); 290 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 291 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 292 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 293 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 294 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 295 296 // if framepointer enabled, restore the stack pointer. 297 if (hasFP(MF)) { 298 // Find the first instruction that restores a callee-saved register. 299 MachineBasicBlock::iterator I = MBBI; 300 301 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 302 --I; 303 304 // Insert instruction "move $sp, $fp" at this location. 305 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 306 } 307 308 // Get the number of bytes from FrameInfo 309 uint64_t StackSize = MFI->getStackSize(); 310 311 if (!StackSize) 312 return; 313 314 // Adjust stack. 315 if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize) 316 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize); 317 else // Expand immediate that doesn't fit in 16-bit. 318 expandLargeImm(SP, StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 319 } 320 321 void MipsFrameLowering:: 322 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 323 RegScavenger *RS) const { 324 MachineRegisterInfo& MRI = MF.getRegInfo(); 325 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA; 326 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 327 328 // FIXME: remove this code if register allocator can correctly mark 329 // $fp and $ra used or unused. 330 331 // Mark $fp and $ra as used or unused. 332 if (hasFP(MF)) 333 MRI.setPhysRegUsed(FP); 334 335 // The register allocator might determine $ra is used after seeing 336 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert 337 // instructions to save/restore $ra unless there is a function call. 338 // To correct this, $ra is explicitly marked unused if there is no 339 // function call. 340 if (MF.getFrameInfo()->hasCalls()) 341 MRI.setPhysRegUsed(RA); 342 else 343 MRI.setPhysRegUnused(RA); 344 } 345