1fcef3e46SJacques Pienaar//===- LanaiRegisterInfo.td - Lanai Register defs ------------*- tablegen -*-===// 2fcef3e46SJacques Pienaar// 3*2946cd70SChandler Carruth// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*2946cd70SChandler Carruth// See https://llvm.org/LICENSE.txt for license information. 5*2946cd70SChandler Carruth// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6fcef3e46SJacques Pienaar// 7fcef3e46SJacques Pienaar//===----------------------------------------------------------------------===// 8fcef3e46SJacques Pienaar// Declarations that describe the Lanai register file 9fcef3e46SJacques Pienaar//===----------------------------------------------------------------------===// 10fcef3e46SJacques Pienaar 11fcef3e46SJacques Pienaar// Registers are identified with 5-bit ID numbers. 12fcef3e46SJacques Pienaarclass LanaiReg<bits<5> num, string n, list<Register> subregs = [], 13fcef3e46SJacques Pienaar list<string> altNames = []> : Register<n, altNames> { 14fcef3e46SJacques Pienaar field bits<5> Num; 15fcef3e46SJacques Pienaar let Num = num; 16fcef3e46SJacques Pienaar let Namespace = "Lanai"; 17fcef3e46SJacques Pienaar let SubRegs = subregs; 18fcef3e46SJacques Pienaar} 19fcef3e46SJacques Pienaar 20fcef3e46SJacques Pienaarlet Namespace = "Lanai" in { 21fcef3e46SJacques Pienaar def sub_32 : SubRegIndex<32>; 22fcef3e46SJacques Pienaar} 23fcef3e46SJacques Pienaar 24fcef3e46SJacques Pienaar// Integer registers 25fcef3e46SJacques Pienaarforeach i = 0-31 in { 26fcef3e46SJacques Pienaar def R#i : LanaiReg<i, "r"#i>, DwarfRegNum<[i]>; 27fcef3e46SJacques Pienaar} 28fcef3e46SJacques Pienaar 29fcef3e46SJacques Pienaar// Register aliases 30fcef3e46SJacques Pienaarlet SubRegIndices = [sub_32] in { 31fcef3e46SJacques Pienaar def PC : LanaiReg< 2, "pc", [R2]>, DwarfRegAlias<R2>; 32fcef3e46SJacques Pienaar def SP : LanaiReg< 4, "sp", [R4]>, DwarfRegAlias<R4>; 33fcef3e46SJacques Pienaar def FP : LanaiReg< 5, "fp", [R5]>, DwarfRegAlias<R5>; 34fcef3e46SJacques Pienaar def RV : LanaiReg< 8, "rv", [R8]>, DwarfRegAlias<R8>; 35fcef3e46SJacques Pienaar def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>; 36fcef3e46SJacques Pienaar def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>; 37fcef3e46SJacques Pienaar def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>; 38fcef3e46SJacques Pienaar} 39fcef3e46SJacques Pienaar 40fcef3e46SJacques Pienaar// Define a status register to capture the dependencies between the set flag 41fcef3e46SJacques Pienaar// and setcc instructions 42fcef3e46SJacques Pienaardef SR : LanaiReg< 0, "sw">; 43fcef3e46SJacques Pienaar 44fcef3e46SJacques Pienaar// Register classes. 45fcef3e46SJacques Pienaardef GPR : RegisterClass<"Lanai", [i32], 32, 46fcef3e46SJacques Pienaar (add R3, R9, R12, R13, R14, R16, R17, 47fcef3e46SJacques Pienaar (sequence "R%i", 20, 31), 48fcef3e46SJacques Pienaar R6, R7, R18, R19, // registers for passing arguments 49fcef3e46SJacques Pienaar R15, RCA, // register for constant addresses 50fcef3e46SJacques Pienaar R10, RR1, R11, RR2, // programmer controlled registers 51fcef3e46SJacques Pienaar R8, RV, // return value 52fcef3e46SJacques Pienaar R5, FP, // frame pointer 53fcef3e46SJacques Pienaar R4, SP, // stack pointer 54fcef3e46SJacques Pienaar R2, PC, // program counter 55fcef3e46SJacques Pienaar R1, // all 1s (0xffffffff) 56fcef3e46SJacques Pienaar R0 // constant 0 57fcef3e46SJacques Pienaar )>; 58fcef3e46SJacques Pienaar 59fcef3e46SJacques Pienaar// Condition code register class 60fcef3e46SJacques Pienaardef CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> { 61fcef3e46SJacques Pienaar let CopyCost = -1; // Don't allow copying of status registers 62fcef3e46SJacques Pienaar let isAllocatable = 0; 63fcef3e46SJacques Pienaar} 64