xref: /llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV71.td (revision a98fc08396cb71f9e0cce4ac8f1525db46f22a9c)
1*a98fc083SKrzysztof Parzyszek//=-HexagonScheduleV71.td - HexagonV71 Scheduling Definitions *- tablegen -*-=//
2*a98fc083SKrzysztof Parzyszek//
3*a98fc083SKrzysztof Parzyszek//                     The LLVM Compiler Infrastructure
4*a98fc083SKrzysztof Parzyszek//
5*a98fc083SKrzysztof Parzyszek// This file is distributed under the University of Illinois Open Source
6*a98fc083SKrzysztof Parzyszek// License. See LICENSE.TXT for details.
7*a98fc083SKrzysztof Parzyszek//
8*a98fc083SKrzysztof Parzyszek//===----------------------------------------------------------------------===//
9*a98fc083SKrzysztof Parzyszek
10*a98fc083SKrzysztof Parzyszek//
11*a98fc083SKrzysztof Parzyszek// ScalarItin and HVXItin contain some old itineraries still used by a handful
12*a98fc083SKrzysztof Parzyszek// of instructions. Hopefully, we will be able to get rid of them soon.
13*a98fc083SKrzysztof Parzyszekdef HexagonV71ItinList : DepScalarItinV71, ScalarItin,
14*a98fc083SKrzysztof Parzyszek                         DepHVXItinV71, HVXItin, PseudoItin {
15*a98fc083SKrzysztof Parzyszek  list<InstrItinData> ItinList =
16*a98fc083SKrzysztof Parzyszek    !listconcat(DepScalarItinV71_list, ScalarItin_list,
17*a98fc083SKrzysztof Parzyszek                DepHVXItinV71_list, HVXItin_list, PseudoItin_list);
18*a98fc083SKrzysztof Parzyszek}
19*a98fc083SKrzysztof Parzyszek
20*a98fc083SKrzysztof Parzyszekdef HexagonItinerariesV71 :
21*a98fc083SKrzysztof Parzyszek      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
22*a98fc083SKrzysztof Parzyszek                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
23*a98fc083SKrzysztof Parzyszek                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
24*a98fc083SKrzysztof Parzyszek                            CVI_ALL_NOMEM, CVI_ZW],
25*a98fc083SKrzysztof Parzyszek                            [Hex_FWD, HVX_FWD],
26*a98fc083SKrzysztof Parzyszek                            HexagonV71ItinList.ItinList>;
27*a98fc083SKrzysztof Parzyszek
28*a98fc083SKrzysztof Parzyszekdef HexagonModelV71 : SchedMachineModel {
29*a98fc083SKrzysztof Parzyszek  // Max issue per cycle == bundle width.
30*a98fc083SKrzysztof Parzyszek  let IssueWidth = 4;
31*a98fc083SKrzysztof Parzyszek  let Itineraries = HexagonItinerariesV71;
32*a98fc083SKrzysztof Parzyszek  let LoadLatency = 1;
33*a98fc083SKrzysztof Parzyszek  let CompleteModel = 0;
34*a98fc083SKrzysztof Parzyszek}
35*a98fc083SKrzysztof Parzyszek
36*a98fc083SKrzysztof Parzyszek//===----------------------------------------------------------------------===//
37*a98fc083SKrzysztof Parzyszek// Hexagon V71 Resource Definitions -
38*a98fc083SKrzysztof Parzyszek//===----------------------------------------------------------------------===//
39*a98fc083SKrzysztof Parzyszek
40