1 //===- Memory.cpp - Memory Handling Support ---------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines some helpful functions for allocating memory and dealing 11 // with memory mapped files 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/Support/Memory.h" 16 #include "llvm/Support/Valgrind.h" 17 #include "llvm/Config/config.h" 18 19 namespace llvm { 20 using namespace sys; 21 } 22 23 // Include the platform-specific parts of this class. 24 #ifdef LLVM_ON_UNIX 25 #include "Unix/Memory.inc" 26 #endif 27 #ifdef LLVM_ON_WIN32 28 #include "Windows/Memory.inc" 29 #endif 30 31 extern "C" void sys_icache_invalidate(const void *Addr, size_t len); 32 33 /// ClearMipsCache - Invalidates instruction cache for Mips. This assembly code 34 /// is copied from the MIPS32 Instruction Set Reference. Since the code ends 35 /// with the return instruction "jr.hb ra" (Jump Register with Hazard Barrier), 36 /// it must be implemented as a function (which is called from the 37 /// InvalidateInstructionCache function). It cannot be directly inlined into 38 /// InvalidateInstructionCache function, because in that case the epilog of 39 /// InvalidateInstructionCache will not be executed. 40 #if defined(__mips__) 41 extern "C" void ClearMipsCache(const void* Addr, size_t Size); 42 asm volatile( 43 ".text\n" 44 ".align 2\n" 45 ".globl ClearMipsCache\n" 46 "ClearMipsCache:\n" 47 ".set noreorder\n" 48 "beq $a1, $zero, 20f\n" /* If size==0, branch around */ 49 "nop\n" 50 "addu $a1, $a0, $a1\n" /* Calculate end address + 1 */ 51 "rdhwr $v0, $1\n" /* Get step size for SYNCI */ 52 /* $1 is $HW_SYNCI_Step */ 53 "beq $v0, $zero, 20f\n" /* If no caches require synchronization, */ 54 /* branch around */ 55 "nop\n" 56 "10: synci 0($a0)\n" /* Synchronize all caches around address */ 57 "sltu $v1, $a0, $a1\n" /* Compare current with end address */ 58 "bne $v1, $zero, 10b\n" /* Branch if more to do */ 59 "addu $a0, $a0, $v0\n" /* Add step size in delay slot */ 60 "sync\n" /* Clear memory hazards */ 61 "20: jr.hb $ra\n" /* Return, clearing instruction hazards */ 62 "nop\n" 63 ); 64 #endif 65 66 /// InvalidateInstructionCache - Before the JIT can run a block of code 67 /// that has been emitted it must invalidate the instruction cache on some 68 /// platforms. 69 void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr, 70 size_t Len) { 71 72 // icache invalidation for PPC and ARM. 73 #if defined(__APPLE__) 74 75 # if (defined(__POWERPC__) || defined (__ppc__) || \ 76 defined(_POWER) || defined(_ARCH_PPC)) || defined(__arm__) 77 sys_icache_invalidate(Addr, Len); 78 # endif 79 80 #else 81 82 # if (defined(__POWERPC__) || defined (__ppc__) || \ 83 defined(_POWER) || defined(_ARCH_PPC)) && defined(__GNUC__) 84 const size_t LineSize = 32; 85 86 const intptr_t Mask = ~(LineSize - 1); 87 const intptr_t StartLine = ((intptr_t) Addr) & Mask; 88 const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask; 89 90 for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize) 91 asm volatile("dcbf 0, %0" : : "r"(Line)); 92 asm volatile("sync"); 93 94 for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize) 95 asm volatile("icbi 0, %0" : : "r"(Line)); 96 asm volatile("isync"); 97 # elif defined(__arm__) && defined(__GNUC__) 98 // FIXME: Can we safely always call this for __GNUC__ everywhere? 99 char *Start = (char*) Addr; 100 char *End = Start + Len; 101 __clear_cache(Start, End); 102 # elif defined(__mips__) 103 ClearMipsCache(Addr, Len); 104 # endif 105 106 #endif // end apple 107 108 ValgrindDiscardTranslations(Addr, Len); 109 } 110