xref: /llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (revision 675231eb09ca37a8b76f748c0b73a1e26604ff20)
1 //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating from LLVM IR into SelectionDAG IR.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SelectionDAGBuilder.h"
14 #include "SDNodeDbgValue.h"
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Analysis/BranchProbabilityInfo.h"
25 #include "llvm/Analysis/ConstantFolding.h"
26 #include "llvm/Analysis/Loads.h"
27 #include "llvm/Analysis/MemoryLocation.h"
28 #include "llvm/Analysis/TargetLibraryInfo.h"
29 #include "llvm/Analysis/ValueTracking.h"
30 #include "llvm/Analysis/VectorUtils.h"
31 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/AssignmentTrackingAnalysis.h"
33 #include "llvm/CodeGen/CodeGenCommonISel.h"
34 #include "llvm/CodeGen/FunctionLoweringInfo.h"
35 #include "llvm/CodeGen/GCMetadata.h"
36 #include "llvm/CodeGen/ISDOpcodes.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineInstrBundleIterator.h"
42 #include "llvm/CodeGen/MachineMemOperand.h"
43 #include "llvm/CodeGen/MachineModuleInfo.h"
44 #include "llvm/CodeGen/MachineOperand.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/RuntimeLibcalls.h"
47 #include "llvm/CodeGen/SelectionDAG.h"
48 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
49 #include "llvm/CodeGen/StackMaps.h"
50 #include "llvm/CodeGen/SwiftErrorValueTracking.h"
51 #include "llvm/CodeGen/TargetFrameLowering.h"
52 #include "llvm/CodeGen/TargetInstrInfo.h"
53 #include "llvm/CodeGen/TargetOpcodes.h"
54 #include "llvm/CodeGen/TargetRegisterInfo.h"
55 #include "llvm/CodeGen/TargetSubtargetInfo.h"
56 #include "llvm/CodeGen/WinEHFuncInfo.h"
57 #include "llvm/IR/Argument.h"
58 #include "llvm/IR/Attributes.h"
59 #include "llvm/IR/BasicBlock.h"
60 #include "llvm/IR/CFG.h"
61 #include "llvm/IR/CallingConv.h"
62 #include "llvm/IR/Constant.h"
63 #include "llvm/IR/ConstantRange.h"
64 #include "llvm/IR/Constants.h"
65 #include "llvm/IR/DataLayout.h"
66 #include "llvm/IR/DebugInfo.h"
67 #include "llvm/IR/DebugInfoMetadata.h"
68 #include "llvm/IR/DerivedTypes.h"
69 #include "llvm/IR/DiagnosticInfo.h"
70 #include "llvm/IR/EHPersonalities.h"
71 #include "llvm/IR/Function.h"
72 #include "llvm/IR/GetElementPtrTypeIterator.h"
73 #include "llvm/IR/InlineAsm.h"
74 #include "llvm/IR/InstrTypes.h"
75 #include "llvm/IR/Instructions.h"
76 #include "llvm/IR/IntrinsicInst.h"
77 #include "llvm/IR/Intrinsics.h"
78 #include "llvm/IR/IntrinsicsAArch64.h"
79 #include "llvm/IR/IntrinsicsWebAssembly.h"
80 #include "llvm/IR/LLVMContext.h"
81 #include "llvm/IR/Metadata.h"
82 #include "llvm/IR/Module.h"
83 #include "llvm/IR/Operator.h"
84 #include "llvm/IR/PatternMatch.h"
85 #include "llvm/IR/Statepoint.h"
86 #include "llvm/IR/Type.h"
87 #include "llvm/IR/User.h"
88 #include "llvm/IR/Value.h"
89 #include "llvm/MC/MCContext.h"
90 #include "llvm/Support/AtomicOrdering.h"
91 #include "llvm/Support/Casting.h"
92 #include "llvm/Support/CommandLine.h"
93 #include "llvm/Support/Compiler.h"
94 #include "llvm/Support/Debug.h"
95 #include "llvm/Support/MathExtras.h"
96 #include "llvm/Support/raw_ostream.h"
97 #include "llvm/Target/TargetIntrinsicInfo.h"
98 #include "llvm/Target/TargetMachine.h"
99 #include "llvm/Target/TargetOptions.h"
100 #include "llvm/TargetParser/Triple.h"
101 #include "llvm/Transforms/Utils/Local.h"
102 #include <cstddef>
103 #include <iterator>
104 #include <limits>
105 #include <optional>
106 #include <tuple>
107 
108 using namespace llvm;
109 using namespace PatternMatch;
110 using namespace SwitchCG;
111 
112 #define DEBUG_TYPE "isel"
113 
114 /// LimitFloatPrecision - Generate low-precision inline sequences for
115 /// some float libcalls (6, 8 or 12 bits).
116 static unsigned LimitFloatPrecision;
117 
118 static cl::opt<bool>
119     InsertAssertAlign("insert-assert-align", cl::init(true),
120                       cl::desc("Insert the experimental `assertalign` node."),
121                       cl::ReallyHidden);
122 
123 static cl::opt<unsigned, true>
124     LimitFPPrecision("limit-float-precision",
125                      cl::desc("Generate low-precision inline sequences "
126                               "for some float libcalls"),
127                      cl::location(LimitFloatPrecision), cl::Hidden,
128                      cl::init(0));
129 
130 static cl::opt<unsigned> SwitchPeelThreshold(
131     "switch-peel-threshold", cl::Hidden, cl::init(66),
132     cl::desc("Set the case probability threshold for peeling the case from a "
133              "switch statement. A value greater than 100 will void this "
134              "optimization"));
135 
136 // Limit the width of DAG chains. This is important in general to prevent
137 // DAG-based analysis from blowing up. For example, alias analysis and
138 // load clustering may not complete in reasonable time. It is difficult to
139 // recognize and avoid this situation within each individual analysis, and
140 // future analyses are likely to have the same behavior. Limiting DAG width is
141 // the safe approach and will be especially important with global DAGs.
142 //
143 // MaxParallelChains default is arbitrarily high to avoid affecting
144 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
145 // sequence over this should have been converted to llvm.memcpy by the
146 // frontend. It is easy to induce this behavior with .ll code such as:
147 // %buffer = alloca [4096 x i8]
148 // %data = load [4096 x i8]* %argPtr
149 // store [4096 x i8] %data, [4096 x i8]* %buffer
150 static const unsigned MaxParallelChains = 64;
151 
152 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
153                                       const SDValue *Parts, unsigned NumParts,
154                                       MVT PartVT, EVT ValueVT, const Value *V,
155                                       std::optional<CallingConv::ID> CC);
156 
157 /// getCopyFromParts - Create a value that contains the specified legal parts
158 /// combined into the value they represent.  If the parts combine to a type
159 /// larger than ValueVT then AssertOp can be used to specify whether the extra
160 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
161 /// (ISD::AssertSext).
162 static SDValue
163 getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
164                  unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V,
165                  std::optional<CallingConv::ID> CC = std::nullopt,
166                  std::optional<ISD::NodeType> AssertOp = std::nullopt) {
167   // Let the target assemble the parts if it wants to
168   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
169   if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts,
170                                                    PartVT, ValueVT, CC))
171     return Val;
172 
173   if (ValueVT.isVector())
174     return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
175                                   CC);
176 
177   assert(NumParts > 0 && "No parts to assemble!");
178   SDValue Val = Parts[0];
179 
180   if (NumParts > 1) {
181     // Assemble the value from multiple parts.
182     if (ValueVT.isInteger()) {
183       unsigned PartBits = PartVT.getSizeInBits();
184       unsigned ValueBits = ValueVT.getSizeInBits();
185 
186       // Assemble the power of 2 part.
187       unsigned RoundParts = llvm::bit_floor(NumParts);
188       unsigned RoundBits = PartBits * RoundParts;
189       EVT RoundVT = RoundBits == ValueBits ?
190         ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
191       SDValue Lo, Hi;
192 
193       EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
194 
195       if (RoundParts > 2) {
196         Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
197                               PartVT, HalfVT, V);
198         Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
199                               RoundParts / 2, PartVT, HalfVT, V);
200       } else {
201         Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
202         Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
203       }
204 
205       if (DAG.getDataLayout().isBigEndian())
206         std::swap(Lo, Hi);
207 
208       Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
209 
210       if (RoundParts < NumParts) {
211         // Assemble the trailing non-power-of-2 part.
212         unsigned OddParts = NumParts - RoundParts;
213         EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
214         Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT,
215                               OddVT, V, CC);
216 
217         // Combine the round and odd parts.
218         Lo = Val;
219         if (DAG.getDataLayout().isBigEndian())
220           std::swap(Lo, Hi);
221         EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
222         Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
223         Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
224                          DAG.getConstant(Lo.getValueSizeInBits(), DL,
225                                          TLI.getShiftAmountTy(
226                                              TotalVT, DAG.getDataLayout())));
227         Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
228         Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
229       }
230     } else if (PartVT.isFloatingPoint()) {
231       // FP split into multiple FP parts (for ppcf128)
232       assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
233              "Unexpected split");
234       SDValue Lo, Hi;
235       Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
236       Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
237       if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
238         std::swap(Lo, Hi);
239       Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
240     } else {
241       // FP split into integer parts (soft fp)
242       assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
243              !PartVT.isVector() && "Unexpected split");
244       EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
245       Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC);
246     }
247   }
248 
249   // There is now one part, held in Val.  Correct it to match ValueVT.
250   // PartEVT is the type of the register class that holds the value.
251   // ValueVT is the type of the inline asm operation.
252   EVT PartEVT = Val.getValueType();
253 
254   if (PartEVT == ValueVT)
255     return Val;
256 
257   if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
258       ValueVT.bitsLT(PartEVT)) {
259     // For an FP value in an integer part, we need to truncate to the right
260     // width first.
261     PartEVT = EVT::getIntegerVT(*DAG.getContext(),  ValueVT.getSizeInBits());
262     Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
263   }
264 
265   // Handle types that have the same size.
266   if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
267     return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
268 
269   // Handle types with different sizes.
270   if (PartEVT.isInteger() && ValueVT.isInteger()) {
271     if (ValueVT.bitsLT(PartEVT)) {
272       // For a truncate, see if we have any information to
273       // indicate whether the truncated bits will always be
274       // zero or sign-extension.
275       if (AssertOp)
276         Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
277                           DAG.getValueType(ValueVT));
278       return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
279     }
280     return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
281   }
282 
283   if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
284     // FP_ROUND's are always exact here.
285     if (ValueVT.bitsLT(Val.getValueType()))
286       return DAG.getNode(
287           ISD::FP_ROUND, DL, ValueVT, Val,
288           DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
289 
290     return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
291   }
292 
293   // Handle MMX to a narrower integer type by bitcasting MMX to integer and
294   // then truncating.
295   if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
296       ValueVT.bitsLT(PartEVT)) {
297     Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val);
298     return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
299   }
300 
301   report_fatal_error("Unknown mismatch in getCopyFromParts!");
302 }
303 
304 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
305                                               const Twine &ErrMsg) {
306   const Instruction *I = dyn_cast_or_null<Instruction>(V);
307   if (!V)
308     return Ctx.emitError(ErrMsg);
309 
310   const char *AsmError = ", possible invalid constraint for vector type";
311   if (const CallInst *CI = dyn_cast<CallInst>(I))
312     if (CI->isInlineAsm())
313       return Ctx.emitError(I, ErrMsg + AsmError);
314 
315   return Ctx.emitError(I, ErrMsg);
316 }
317 
318 /// getCopyFromPartsVector - Create a value that contains the specified legal
319 /// parts combined into the value they represent.  If the parts combine to a
320 /// type larger than ValueVT then AssertOp can be used to specify whether the
321 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
322 /// ValueVT (ISD::AssertSext).
323 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
324                                       const SDValue *Parts, unsigned NumParts,
325                                       MVT PartVT, EVT ValueVT, const Value *V,
326                                       std::optional<CallingConv::ID> CallConv) {
327   assert(ValueVT.isVector() && "Not a vector value");
328   assert(NumParts > 0 && "No parts to assemble!");
329   const bool IsABIRegCopy = CallConv.has_value();
330 
331   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
332   SDValue Val = Parts[0];
333 
334   // Handle a multi-element vector.
335   if (NumParts > 1) {
336     EVT IntermediateVT;
337     MVT RegisterVT;
338     unsigned NumIntermediates;
339     unsigned NumRegs;
340 
341     if (IsABIRegCopy) {
342       NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
343           *DAG.getContext(), *CallConv, ValueVT, IntermediateVT,
344           NumIntermediates, RegisterVT);
345     } else {
346       NumRegs =
347           TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
348                                      NumIntermediates, RegisterVT);
349     }
350 
351     assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
352     NumParts = NumRegs; // Silence a compiler warning.
353     assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
354     assert(RegisterVT.getSizeInBits() ==
355            Parts[0].getSimpleValueType().getSizeInBits() &&
356            "Part type sizes don't match!");
357 
358     // Assemble the parts into intermediate operands.
359     SmallVector<SDValue, 8> Ops(NumIntermediates);
360     if (NumIntermediates == NumParts) {
361       // If the register was not expanded, truncate or copy the value,
362       // as appropriate.
363       for (unsigned i = 0; i != NumParts; ++i)
364         Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
365                                   PartVT, IntermediateVT, V, CallConv);
366     } else if (NumParts > 0) {
367       // If the intermediate type was expanded, build the intermediate
368       // operands from the parts.
369       assert(NumParts % NumIntermediates == 0 &&
370              "Must expand into a divisible number of parts!");
371       unsigned Factor = NumParts / NumIntermediates;
372       for (unsigned i = 0; i != NumIntermediates; ++i)
373         Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
374                                   PartVT, IntermediateVT, V, CallConv);
375     }
376 
377     // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
378     // intermediate operands.
379     EVT BuiltVectorTy =
380         IntermediateVT.isVector()
381             ? EVT::getVectorVT(
382                   *DAG.getContext(), IntermediateVT.getScalarType(),
383                   IntermediateVT.getVectorElementCount() * NumParts)
384             : EVT::getVectorVT(*DAG.getContext(),
385                                IntermediateVT.getScalarType(),
386                                NumIntermediates);
387     Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
388                                                 : ISD::BUILD_VECTOR,
389                       DL, BuiltVectorTy, Ops);
390   }
391 
392   // There is now one part, held in Val.  Correct it to match ValueVT.
393   EVT PartEVT = Val.getValueType();
394 
395   if (PartEVT == ValueVT)
396     return Val;
397 
398   if (PartEVT.isVector()) {
399     // Vector/Vector bitcast.
400     if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
401       return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
402 
403     // If the parts vector has more elements than the value vector, then we
404     // have a vector widening case (e.g. <2 x float> -> <4 x float>).
405     // Extract the elements we want.
406     if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) {
407       assert((PartEVT.getVectorElementCount().getKnownMinValue() >
408               ValueVT.getVectorElementCount().getKnownMinValue()) &&
409              (PartEVT.getVectorElementCount().isScalable() ==
410               ValueVT.getVectorElementCount().isScalable()) &&
411              "Cannot narrow, it would be a lossy transformation");
412       PartEVT =
413           EVT::getVectorVT(*DAG.getContext(), PartEVT.getVectorElementType(),
414                            ValueVT.getVectorElementCount());
415       Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, PartEVT, Val,
416                         DAG.getVectorIdxConstant(0, DL));
417       if (PartEVT == ValueVT)
418         return Val;
419       if (PartEVT.isInteger() && ValueVT.isFloatingPoint())
420         return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
421 
422       // Vector/Vector bitcast (e.g. <2 x bfloat> -> <2 x half>).
423       if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
424         return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
425     }
426 
427     // Promoted vector extract
428     return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
429   }
430 
431   // Trivial bitcast if the types are the same size and the destination
432   // vector type is legal.
433   if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
434       TLI.isTypeLegal(ValueVT))
435     return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
436 
437   if (ValueVT.getVectorNumElements() != 1) {
438      // Certain ABIs require that vectors are passed as integers. For vectors
439      // are the same size, this is an obvious bitcast.
440      if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
441        return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
442      } else if (ValueVT.bitsLT(PartEVT)) {
443        const uint64_t ValueSize = ValueVT.getFixedSizeInBits();
444        EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize);
445        // Drop the extra bits.
446        Val = DAG.getNode(ISD::TRUNCATE, DL, IntermediateType, Val);
447        return DAG.getBitcast(ValueVT, Val);
448      }
449 
450      diagnosePossiblyInvalidConstraint(
451          *DAG.getContext(), V, "non-trivial scalar-to-vector conversion");
452      return DAG.getUNDEF(ValueVT);
453   }
454 
455   // Handle cases such as i8 -> <1 x i1>
456   EVT ValueSVT = ValueVT.getVectorElementType();
457   if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) {
458     unsigned ValueSize = ValueSVT.getSizeInBits();
459     if (ValueSize == PartEVT.getSizeInBits()) {
460       Val = DAG.getNode(ISD::BITCAST, DL, ValueSVT, Val);
461     } else if (ValueSVT.isFloatingPoint() && PartEVT.isInteger()) {
462       // It's possible a scalar floating point type gets softened to integer and
463       // then promoted to a larger integer. If PartEVT is the larger integer
464       // we need to truncate it and then bitcast to the FP type.
465       assert(ValueSVT.bitsLT(PartEVT) && "Unexpected types");
466       EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize);
467       Val = DAG.getNode(ISD::TRUNCATE, DL, IntermediateType, Val);
468       Val = DAG.getBitcast(ValueSVT, Val);
469     } else {
470       Val = ValueVT.isFloatingPoint()
471                 ? DAG.getFPExtendOrRound(Val, DL, ValueSVT)
472                 : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT);
473     }
474   }
475 
476   return DAG.getBuildVector(ValueVT, DL, Val);
477 }
478 
479 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
480                                  SDValue Val, SDValue *Parts, unsigned NumParts,
481                                  MVT PartVT, const Value *V,
482                                  std::optional<CallingConv::ID> CallConv);
483 
484 /// getCopyToParts - Create a series of nodes that contain the specified value
485 /// split into legal parts.  If the parts contain more bits than Val, then, for
486 /// integers, ExtendKind can be used to specify how to generate the extra bits.
487 static void
488 getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
489                unsigned NumParts, MVT PartVT, const Value *V,
490                std::optional<CallingConv::ID> CallConv = std::nullopt,
491                ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
492   // Let the target split the parts if it wants to
493   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
494   if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT,
495                                       CallConv))
496     return;
497   EVT ValueVT = Val.getValueType();
498 
499   // Handle the vector case separately.
500   if (ValueVT.isVector())
501     return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V,
502                                 CallConv);
503 
504   unsigned OrigNumParts = NumParts;
505   assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
506          "Copying to an illegal type!");
507 
508   if (NumParts == 0)
509     return;
510 
511   assert(!ValueVT.isVector() && "Vector case handled elsewhere");
512   EVT PartEVT = PartVT;
513   if (PartEVT == ValueVT) {
514     assert(NumParts == 1 && "No-op copy with multiple parts!");
515     Parts[0] = Val;
516     return;
517   }
518 
519   unsigned PartBits = PartVT.getSizeInBits();
520   if (NumParts * PartBits > ValueVT.getSizeInBits()) {
521     // If the parts cover more bits than the value has, promote the value.
522     if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
523       assert(NumParts == 1 && "Do not know what to promote to!");
524       Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
525     } else {
526       if (ValueVT.isFloatingPoint()) {
527         // FP values need to be bitcast, then extended if they are being put
528         // into a larger container.
529         ValueVT = EVT::getIntegerVT(*DAG.getContext(),  ValueVT.getSizeInBits());
530         Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
531       }
532       assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
533              ValueVT.isInteger() &&
534              "Unknown mismatch!");
535       ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
536       Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
537       if (PartVT == MVT::x86mmx)
538         Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
539     }
540   } else if (PartBits == ValueVT.getSizeInBits()) {
541     // Different types of the same size.
542     assert(NumParts == 1 && PartEVT != ValueVT);
543     Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
544   } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
545     // If the parts cover less bits than value has, truncate the value.
546     assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
547            ValueVT.isInteger() &&
548            "Unknown mismatch!");
549     ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
550     Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
551     if (PartVT == MVT::x86mmx)
552       Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
553   }
554 
555   // The value may have changed - recompute ValueVT.
556   ValueVT = Val.getValueType();
557   assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
558          "Failed to tile the value with PartVT!");
559 
560   if (NumParts == 1) {
561     if (PartEVT != ValueVT) {
562       diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
563                                         "scalar-to-vector conversion failed");
564       Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
565     }
566 
567     Parts[0] = Val;
568     return;
569   }
570 
571   // Expand the value into multiple parts.
572   if (NumParts & (NumParts - 1)) {
573     // The number of parts is not a power of 2.  Split off and copy the tail.
574     assert(PartVT.isInteger() && ValueVT.isInteger() &&
575            "Do not know what to expand to!");
576     unsigned RoundParts = llvm::bit_floor(NumParts);
577     unsigned RoundBits = RoundParts * PartBits;
578     unsigned OddParts = NumParts - RoundParts;
579     SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
580       DAG.getShiftAmountConstant(RoundBits, ValueVT, DL));
581 
582     getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V,
583                    CallConv);
584 
585     if (DAG.getDataLayout().isBigEndian())
586       // The odd parts were reversed by getCopyToParts - unreverse them.
587       std::reverse(Parts + RoundParts, Parts + NumParts);
588 
589     NumParts = RoundParts;
590     ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
591     Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
592   }
593 
594   // The number of parts is a power of 2.  Repeatedly bisect the value using
595   // EXTRACT_ELEMENT.
596   Parts[0] = DAG.getNode(ISD::BITCAST, DL,
597                          EVT::getIntegerVT(*DAG.getContext(),
598                                            ValueVT.getSizeInBits()),
599                          Val);
600 
601   for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
602     for (unsigned i = 0; i < NumParts; i += StepSize) {
603       unsigned ThisBits = StepSize * PartBits / 2;
604       EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
605       SDValue &Part0 = Parts[i];
606       SDValue &Part1 = Parts[i+StepSize/2];
607 
608       Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
609                           ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
610       Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
611                           ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
612 
613       if (ThisBits == PartBits && ThisVT != PartVT) {
614         Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
615         Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
616       }
617     }
618   }
619 
620   if (DAG.getDataLayout().isBigEndian())
621     std::reverse(Parts, Parts + OrigNumParts);
622 }
623 
624 static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val,
625                                      const SDLoc &DL, EVT PartVT) {
626   if (!PartVT.isVector())
627     return SDValue();
628 
629   EVT ValueVT = Val.getValueType();
630   EVT PartEVT = PartVT.getVectorElementType();
631   EVT ValueEVT = ValueVT.getVectorElementType();
632   ElementCount PartNumElts = PartVT.getVectorElementCount();
633   ElementCount ValueNumElts = ValueVT.getVectorElementCount();
634 
635   // We only support widening vectors with equivalent element types and
636   // fixed/scalable properties. If a target needs to widen a fixed-length type
637   // to a scalable one, it should be possible to use INSERT_SUBVECTOR below.
638   if (ElementCount::isKnownLE(PartNumElts, ValueNumElts) ||
639       PartNumElts.isScalable() != ValueNumElts.isScalable())
640     return SDValue();
641 
642   // Have a try for bf16 because some targets share its ABI with fp16.
643   if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) {
644     assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
645            "Cannot widen to illegal type");
646     Val = DAG.getNode(ISD::BITCAST, DL,
647                       ValueVT.changeVectorElementType(MVT::f16), Val);
648   } else if (PartEVT != ValueEVT) {
649     return SDValue();
650   }
651 
652   // Widening a scalable vector to another scalable vector is done by inserting
653   // the vector into a larger undef one.
654   if (PartNumElts.isScalable())
655     return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT),
656                        Val, DAG.getVectorIdxConstant(0, DL));
657 
658   // Vector widening case, e.g. <2 x float> -> <4 x float>.  Shuffle in
659   // undef elements.
660   SmallVector<SDValue, 16> Ops;
661   DAG.ExtractVectorElements(Val, Ops);
662   SDValue EltUndef = DAG.getUNDEF(PartEVT);
663   Ops.append((PartNumElts - ValueNumElts).getFixedValue(), EltUndef);
664 
665   // FIXME: Use CONCAT for 2x -> 4x.
666   return DAG.getBuildVector(PartVT, DL, Ops);
667 }
668 
669 /// getCopyToPartsVector - Create a series of nodes that contain the specified
670 /// value split into legal parts.
671 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
672                                  SDValue Val, SDValue *Parts, unsigned NumParts,
673                                  MVT PartVT, const Value *V,
674                                  std::optional<CallingConv::ID> CallConv) {
675   EVT ValueVT = Val.getValueType();
676   assert(ValueVT.isVector() && "Not a vector");
677   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
678   const bool IsABIRegCopy = CallConv.has_value();
679 
680   if (NumParts == 1) {
681     EVT PartEVT = PartVT;
682     if (PartEVT == ValueVT) {
683       // Nothing to do.
684     } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
685       // Bitconvert vector->vector case.
686       Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
687     } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
688       Val = Widened;
689     } else if (PartVT.isVector() &&
690                PartEVT.getVectorElementType().bitsGE(
691                    ValueVT.getVectorElementType()) &&
692                PartEVT.getVectorElementCount() ==
693                    ValueVT.getVectorElementCount()) {
694 
695       // Promoted vector extract
696       Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
697     } else if (PartEVT.isVector() &&
698                PartEVT.getVectorElementType() !=
699                    ValueVT.getVectorElementType() &&
700                TLI.getTypeAction(*DAG.getContext(), ValueVT) ==
701                    TargetLowering::TypeWidenVector) {
702       // Combination of widening and promotion.
703       EVT WidenVT =
704           EVT::getVectorVT(*DAG.getContext(), ValueVT.getVectorElementType(),
705                            PartVT.getVectorElementCount());
706       SDValue Widened = widenVectorToPartType(DAG, Val, DL, WidenVT);
707       Val = DAG.getAnyExtOrTrunc(Widened, DL, PartVT);
708     } else {
709       // Don't extract an integer from a float vector. This can happen if the
710       // FP type gets softened to integer and then promoted. The promotion
711       // prevents it from being picked up by the earlier bitcast case.
712       if (ValueVT.getVectorElementCount().isScalar() &&
713           (!ValueVT.isFloatingPoint() || !PartVT.isInteger())) {
714         Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
715                           DAG.getVectorIdxConstant(0, DL));
716       } else {
717         uint64_t ValueSize = ValueVT.getFixedSizeInBits();
718         assert(PartVT.getFixedSizeInBits() > ValueSize &&
719                "lossy conversion of vector to scalar type");
720         EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize);
721         Val = DAG.getBitcast(IntermediateType, Val);
722         Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
723       }
724     }
725 
726     assert(Val.getValueType() == PartVT && "Unexpected vector part value type");
727     Parts[0] = Val;
728     return;
729   }
730 
731   // Handle a multi-element vector.
732   EVT IntermediateVT;
733   MVT RegisterVT;
734   unsigned NumIntermediates;
735   unsigned NumRegs;
736   if (IsABIRegCopy) {
737     NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
738         *DAG.getContext(), *CallConv, ValueVT, IntermediateVT, NumIntermediates,
739         RegisterVT);
740   } else {
741     NumRegs =
742         TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
743                                    NumIntermediates, RegisterVT);
744   }
745 
746   assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
747   NumParts = NumRegs; // Silence a compiler warning.
748   assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
749 
750   assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() &&
751          "Mixing scalable and fixed vectors when copying in parts");
752 
753   std::optional<ElementCount> DestEltCnt;
754 
755   if (IntermediateVT.isVector())
756     DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates;
757   else
758     DestEltCnt = ElementCount::getFixed(NumIntermediates);
759 
760   EVT BuiltVectorTy = EVT::getVectorVT(
761       *DAG.getContext(), IntermediateVT.getScalarType(), *DestEltCnt);
762 
763   if (ValueVT == BuiltVectorTy) {
764     // Nothing to do.
765   } else if (ValueVT.getSizeInBits() == BuiltVectorTy.getSizeInBits()) {
766     // Bitconvert vector->vector case.
767     Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val);
768   } else {
769     if (BuiltVectorTy.getVectorElementType().bitsGT(
770             ValueVT.getVectorElementType())) {
771       // Integer promotion.
772       ValueVT = EVT::getVectorVT(*DAG.getContext(),
773                                  BuiltVectorTy.getVectorElementType(),
774                                  ValueVT.getVectorElementCount());
775       Val = DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
776     }
777 
778     if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy)) {
779       Val = Widened;
780     }
781   }
782 
783   assert(Val.getValueType() == BuiltVectorTy && "Unexpected vector value type");
784 
785   // Split the vector into intermediate operands.
786   SmallVector<SDValue, 8> Ops(NumIntermediates);
787   for (unsigned i = 0; i != NumIntermediates; ++i) {
788     if (IntermediateVT.isVector()) {
789       // This does something sensible for scalable vectors - see the
790       // definition of EXTRACT_SUBVECTOR for further details.
791       unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements();
792       Ops[i] =
793           DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
794                       DAG.getVectorIdxConstant(i * IntermediateNumElts, DL));
795     } else {
796       Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
797                            DAG.getVectorIdxConstant(i, DL));
798     }
799   }
800 
801   // Split the intermediate operands into legal parts.
802   if (NumParts == NumIntermediates) {
803     // If the register was not expanded, promote or copy the value,
804     // as appropriate.
805     for (unsigned i = 0; i != NumParts; ++i)
806       getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv);
807   } else if (NumParts > 0) {
808     // If the intermediate type was expanded, split each the value into
809     // legal parts.
810     assert(NumIntermediates != 0 && "division by zero");
811     assert(NumParts % NumIntermediates == 0 &&
812            "Must expand into a divisible number of parts!");
813     unsigned Factor = NumParts / NumIntermediates;
814     for (unsigned i = 0; i != NumIntermediates; ++i)
815       getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V,
816                      CallConv);
817   }
818 }
819 
820 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt,
821                            EVT valuevt, std::optional<CallingConv::ID> CC)
822     : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
823       RegCount(1, regs.size()), CallConv(CC) {}
824 
825 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
826                            const DataLayout &DL, unsigned Reg, Type *Ty,
827                            std::optional<CallingConv::ID> CC) {
828   ComputeValueVTs(TLI, DL, Ty, ValueVTs);
829 
830   CallConv = CC;
831 
832   for (EVT ValueVT : ValueVTs) {
833     unsigned NumRegs =
834         isABIMangled()
835             ? TLI.getNumRegistersForCallingConv(Context, *CC, ValueVT)
836             : TLI.getNumRegisters(Context, ValueVT);
837     MVT RegisterVT =
838         isABIMangled()
839             ? TLI.getRegisterTypeForCallingConv(Context, *CC, ValueVT)
840             : TLI.getRegisterType(Context, ValueVT);
841     for (unsigned i = 0; i != NumRegs; ++i)
842       Regs.push_back(Reg + i);
843     RegVTs.push_back(RegisterVT);
844     RegCount.push_back(NumRegs);
845     Reg += NumRegs;
846   }
847 }
848 
849 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
850                                       FunctionLoweringInfo &FuncInfo,
851                                       const SDLoc &dl, SDValue &Chain,
852                                       SDValue *Glue, const Value *V) const {
853   // A Value with type {} or [0 x %t] needs no registers.
854   if (ValueVTs.empty())
855     return SDValue();
856 
857   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
858 
859   // Assemble the legal parts into the final values.
860   SmallVector<SDValue, 4> Values(ValueVTs.size());
861   SmallVector<SDValue, 8> Parts;
862   for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
863     // Copy the legal parts from the registers.
864     EVT ValueVT = ValueVTs[Value];
865     unsigned NumRegs = RegCount[Value];
866     MVT RegisterVT = isABIMangled()
867                          ? TLI.getRegisterTypeForCallingConv(
868                                *DAG.getContext(), *CallConv, RegVTs[Value])
869                          : RegVTs[Value];
870 
871     Parts.resize(NumRegs);
872     for (unsigned i = 0; i != NumRegs; ++i) {
873       SDValue P;
874       if (!Glue) {
875         P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
876       } else {
877         P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Glue);
878         *Glue = P.getValue(2);
879       }
880 
881       Chain = P.getValue(1);
882       Parts[i] = P;
883 
884       // If the source register was virtual and if we know something about it,
885       // add an assert node.
886       if (!Register::isVirtualRegister(Regs[Part + i]) ||
887           !RegisterVT.isInteger())
888         continue;
889 
890       const FunctionLoweringInfo::LiveOutInfo *LOI =
891         FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
892       if (!LOI)
893         continue;
894 
895       unsigned RegSize = RegisterVT.getScalarSizeInBits();
896       unsigned NumSignBits = LOI->NumSignBits;
897       unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
898 
899       if (NumZeroBits == RegSize) {
900         // The current value is a zero.
901         // Explicitly express that as it would be easier for
902         // optimizations to kick in.
903         Parts[i] = DAG.getConstant(0, dl, RegisterVT);
904         continue;
905       }
906 
907       // FIXME: We capture more information than the dag can represent.  For
908       // now, just use the tightest assertzext/assertsext possible.
909       bool isSExt;
910       EVT FromVT(MVT::Other);
911       if (NumZeroBits) {
912         FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
913         isSExt = false;
914       } else if (NumSignBits > 1) {
915         FromVT =
916             EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
917         isSExt = true;
918       } else {
919         continue;
920       }
921       // Add an assertion node.
922       assert(FromVT != MVT::Other);
923       Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
924                              RegisterVT, P, DAG.getValueType(FromVT));
925     }
926 
927     Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs,
928                                      RegisterVT, ValueVT, V, CallConv);
929     Part += NumRegs;
930     Parts.clear();
931   }
932 
933   return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
934 }
935 
936 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
937                                  const SDLoc &dl, SDValue &Chain, SDValue *Glue,
938                                  const Value *V,
939                                  ISD::NodeType PreferredExtendType) const {
940   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
941   ISD::NodeType ExtendKind = PreferredExtendType;
942 
943   // Get the list of the values's legal parts.
944   unsigned NumRegs = Regs.size();
945   SmallVector<SDValue, 8> Parts(NumRegs);
946   for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
947     unsigned NumParts = RegCount[Value];
948 
949     MVT RegisterVT = isABIMangled()
950                          ? TLI.getRegisterTypeForCallingConv(
951                                *DAG.getContext(), *CallConv, RegVTs[Value])
952                          : RegVTs[Value];
953 
954     if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
955       ExtendKind = ISD::ZERO_EXTEND;
956 
957     getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
958                    NumParts, RegisterVT, V, CallConv, ExtendKind);
959     Part += NumParts;
960   }
961 
962   // Copy the parts into the registers.
963   SmallVector<SDValue, 8> Chains(NumRegs);
964   for (unsigned i = 0; i != NumRegs; ++i) {
965     SDValue Part;
966     if (!Glue) {
967       Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
968     } else {
969       Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Glue);
970       *Glue = Part.getValue(1);
971     }
972 
973     Chains[i] = Part.getValue(0);
974   }
975 
976   if (NumRegs == 1 || Glue)
977     // If NumRegs > 1 && Glue is used then the use of the last CopyToReg is
978     // flagged to it. That is the CopyToReg nodes and the user are considered
979     // a single scheduling unit. If we create a TokenFactor and return it as
980     // chain, then the TokenFactor is both a predecessor (operand) of the
981     // user as well as a successor (the TF operands are flagged to the user).
982     // c1, f1 = CopyToReg
983     // c2, f2 = CopyToReg
984     // c3     = TokenFactor c1, c2
985     // ...
986     //        = op c3, ..., f2
987     Chain = Chains[NumRegs-1];
988   else
989     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
990 }
991 
992 void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
993                                         unsigned MatchingIdx, const SDLoc &dl,
994                                         SelectionDAG &DAG,
995                                         std::vector<SDValue> &Ops) const {
996   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
997 
998   InlineAsm::Flag Flag(Code, Regs.size());
999   if (HasMatching)
1000     Flag.setMatchingOp(MatchingIdx);
1001   else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) {
1002     // Put the register class of the virtual registers in the flag word.  That
1003     // way, later passes can recompute register class constraints for inline
1004     // assembly as well as normal instructions.
1005     // Don't do this for tied operands that can use the regclass information
1006     // from the def.
1007     const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1008     const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
1009     Flag.setRegClass(RC->getID());
1010   }
1011 
1012   SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
1013   Ops.push_back(Res);
1014 
1015   if (Code == InlineAsm::Kind::Clobber) {
1016     // Clobbers should always have a 1:1 mapping with registers, and may
1017     // reference registers that have illegal (e.g. vector) types. Hence, we
1018     // shouldn't try to apply any sort of splitting logic to them.
1019     assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&
1020            "No 1:1 mapping from clobbers to regs?");
1021     Register SP = TLI.getStackPointerRegisterToSaveRestore();
1022     (void)SP;
1023     for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
1024       Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
1025       assert(
1026           (Regs[I] != SP ||
1027            DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) &&
1028           "If we clobbered the stack pointer, MFI should know about it.");
1029     }
1030     return;
1031   }
1032 
1033   for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
1034     MVT RegisterVT = RegVTs[Value];
1035     unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value],
1036                                            RegisterVT);
1037     for (unsigned i = 0; i != NumRegs; ++i) {
1038       assert(Reg < Regs.size() && "Mismatch in # registers expected");
1039       unsigned TheReg = Regs[Reg++];
1040       Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
1041     }
1042   }
1043 }
1044 
1045 SmallVector<std::pair<unsigned, TypeSize>, 4>
1046 RegsForValue::getRegsAndSizes() const {
1047   SmallVector<std::pair<unsigned, TypeSize>, 4> OutVec;
1048   unsigned I = 0;
1049   for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
1050     unsigned RegCount = std::get<0>(CountAndVT);
1051     MVT RegisterVT = std::get<1>(CountAndVT);
1052     TypeSize RegisterSize = RegisterVT.getSizeInBits();
1053     for (unsigned E = I + RegCount; I != E; ++I)
1054       OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
1055   }
1056   return OutVec;
1057 }
1058 
1059 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
1060                                AssumptionCache *ac,
1061                                const TargetLibraryInfo *li) {
1062   AA = aa;
1063   AC = ac;
1064   GFI = gfi;
1065   LibInfo = li;
1066   Context = DAG.getContext();
1067   LPadToCallSiteMap.clear();
1068   SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout());
1069   AssignmentTrackingEnabled = isAssignmentTrackingEnabled(
1070       *DAG.getMachineFunction().getFunction().getParent());
1071 }
1072 
1073 void SelectionDAGBuilder::clear() {
1074   NodeMap.clear();
1075   UnusedArgNodeMap.clear();
1076   PendingLoads.clear();
1077   PendingExports.clear();
1078   PendingConstrainedFP.clear();
1079   PendingConstrainedFPStrict.clear();
1080   CurInst = nullptr;
1081   HasTailCall = false;
1082   SDNodeOrder = LowestSDNodeOrder;
1083   StatepointLowering.clear();
1084 }
1085 
1086 void SelectionDAGBuilder::clearDanglingDebugInfo() {
1087   DanglingDebugInfoMap.clear();
1088 }
1089 
1090 // Update DAG root to include dependencies on Pending chains.
1091 SDValue SelectionDAGBuilder::updateRoot(SmallVectorImpl<SDValue> &Pending) {
1092   SDValue Root = DAG.getRoot();
1093 
1094   if (Pending.empty())
1095     return Root;
1096 
1097   // Add current root to PendingChains, unless we already indirectly
1098   // depend on it.
1099   if (Root.getOpcode() != ISD::EntryToken) {
1100     unsigned i = 0, e = Pending.size();
1101     for (; i != e; ++i) {
1102       assert(Pending[i].getNode()->getNumOperands() > 1);
1103       if (Pending[i].getNode()->getOperand(0) == Root)
1104         break;  // Don't add the root if we already indirectly depend on it.
1105     }
1106 
1107     if (i == e)
1108       Pending.push_back(Root);
1109   }
1110 
1111   if (Pending.size() == 1)
1112     Root = Pending[0];
1113   else
1114     Root = DAG.getTokenFactor(getCurSDLoc(), Pending);
1115 
1116   DAG.setRoot(Root);
1117   Pending.clear();
1118   return Root;
1119 }
1120 
1121 SDValue SelectionDAGBuilder::getMemoryRoot() {
1122   return updateRoot(PendingLoads);
1123 }
1124 
1125 SDValue SelectionDAGBuilder::getRoot() {
1126   // Chain up all pending constrained intrinsics together with all
1127   // pending loads, by simply appending them to PendingLoads and
1128   // then calling getMemoryRoot().
1129   PendingLoads.reserve(PendingLoads.size() +
1130                        PendingConstrainedFP.size() +
1131                        PendingConstrainedFPStrict.size());
1132   PendingLoads.append(PendingConstrainedFP.begin(),
1133                       PendingConstrainedFP.end());
1134   PendingLoads.append(PendingConstrainedFPStrict.begin(),
1135                       PendingConstrainedFPStrict.end());
1136   PendingConstrainedFP.clear();
1137   PendingConstrainedFPStrict.clear();
1138   return getMemoryRoot();
1139 }
1140 
1141 SDValue SelectionDAGBuilder::getControlRoot() {
1142   // We need to emit pending fpexcept.strict constrained intrinsics,
1143   // so append them to the PendingExports list.
1144   PendingExports.append(PendingConstrainedFPStrict.begin(),
1145                         PendingConstrainedFPStrict.end());
1146   PendingConstrainedFPStrict.clear();
1147   return updateRoot(PendingExports);
1148 }
1149 
1150 void SelectionDAGBuilder::visit(const Instruction &I) {
1151   // Set up outgoing PHI node register values before emitting the terminator.
1152   if (I.isTerminator()) {
1153     HandlePHINodesInSuccessorBlocks(I.getParent());
1154   }
1155 
1156   // Add SDDbgValue nodes for any var locs here. Do so before updating
1157   // SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}.
1158   if (FunctionVarLocs const *FnVarLocs = DAG.getFunctionVarLocs()) {
1159     // Add SDDbgValue nodes for any var locs here. Do so before updating
1160     // SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}.
1161     for (auto It = FnVarLocs->locs_begin(&I), End = FnVarLocs->locs_end(&I);
1162          It != End; ++It) {
1163       auto *Var = FnVarLocs->getDILocalVariable(It->VariableID);
1164       dropDanglingDebugInfo(Var, It->Expr);
1165       if (It->Values.isKillLocation(It->Expr)) {
1166         handleKillDebugValue(Var, It->Expr, It->DL, SDNodeOrder);
1167         continue;
1168       }
1169       SmallVector<Value *> Values(It->Values.location_ops());
1170       if (!handleDebugValue(Values, Var, It->Expr, It->DL, SDNodeOrder,
1171                             It->Values.hasArgList()))
1172         addDanglingDebugInfo(It, SDNodeOrder);
1173     }
1174   }
1175 
1176   // Increase the SDNodeOrder if dealing with a non-debug instruction.
1177   if (!isa<DbgInfoIntrinsic>(I))
1178     ++SDNodeOrder;
1179 
1180   CurInst = &I;
1181 
1182   // Set inserted listener only if required.
1183   bool NodeInserted = false;
1184   std::unique_ptr<SelectionDAG::DAGNodeInsertedListener> InsertedListener;
1185   MDNode *PCSectionsMD = I.getMetadata(LLVMContext::MD_pcsections);
1186   if (PCSectionsMD) {
1187     InsertedListener = std::make_unique<SelectionDAG::DAGNodeInsertedListener>(
1188         DAG, [&](SDNode *) { NodeInserted = true; });
1189   }
1190 
1191   visit(I.getOpcode(), I);
1192 
1193   if (!I.isTerminator() && !HasTailCall &&
1194       !isa<GCStatepointInst>(I)) // statepoints handle their exports internally
1195     CopyToExportRegsIfNeeded(&I);
1196 
1197   // Handle metadata.
1198   if (PCSectionsMD) {
1199     auto It = NodeMap.find(&I);
1200     if (It != NodeMap.end()) {
1201       DAG.addPCSections(It->second.getNode(), PCSectionsMD);
1202     } else if (NodeInserted) {
1203       // This should not happen; if it does, don't let it go unnoticed so we can
1204       // fix it. Relevant visit*() function is probably missing a setValue().
1205       errs() << "warning: loosing !pcsections metadata ["
1206              << I.getModule()->getName() << "]\n";
1207       LLVM_DEBUG(I.dump());
1208       assert(false);
1209     }
1210   }
1211 
1212   CurInst = nullptr;
1213 }
1214 
1215 void SelectionDAGBuilder::visitPHI(const PHINode &) {
1216   llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
1217 }
1218 
1219 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1220   // Note: this doesn't use InstVisitor, because it has to work with
1221   // ConstantExpr's in addition to instructions.
1222   switch (Opcode) {
1223   default: llvm_unreachable("Unknown instruction type encountered!");
1224     // Build the switch statement using the Instruction.def file.
1225 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1226     case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1227 #include "llvm/IR/Instruction.def"
1228   }
1229 }
1230 
1231 static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG,
1232                                             DILocalVariable *Variable,
1233                                             DebugLoc DL, unsigned Order,
1234                                             RawLocationWrapper Values,
1235                                             DIExpression *Expression) {
1236   if (!Values.hasArgList())
1237     return false;
1238   // For variadic dbg_values we will now insert an undef.
1239   // FIXME: We can potentially recover these!
1240   SmallVector<SDDbgOperand, 2> Locs;
1241   for (const Value *V : Values.location_ops()) {
1242     auto *Undef = UndefValue::get(V->getType());
1243     Locs.push_back(SDDbgOperand::fromConst(Undef));
1244   }
1245   SDDbgValue *SDV = DAG.getDbgValueList(Variable, Expression, Locs, {},
1246                                         /*IsIndirect=*/false, DL, Order,
1247                                         /*IsVariadic=*/true);
1248   DAG.AddDbgValue(SDV, /*isParameter=*/false);
1249   return true;
1250 }
1251 
1252 void SelectionDAGBuilder::addDanglingDebugInfo(const VarLocInfo *VarLoc,
1253                                                unsigned Order) {
1254   if (!handleDanglingVariadicDebugInfo(
1255           DAG,
1256           const_cast<DILocalVariable *>(DAG.getFunctionVarLocs()
1257                                             ->getVariable(VarLoc->VariableID)
1258                                             .getVariable()),
1259           VarLoc->DL, Order, VarLoc->Values, VarLoc->Expr)) {
1260     DanglingDebugInfoMap[VarLoc->Values.getVariableLocationOp(0)].emplace_back(
1261         VarLoc, Order);
1262   }
1263 }
1264 
1265 void SelectionDAGBuilder::addDanglingDebugInfo(const DbgValueInst *DI,
1266                                                unsigned Order) {
1267   // We treat variadic dbg_values differently at this stage.
1268   if (!handleDanglingVariadicDebugInfo(
1269           DAG, DI->getVariable(), DI->getDebugLoc(), Order,
1270           DI->getWrappedLocation(), DI->getExpression())) {
1271     // TODO: Dangling debug info will eventually either be resolved or produce
1272     // an Undef DBG_VALUE. However in the resolution case, a gap may appear
1273     // between the original dbg.value location and its resolved DBG_VALUE,
1274     // which we should ideally fill with an extra Undef DBG_VALUE.
1275     assert(DI->getNumVariableLocationOps() == 1 &&
1276            "DbgValueInst without an ArgList should have a single location "
1277            "operand.");
1278     DanglingDebugInfoMap[DI->getValue(0)].emplace_back(DI, Order);
1279   }
1280 }
1281 
1282 void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable,
1283                                                 const DIExpression *Expr) {
1284   auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1285     DIVariable *DanglingVariable = DDI.getVariable(DAG.getFunctionVarLocs());
1286     DIExpression *DanglingExpr = DDI.getExpression();
1287     if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) {
1288       LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << printDDI(DDI)
1289                         << "\n");
1290       return true;
1291     }
1292     return false;
1293   };
1294 
1295   for (auto &DDIMI : DanglingDebugInfoMap) {
1296     DanglingDebugInfoVector &DDIV = DDIMI.second;
1297 
1298     // If debug info is to be dropped, run it through final checks to see
1299     // whether it can be salvaged.
1300     for (auto &DDI : DDIV)
1301       if (isMatchingDbgValue(DDI))
1302         salvageUnresolvedDbgValue(DDI);
1303 
1304     erase_if(DDIV, isMatchingDbgValue);
1305   }
1306 }
1307 
1308 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1309 // generate the debug data structures now that we've seen its definition.
1310 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1311                                                    SDValue Val) {
1312   auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1313   if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1314     return;
1315 
1316   DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1317   for (auto &DDI : DDIV) {
1318     DebugLoc DL = DDI.getDebugLoc();
1319     unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1320     unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1321     DILocalVariable *Variable = DDI.getVariable(DAG.getFunctionVarLocs());
1322     DIExpression *Expr = DDI.getExpression();
1323     assert(Variable->isValidLocationForIntrinsic(DL) &&
1324            "Expected inlined-at fields to agree");
1325     SDDbgValue *SDV;
1326     if (Val.getNode()) {
1327       // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a
1328       // FuncArgumentDbgValue (it would be hoisted to the function entry, and if
1329       // we couldn't resolve it directly when examining the DbgValue intrinsic
1330       // in the first place we should not be more successful here). Unless we
1331       // have some test case that prove this to be correct we should avoid
1332       // calling EmitFuncArgumentDbgValue here.
1333       if (!EmitFuncArgumentDbgValue(V, Variable, Expr, DL,
1334                                     FuncArgumentDbgValueKind::Value, Val)) {
1335         LLVM_DEBUG(dbgs() << "Resolve dangling debug info for " << printDDI(DDI)
1336                           << "\n");
1337         LLVM_DEBUG(dbgs() << "  By mapping to:\n    "; Val.dump());
1338         // Increase the SDNodeOrder for the DbgValue here to make sure it is
1339         // inserted after the definition of Val when emitting the instructions
1340         // after ISel. An alternative could be to teach
1341         // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1342         LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()
1343                    << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "
1344                    << ValSDNodeOrder << "\n");
1345         SDV = getDbgValue(Val, Variable, Expr, DL,
1346                           std::max(DbgSDNodeOrder, ValSDNodeOrder));
1347         DAG.AddDbgValue(SDV, false);
1348       } else
1349         LLVM_DEBUG(dbgs() << "Resolved dangling debug info for "
1350                           << printDDI(DDI) << " in EmitFuncArgumentDbgValue\n");
1351     } else {
1352       LLVM_DEBUG(dbgs() << "Dropping debug info for " << printDDI(DDI) << "\n");
1353       auto Undef = UndefValue::get(V->getType());
1354       auto SDV =
1355           DAG.getConstantDbgValue(Variable, Expr, Undef, DL, DbgSDNodeOrder);
1356       DAG.AddDbgValue(SDV, false);
1357     }
1358   }
1359   DDIV.clear();
1360 }
1361 
1362 void SelectionDAGBuilder::salvageUnresolvedDbgValue(DanglingDebugInfo &DDI) {
1363   // TODO: For the variadic implementation, instead of only checking the fail
1364   // state of `handleDebugValue`, we need know specifically which values were
1365   // invalid, so that we attempt to salvage only those values when processing
1366   // a DIArgList.
1367   Value *V = DDI.getVariableLocationOp(0);
1368   Value *OrigV = V;
1369   DILocalVariable *Var = DDI.getVariable(DAG.getFunctionVarLocs());
1370   DIExpression *Expr = DDI.getExpression();
1371   DebugLoc DL = DDI.getDebugLoc();
1372   unsigned SDOrder = DDI.getSDNodeOrder();
1373 
1374   // Currently we consider only dbg.value intrinsics -- we tell the salvager
1375   // that DW_OP_stack_value is desired.
1376   bool StackValue = true;
1377 
1378   // Can this Value can be encoded without any further work?
1379   if (handleDebugValue(V, Var, Expr, DL, SDOrder, /*IsVariadic=*/false))
1380     return;
1381 
1382   // Attempt to salvage back through as many instructions as possible. Bail if
1383   // a non-instruction is seen, such as a constant expression or global
1384   // variable. FIXME: Further work could recover those too.
1385   while (isa<Instruction>(V)) {
1386     Instruction &VAsInst = *cast<Instruction>(V);
1387     // Temporary "0", awaiting real implementation.
1388     SmallVector<uint64_t, 16> Ops;
1389     SmallVector<Value *, 4> AdditionalValues;
1390     V = salvageDebugInfoImpl(VAsInst, Expr->getNumLocationOperands(), Ops,
1391                              AdditionalValues);
1392     // If we cannot salvage any further, and haven't yet found a suitable debug
1393     // expression, bail out.
1394     if (!V)
1395       break;
1396 
1397     // TODO: If AdditionalValues isn't empty, then the salvage can only be
1398     // represented with a DBG_VALUE_LIST, so we give up. When we have support
1399     // here for variadic dbg_values, remove that condition.
1400     if (!AdditionalValues.empty())
1401       break;
1402 
1403     // New value and expr now represent this debuginfo.
1404     Expr = DIExpression::appendOpsToArg(Expr, Ops, 0, StackValue);
1405 
1406     // Some kind of simplification occurred: check whether the operand of the
1407     // salvaged debug expression can be encoded in this DAG.
1408     if (handleDebugValue(V, Var, Expr, DL, SDOrder, /*IsVariadic=*/false)) {
1409       LLVM_DEBUG(
1410           dbgs() << "Salvaged debug location info for:\n  " << *Var << "\n"
1411                  << *OrigV << "\nBy stripping back to:\n  " << *V << "\n");
1412       return;
1413     }
1414   }
1415 
1416   // This was the final opportunity to salvage this debug information, and it
1417   // couldn't be done. Place an undef DBG_VALUE at this location to terminate
1418   // any earlier variable location.
1419   assert(OrigV && "V shouldn't be null");
1420   auto *Undef = UndefValue::get(OrigV->getType());
1421   auto *SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder);
1422   DAG.AddDbgValue(SDV, false);
1423   LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n  " << printDDI(DDI)
1424                     << "\n");
1425 }
1426 
1427 void SelectionDAGBuilder::handleKillDebugValue(DILocalVariable *Var,
1428                                                DIExpression *Expr,
1429                                                DebugLoc DbgLoc,
1430                                                unsigned Order) {
1431   Value *Poison = PoisonValue::get(Type::getInt1Ty(*Context));
1432   DIExpression *NewExpr =
1433       const_cast<DIExpression *>(DIExpression::convertToUndefExpression(Expr));
1434   handleDebugValue(Poison, Var, NewExpr, DbgLoc, Order,
1435                    /*IsVariadic*/ false);
1436 }
1437 
1438 bool SelectionDAGBuilder::handleDebugValue(ArrayRef<const Value *> Values,
1439                                            DILocalVariable *Var,
1440                                            DIExpression *Expr, DebugLoc DbgLoc,
1441                                            unsigned Order, bool IsVariadic) {
1442   if (Values.empty())
1443     return true;
1444   SmallVector<SDDbgOperand> LocationOps;
1445   SmallVector<SDNode *> Dependencies;
1446   for (const Value *V : Values) {
1447     // Constant value.
1448     if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1449         isa<ConstantPointerNull>(V)) {
1450       LocationOps.emplace_back(SDDbgOperand::fromConst(V));
1451       continue;
1452     }
1453 
1454     // Look through IntToPtr constants.
1455     if (auto *CE = dyn_cast<ConstantExpr>(V))
1456       if (CE->getOpcode() == Instruction::IntToPtr) {
1457         LocationOps.emplace_back(SDDbgOperand::fromConst(CE->getOperand(0)));
1458         continue;
1459       }
1460 
1461     // If the Value is a frame index, we can create a FrameIndex debug value
1462     // without relying on the DAG at all.
1463     if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1464       auto SI = FuncInfo.StaticAllocaMap.find(AI);
1465       if (SI != FuncInfo.StaticAllocaMap.end()) {
1466         LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(SI->second));
1467         continue;
1468       }
1469     }
1470 
1471     // Do not use getValue() in here; we don't want to generate code at
1472     // this point if it hasn't been done yet.
1473     SDValue N = NodeMap[V];
1474     if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map.
1475       N = UnusedArgNodeMap[V];
1476     if (N.getNode()) {
1477       // Only emit func arg dbg value for non-variadic dbg.values for now.
1478       if (!IsVariadic &&
1479           EmitFuncArgumentDbgValue(V, Var, Expr, DbgLoc,
1480                                    FuncArgumentDbgValueKind::Value, N))
1481         return true;
1482       if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) {
1483         // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can
1484         // describe stack slot locations.
1485         //
1486         // Consider "int x = 0; int *px = &x;". There are two kinds of
1487         // interesting debug values here after optimization:
1488         //
1489         //   dbg.value(i32* %px, !"int *px", !DIExpression()), and
1490         //   dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
1491         //
1492         // Both describe the direct values of their associated variables.
1493         Dependencies.push_back(N.getNode());
1494         LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(FISDN->getIndex()));
1495         continue;
1496       }
1497       LocationOps.emplace_back(
1498           SDDbgOperand::fromNode(N.getNode(), N.getResNo()));
1499       continue;
1500     }
1501 
1502     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1503     // Special rules apply for the first dbg.values of parameter variables in a
1504     // function. Identify them by the fact they reference Argument Values, that
1505     // they're parameters, and they are parameters of the current function. We
1506     // need to let them dangle until they get an SDNode.
1507     bool IsParamOfFunc =
1508         isa<Argument>(V) && Var->isParameter() && !DbgLoc.getInlinedAt();
1509     if (IsParamOfFunc)
1510       return false;
1511 
1512     // The value is not used in this block yet (or it would have an SDNode).
1513     // We still want the value to appear for the user if possible -- if it has
1514     // an associated VReg, we can refer to that instead.
1515     auto VMI = FuncInfo.ValueMap.find(V);
1516     if (VMI != FuncInfo.ValueMap.end()) {
1517       unsigned Reg = VMI->second;
1518       // If this is a PHI node, it may be split up into several MI PHI nodes
1519       // (in FunctionLoweringInfo::set).
1520       RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
1521                        V->getType(), std::nullopt);
1522       if (RFV.occupiesMultipleRegs()) {
1523         // FIXME: We could potentially support variadic dbg_values here.
1524         if (IsVariadic)
1525           return false;
1526         unsigned Offset = 0;
1527         unsigned BitsToDescribe = 0;
1528         if (auto VarSize = Var->getSizeInBits())
1529           BitsToDescribe = *VarSize;
1530         if (auto Fragment = Expr->getFragmentInfo())
1531           BitsToDescribe = Fragment->SizeInBits;
1532         for (const auto &RegAndSize : RFV.getRegsAndSizes()) {
1533           // Bail out if all bits are described already.
1534           if (Offset >= BitsToDescribe)
1535             break;
1536           // TODO: handle scalable vectors.
1537           unsigned RegisterSize = RegAndSize.second;
1538           unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
1539                                       ? BitsToDescribe - Offset
1540                                       : RegisterSize;
1541           auto FragmentExpr = DIExpression::createFragmentExpression(
1542               Expr, Offset, FragmentSize);
1543           if (!FragmentExpr)
1544             continue;
1545           SDDbgValue *SDV = DAG.getVRegDbgValue(
1546               Var, *FragmentExpr, RegAndSize.first, false, DbgLoc, SDNodeOrder);
1547           DAG.AddDbgValue(SDV, false);
1548           Offset += RegisterSize;
1549         }
1550         return true;
1551       }
1552       // We can use simple vreg locations for variadic dbg_values as well.
1553       LocationOps.emplace_back(SDDbgOperand::fromVReg(Reg));
1554       continue;
1555     }
1556     // We failed to create a SDDbgOperand for V.
1557     return false;
1558   }
1559 
1560   // We have created a SDDbgOperand for each Value in Values.
1561   // Should use Order instead of SDNodeOrder?
1562   assert(!LocationOps.empty());
1563   SDDbgValue *SDV = DAG.getDbgValueList(Var, Expr, LocationOps, Dependencies,
1564                                         /*IsIndirect=*/false, DbgLoc,
1565                                         SDNodeOrder, IsVariadic);
1566   DAG.AddDbgValue(SDV, /*isParameter=*/false);
1567   return true;
1568 }
1569 
1570 void SelectionDAGBuilder::resolveOrClearDbgInfo() {
1571   // Try to fixup any remaining dangling debug info -- and drop it if we can't.
1572   for (auto &Pair : DanglingDebugInfoMap)
1573     for (auto &DDI : Pair.second)
1574       salvageUnresolvedDbgValue(DDI);
1575   clearDanglingDebugInfo();
1576 }
1577 
1578 /// getCopyFromRegs - If there was virtual register allocated for the value V
1579 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1580 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1581   DenseMap<const Value *, Register>::iterator It = FuncInfo.ValueMap.find(V);
1582   SDValue Result;
1583 
1584   if (It != FuncInfo.ValueMap.end()) {
1585     Register InReg = It->second;
1586 
1587     RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1588                      DAG.getDataLayout(), InReg, Ty,
1589                      std::nullopt); // This is not an ABI copy.
1590     SDValue Chain = DAG.getEntryNode();
1591     Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
1592                                  V);
1593     resolveDanglingDebugInfo(V, Result);
1594   }
1595 
1596   return Result;
1597 }
1598 
1599 /// getValue - Return an SDValue for the given Value.
1600 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1601   // If we already have an SDValue for this value, use it. It's important
1602   // to do this first, so that we don't create a CopyFromReg if we already
1603   // have a regular SDValue.
1604   SDValue &N = NodeMap[V];
1605   if (N.getNode()) return N;
1606 
1607   // If there's a virtual register allocated and initialized for this
1608   // value, use it.
1609   if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
1610     return copyFromReg;
1611 
1612   // Otherwise create a new SDValue and remember it.
1613   SDValue Val = getValueImpl(V);
1614   NodeMap[V] = Val;
1615   resolveDanglingDebugInfo(V, Val);
1616   return Val;
1617 }
1618 
1619 /// getNonRegisterValue - Return an SDValue for the given Value, but
1620 /// don't look in FuncInfo.ValueMap for a virtual register.
1621 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1622   // If we already have an SDValue for this value, use it.
1623   SDValue &N = NodeMap[V];
1624   if (N.getNode()) {
1625     if (isIntOrFPConstant(N)) {
1626       // Remove the debug location from the node as the node is about to be used
1627       // in a location which may differ from the original debug location.  This
1628       // is relevant to Constant and ConstantFP nodes because they can appear
1629       // as constant expressions inside PHI nodes.
1630       N->setDebugLoc(DebugLoc());
1631     }
1632     return N;
1633   }
1634 
1635   // Otherwise create a new SDValue and remember it.
1636   SDValue Val = getValueImpl(V);
1637   NodeMap[V] = Val;
1638   resolveDanglingDebugInfo(V, Val);
1639   return Val;
1640 }
1641 
1642 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1643 /// Create an SDValue for the given value.
1644 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1645   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1646 
1647   if (const Constant *C = dyn_cast<Constant>(V)) {
1648     EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1649 
1650     if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1651       return DAG.getConstant(*CI, getCurSDLoc(), VT);
1652 
1653     if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1654       return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1655 
1656     if (isa<ConstantPointerNull>(C)) {
1657       unsigned AS = V->getType()->getPointerAddressSpace();
1658       return DAG.getConstant(0, getCurSDLoc(),
1659                              TLI.getPointerTy(DAG.getDataLayout(), AS));
1660     }
1661 
1662     if (match(C, m_VScale()))
1663       return DAG.getVScale(getCurSDLoc(), VT, APInt(VT.getSizeInBits(), 1));
1664 
1665     if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1666       return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1667 
1668     if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1669       return DAG.getUNDEF(VT);
1670 
1671     if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1672       visit(CE->getOpcode(), *CE);
1673       SDValue N1 = NodeMap[V];
1674       assert(N1.getNode() && "visit didn't populate the NodeMap!");
1675       return N1;
1676     }
1677 
1678     if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1679       SmallVector<SDValue, 4> Constants;
1680       for (const Use &U : C->operands()) {
1681         SDNode *Val = getValue(U).getNode();
1682         // If the operand is an empty aggregate, there are no values.
1683         if (!Val) continue;
1684         // Add each leaf value from the operand to the Constants list
1685         // to form a flattened list of all the values.
1686         for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1687           Constants.push_back(SDValue(Val, i));
1688       }
1689 
1690       return DAG.getMergeValues(Constants, getCurSDLoc());
1691     }
1692 
1693     if (const ConstantDataSequential *CDS =
1694           dyn_cast<ConstantDataSequential>(C)) {
1695       SmallVector<SDValue, 4> Ops;
1696       for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1697         SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1698         // Add each leaf value from the operand to the Constants list
1699         // to form a flattened list of all the values.
1700         for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1701           Ops.push_back(SDValue(Val, i));
1702       }
1703 
1704       if (isa<ArrayType>(CDS->getType()))
1705         return DAG.getMergeValues(Ops, getCurSDLoc());
1706       return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1707     }
1708 
1709     if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1710       assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1711              "Unknown struct or array constant!");
1712 
1713       SmallVector<EVT, 4> ValueVTs;
1714       ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1715       unsigned NumElts = ValueVTs.size();
1716       if (NumElts == 0)
1717         return SDValue(); // empty struct
1718       SmallVector<SDValue, 4> Constants(NumElts);
1719       for (unsigned i = 0; i != NumElts; ++i) {
1720         EVT EltVT = ValueVTs[i];
1721         if (isa<UndefValue>(C))
1722           Constants[i] = DAG.getUNDEF(EltVT);
1723         else if (EltVT.isFloatingPoint())
1724           Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1725         else
1726           Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1727       }
1728 
1729       return DAG.getMergeValues(Constants, getCurSDLoc());
1730     }
1731 
1732     if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1733       return DAG.getBlockAddress(BA, VT);
1734 
1735     if (const auto *Equiv = dyn_cast<DSOLocalEquivalent>(C))
1736       return getValue(Equiv->getGlobalValue());
1737 
1738     if (const auto *NC = dyn_cast<NoCFIValue>(C))
1739       return getValue(NC->getGlobalValue());
1740 
1741     if (VT == MVT::aarch64svcount) {
1742       assert(C->isNullValue() && "Can only zero this target type!");
1743       return DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT,
1744                          DAG.getConstant(0, getCurSDLoc(), MVT::nxv16i1));
1745     }
1746 
1747     VectorType *VecTy = cast<VectorType>(V->getType());
1748 
1749     // Now that we know the number and type of the elements, get that number of
1750     // elements into the Ops array based on what kind of constant it is.
1751     if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1752       SmallVector<SDValue, 16> Ops;
1753       unsigned NumElements = cast<FixedVectorType>(VecTy)->getNumElements();
1754       for (unsigned i = 0; i != NumElements; ++i)
1755         Ops.push_back(getValue(CV->getOperand(i)));
1756 
1757       return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1758     }
1759 
1760     if (isa<ConstantAggregateZero>(C)) {
1761       EVT EltVT =
1762           TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1763 
1764       SDValue Op;
1765       if (EltVT.isFloatingPoint())
1766         Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1767       else
1768         Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1769 
1770       return NodeMap[V] = DAG.getSplat(VT, getCurSDLoc(), Op);
1771     }
1772 
1773     llvm_unreachable("Unknown vector constant");
1774   }
1775 
1776   // If this is a static alloca, generate it as the frameindex instead of
1777   // computation.
1778   if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1779     DenseMap<const AllocaInst*, int>::iterator SI =
1780       FuncInfo.StaticAllocaMap.find(AI);
1781     if (SI != FuncInfo.StaticAllocaMap.end())
1782       return DAG.getFrameIndex(
1783           SI->second, TLI.getValueType(DAG.getDataLayout(), AI->getType()));
1784   }
1785 
1786   // If this is an instruction which fast-isel has deferred, select it now.
1787   if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1788     Register InReg = FuncInfo.InitializeRegForValue(Inst);
1789 
1790     RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1791                      Inst->getType(), std::nullopt);
1792     SDValue Chain = DAG.getEntryNode();
1793     return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1794   }
1795 
1796   if (const MetadataAsValue *MD = dyn_cast<MetadataAsValue>(V))
1797     return DAG.getMDNode(cast<MDNode>(MD->getMetadata()));
1798 
1799   if (const auto *BB = dyn_cast<BasicBlock>(V))
1800     return DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
1801 
1802   llvm_unreachable("Can't get register for value!");
1803 }
1804 
1805 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1806   auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1807   bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1808   bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1809   bool IsSEH = isAsynchronousEHPersonality(Pers);
1810   MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1811   if (!IsSEH)
1812     CatchPadMBB->setIsEHScopeEntry();
1813   // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1814   if (IsMSVCCXX || IsCoreCLR)
1815     CatchPadMBB->setIsEHFuncletEntry();
1816 }
1817 
1818 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1819   // Update machine-CFG edge.
1820   MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1821   FuncInfo.MBB->addSuccessor(TargetMBB);
1822   TargetMBB->setIsEHCatchretTarget(true);
1823   DAG.getMachineFunction().setHasEHCatchret(true);
1824 
1825   auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1826   bool IsSEH = isAsynchronousEHPersonality(Pers);
1827   if (IsSEH) {
1828     // If this is not a fall-through branch or optimizations are switched off,
1829     // emit the branch.
1830     if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1831         TM.getOptLevel() == CodeGenOptLevel::None)
1832       DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1833                               getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1834     return;
1835   }
1836 
1837   // Figure out the funclet membership for the catchret's successor.
1838   // This will be used by the FuncletLayout pass to determine how to order the
1839   // BB's.
1840   // A 'catchret' returns to the outer scope's color.
1841   Value *ParentPad = I.getCatchSwitchParentPad();
1842   const BasicBlock *SuccessorColor;
1843   if (isa<ConstantTokenNone>(ParentPad))
1844     SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1845   else
1846     SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1847   assert(SuccessorColor && "No parent funclet for catchret!");
1848   MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1849   assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1850 
1851   // Create the terminator node.
1852   SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1853                             getControlRoot(), DAG.getBasicBlock(TargetMBB),
1854                             DAG.getBasicBlock(SuccessorColorMBB));
1855   DAG.setRoot(Ret);
1856 }
1857 
1858 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1859   // Don't emit any special code for the cleanuppad instruction. It just marks
1860   // the start of an EH scope/funclet.
1861   FuncInfo.MBB->setIsEHScopeEntry();
1862   auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1863   if (Pers != EHPersonality::Wasm_CXX) {
1864     FuncInfo.MBB->setIsEHFuncletEntry();
1865     FuncInfo.MBB->setIsCleanupFuncletEntry();
1866   }
1867 }
1868 
1869 // In wasm EH, even though a catchpad may not catch an exception if a tag does
1870 // not match, it is OK to add only the first unwind destination catchpad to the
1871 // successors, because there will be at least one invoke instruction within the
1872 // catch scope that points to the next unwind destination, if one exists, so
1873 // CFGSort cannot mess up with BB sorting order.
1874 // (All catchpads with 'catch (type)' clauses have a 'llvm.rethrow' intrinsic
1875 // call within them, and catchpads only consisting of 'catch (...)' have a
1876 // '__cxa_end_catch' call within them, both of which generate invokes in case
1877 // the next unwind destination exists, i.e., the next unwind destination is not
1878 // the caller.)
1879 //
1880 // Having at most one EH pad successor is also simpler and helps later
1881 // transformations.
1882 //
1883 // For example,
1884 // current:
1885 //   invoke void @foo to ... unwind label %catch.dispatch
1886 // catch.dispatch:
1887 //   %0 = catchswitch within ... [label %catch.start] unwind label %next
1888 // catch.start:
1889 //   ...
1890 //   ... in this BB or some other child BB dominated by this BB there will be an
1891 //   invoke that points to 'next' BB as an unwind destination
1892 //
1893 // next: ; We don't need to add this to 'current' BB's successor
1894 //   ...
1895 static void findWasmUnwindDestinations(
1896     FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1897     BranchProbability Prob,
1898     SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1899         &UnwindDests) {
1900   while (EHPadBB) {
1901     const Instruction *Pad = EHPadBB->getFirstNonPHI();
1902     if (isa<CleanupPadInst>(Pad)) {
1903       // Stop on cleanup pads.
1904       UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1905       UnwindDests.back().first->setIsEHScopeEntry();
1906       break;
1907     } else if (const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1908       // Add the catchpad handlers to the possible destinations. We don't
1909       // continue to the unwind destination of the catchswitch for wasm.
1910       for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1911         UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1912         UnwindDests.back().first->setIsEHScopeEntry();
1913       }
1914       break;
1915     } else {
1916       continue;
1917     }
1918   }
1919 }
1920 
1921 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1922 /// many places it could ultimately go. In the IR, we have a single unwind
1923 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1924 /// This function skips over imaginary basic blocks that hold catchswitch
1925 /// instructions, and finds all the "real" machine
1926 /// basic block destinations. As those destinations may not be successors of
1927 /// EHPadBB, here we also calculate the edge probability to those destinations.
1928 /// The passed-in Prob is the edge probability to EHPadBB.
1929 static void findUnwindDestinations(
1930     FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1931     BranchProbability Prob,
1932     SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1933         &UnwindDests) {
1934   EHPersonality Personality =
1935     classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1936   bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1937   bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1938   bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
1939   bool IsSEH = isAsynchronousEHPersonality(Personality);
1940 
1941   if (IsWasmCXX) {
1942     findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests);
1943     assert(UnwindDests.size() <= 1 &&
1944            "There should be at most one unwind destination for wasm");
1945     return;
1946   }
1947 
1948   while (EHPadBB) {
1949     const Instruction *Pad = EHPadBB->getFirstNonPHI();
1950     BasicBlock *NewEHPadBB = nullptr;
1951     if (isa<LandingPadInst>(Pad)) {
1952       // Stop on landingpads. They are not funclets.
1953       UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1954       break;
1955     } else if (isa<CleanupPadInst>(Pad)) {
1956       // Stop on cleanup pads. Cleanups are always funclet entries for all known
1957       // personalities.
1958       UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1959       UnwindDests.back().first->setIsEHScopeEntry();
1960       UnwindDests.back().first->setIsEHFuncletEntry();
1961       break;
1962     } else if (const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1963       // Add the catchpad handlers to the possible destinations.
1964       for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1965         UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1966         // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1967         if (IsMSVCCXX || IsCoreCLR)
1968           UnwindDests.back().first->setIsEHFuncletEntry();
1969         if (!IsSEH)
1970           UnwindDests.back().first->setIsEHScopeEntry();
1971       }
1972       NewEHPadBB = CatchSwitch->getUnwindDest();
1973     } else {
1974       continue;
1975     }
1976 
1977     BranchProbabilityInfo *BPI = FuncInfo.BPI;
1978     if (BPI && NewEHPadBB)
1979       Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1980     EHPadBB = NewEHPadBB;
1981   }
1982 }
1983 
1984 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1985   // Update successor info.
1986   SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1987   auto UnwindDest = I.getUnwindDest();
1988   BranchProbabilityInfo *BPI = FuncInfo.BPI;
1989   BranchProbability UnwindDestProb =
1990       (BPI && UnwindDest)
1991           ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1992           : BranchProbability::getZero();
1993   findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1994   for (auto &UnwindDest : UnwindDests) {
1995     UnwindDest.first->setIsEHPad();
1996     addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1997   }
1998   FuncInfo.MBB->normalizeSuccProbs();
1999 
2000   // Create the terminator node.
2001   SDValue Ret =
2002       DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
2003   DAG.setRoot(Ret);
2004 }
2005 
2006 void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
2007   report_fatal_error("visitCatchSwitch not yet implemented!");
2008 }
2009 
2010 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
2011   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2012   auto &DL = DAG.getDataLayout();
2013   SDValue Chain = getControlRoot();
2014   SmallVector<ISD::OutputArg, 8> Outs;
2015   SmallVector<SDValue, 8> OutVals;
2016 
2017   // Calls to @llvm.experimental.deoptimize don't generate a return value, so
2018   // lower
2019   //
2020   //   %val = call <ty> @llvm.experimental.deoptimize()
2021   //   ret <ty> %val
2022   //
2023   // differently.
2024   if (I.getParent()->getTerminatingDeoptimizeCall()) {
2025     LowerDeoptimizingReturn();
2026     return;
2027   }
2028 
2029   if (!FuncInfo.CanLowerReturn) {
2030     unsigned DemoteReg = FuncInfo.DemoteRegister;
2031     const Function *F = I.getParent()->getParent();
2032 
2033     // Emit a store of the return value through the virtual register.
2034     // Leave Outs empty so that LowerReturn won't try to load return
2035     // registers the usual way.
2036     SmallVector<EVT, 1> PtrValueVTs;
2037     ComputeValueVTs(TLI, DL,
2038                     PointerType::get(F->getContext(),
2039                                      DAG.getDataLayout().getAllocaAddrSpace()),
2040                     PtrValueVTs);
2041 
2042     SDValue RetPtr =
2043         DAG.getCopyFromReg(Chain, getCurSDLoc(), DemoteReg, PtrValueVTs[0]);
2044     SDValue RetOp = getValue(I.getOperand(0));
2045 
2046     SmallVector<EVT, 4> ValueVTs, MemVTs;
2047     SmallVector<uint64_t, 4> Offsets;
2048     ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs,
2049                     &Offsets, 0);
2050     unsigned NumValues = ValueVTs.size();
2051 
2052     SmallVector<SDValue, 4> Chains(NumValues);
2053     Align BaseAlign = DL.getPrefTypeAlign(I.getOperand(0)->getType());
2054     for (unsigned i = 0; i != NumValues; ++i) {
2055       // An aggregate return value cannot wrap around the address space, so
2056       // offsets to its parts don't wrap either.
2057       SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr,
2058                                            TypeSize::Fixed(Offsets[i]));
2059 
2060       SDValue Val = RetOp.getValue(RetOp.getResNo() + i);
2061       if (MemVTs[i] != ValueVTs[i])
2062         Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]);
2063       Chains[i] = DAG.getStore(
2064           Chain, getCurSDLoc(), Val,
2065           // FIXME: better loc info would be nice.
2066           Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()),
2067           commonAlignment(BaseAlign, Offsets[i]));
2068     }
2069 
2070     Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
2071                         MVT::Other, Chains);
2072   } else if (I.getNumOperands() != 0) {
2073     SmallVector<EVT, 4> ValueVTs;
2074     ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
2075     unsigned NumValues = ValueVTs.size();
2076     if (NumValues) {
2077       SDValue RetOp = getValue(I.getOperand(0));
2078 
2079       const Function *F = I.getParent()->getParent();
2080 
2081       bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
2082           I.getOperand(0)->getType(), F->getCallingConv(),
2083           /*IsVarArg*/ false, DL);
2084 
2085       ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
2086       if (F->getAttributes().hasRetAttr(Attribute::SExt))
2087         ExtendKind = ISD::SIGN_EXTEND;
2088       else if (F->getAttributes().hasRetAttr(Attribute::ZExt))
2089         ExtendKind = ISD::ZERO_EXTEND;
2090 
2091       LLVMContext &Context = F->getContext();
2092       bool RetInReg = F->getAttributes().hasRetAttr(Attribute::InReg);
2093 
2094       for (unsigned j = 0; j != NumValues; ++j) {
2095         EVT VT = ValueVTs[j];
2096 
2097         if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
2098           VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
2099 
2100         CallingConv::ID CC = F->getCallingConv();
2101 
2102         unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
2103         MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
2104         SmallVector<SDValue, 4> Parts(NumParts);
2105         getCopyToParts(DAG, getCurSDLoc(),
2106                        SDValue(RetOp.getNode(), RetOp.getResNo() + j),
2107                        &Parts[0], NumParts, PartVT, &I, CC, ExtendKind);
2108 
2109         // 'inreg' on function refers to return value
2110         ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2111         if (RetInReg)
2112           Flags.setInReg();
2113 
2114         if (I.getOperand(0)->getType()->isPointerTy()) {
2115           Flags.setPointer();
2116           Flags.setPointerAddrSpace(
2117               cast<PointerType>(I.getOperand(0)->getType())->getAddressSpace());
2118         }
2119 
2120         if (NeedsRegBlock) {
2121           Flags.setInConsecutiveRegs();
2122           if (j == NumValues - 1)
2123             Flags.setInConsecutiveRegsLast();
2124         }
2125 
2126         // Propagate extension type if any
2127         if (ExtendKind == ISD::SIGN_EXTEND)
2128           Flags.setSExt();
2129         else if (ExtendKind == ISD::ZERO_EXTEND)
2130           Flags.setZExt();
2131 
2132         for (unsigned i = 0; i < NumParts; ++i) {
2133           Outs.push_back(ISD::OutputArg(Flags,
2134                                         Parts[i].getValueType().getSimpleVT(),
2135                                         VT, /*isfixed=*/true, 0, 0));
2136           OutVals.push_back(Parts[i]);
2137         }
2138       }
2139     }
2140   }
2141 
2142   // Push in swifterror virtual register as the last element of Outs. This makes
2143   // sure swifterror virtual register will be returned in the swifterror
2144   // physical register.
2145   const Function *F = I.getParent()->getParent();
2146   if (TLI.supportSwiftError() &&
2147       F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
2148     assert(SwiftError.getFunctionArg() && "Need a swift error argument");
2149     ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2150     Flags.setSwiftError();
2151     Outs.push_back(ISD::OutputArg(
2152         Flags, /*vt=*/TLI.getPointerTy(DL), /*argvt=*/EVT(TLI.getPointerTy(DL)),
2153         /*isfixed=*/true, /*origidx=*/1, /*partOffs=*/0));
2154     // Create SDNode for the swifterror virtual register.
2155     OutVals.push_back(
2156         DAG.getRegister(SwiftError.getOrCreateVRegUseAt(
2157                             &I, FuncInfo.MBB, SwiftError.getFunctionArg()),
2158                         EVT(TLI.getPointerTy(DL))));
2159   }
2160 
2161   bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
2162   CallingConv::ID CallConv =
2163     DAG.getMachineFunction().getFunction().getCallingConv();
2164   Chain = DAG.getTargetLoweringInfo().LowerReturn(
2165       Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
2166 
2167   // Verify that the target's LowerReturn behaved as expected.
2168   assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
2169          "LowerReturn didn't return a valid chain!");
2170 
2171   // Update the DAG with the new chain value resulting from return lowering.
2172   DAG.setRoot(Chain);
2173 }
2174 
2175 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
2176 /// created for it, emit nodes to copy the value into the virtual
2177 /// registers.
2178 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
2179   // Skip empty types
2180   if (V->getType()->isEmptyTy())
2181     return;
2182 
2183   DenseMap<const Value *, Register>::iterator VMI = FuncInfo.ValueMap.find(V);
2184   if (VMI != FuncInfo.ValueMap.end()) {
2185     assert((!V->use_empty() || isa<CallBrInst>(V)) &&
2186            "Unused value assigned virtual registers!");
2187     CopyValueToVirtualRegister(V, VMI->second);
2188   }
2189 }
2190 
2191 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
2192 /// the current basic block, add it to ValueMap now so that we'll get a
2193 /// CopyTo/FromReg.
2194 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
2195   // No need to export constants.
2196   if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
2197 
2198   // Already exported?
2199   if (FuncInfo.isExportedInst(V)) return;
2200 
2201   Register Reg = FuncInfo.InitializeRegForValue(V);
2202   CopyValueToVirtualRegister(V, Reg);
2203 }
2204 
2205 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
2206                                                      const BasicBlock *FromBB) {
2207   // The operands of the setcc have to be in this block.  We don't know
2208   // how to export them from some other block.
2209   if (const Instruction *VI = dyn_cast<Instruction>(V)) {
2210     // Can export from current BB.
2211     if (VI->getParent() == FromBB)
2212       return true;
2213 
2214     // Is already exported, noop.
2215     return FuncInfo.isExportedInst(V);
2216   }
2217 
2218   // If this is an argument, we can export it if the BB is the entry block or
2219   // if it is already exported.
2220   if (isa<Argument>(V)) {
2221     if (FromBB->isEntryBlock())
2222       return true;
2223 
2224     // Otherwise, can only export this if it is already exported.
2225     return FuncInfo.isExportedInst(V);
2226   }
2227 
2228   // Otherwise, constants can always be exported.
2229   return true;
2230 }
2231 
2232 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
2233 BranchProbability
2234 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
2235                                         const MachineBasicBlock *Dst) const {
2236   BranchProbabilityInfo *BPI = FuncInfo.BPI;
2237   const BasicBlock *SrcBB = Src->getBasicBlock();
2238   const BasicBlock *DstBB = Dst->getBasicBlock();
2239   if (!BPI) {
2240     // If BPI is not available, set the default probability as 1 / N, where N is
2241     // the number of successors.
2242     auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
2243     return BranchProbability(1, SuccSize);
2244   }
2245   return BPI->getEdgeProbability(SrcBB, DstBB);
2246 }
2247 
2248 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
2249                                                MachineBasicBlock *Dst,
2250                                                BranchProbability Prob) {
2251   if (!FuncInfo.BPI)
2252     Src->addSuccessorWithoutProb(Dst);
2253   else {
2254     if (Prob.isUnknown())
2255       Prob = getEdgeProbability(Src, Dst);
2256     Src->addSuccessor(Dst, Prob);
2257   }
2258 }
2259 
2260 static bool InBlock(const Value *V, const BasicBlock *BB) {
2261   if (const Instruction *I = dyn_cast<Instruction>(V))
2262     return I->getParent() == BB;
2263   return true;
2264 }
2265 
2266 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
2267 /// This function emits a branch and is used at the leaves of an OR or an
2268 /// AND operator tree.
2269 void
2270 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
2271                                                   MachineBasicBlock *TBB,
2272                                                   MachineBasicBlock *FBB,
2273                                                   MachineBasicBlock *CurBB,
2274                                                   MachineBasicBlock *SwitchBB,
2275                                                   BranchProbability TProb,
2276                                                   BranchProbability FProb,
2277                                                   bool InvertCond) {
2278   const BasicBlock *BB = CurBB->getBasicBlock();
2279 
2280   // If the leaf of the tree is a comparison, merge the condition into
2281   // the caseblock.
2282   if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
2283     // The operands of the cmp have to be in this block.  We don't know
2284     // how to export them from some other block.  If this is the first block
2285     // of the sequence, no exporting is needed.
2286     if (CurBB == SwitchBB ||
2287         (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
2288          isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
2289       ISD::CondCode Condition;
2290       if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
2291         ICmpInst::Predicate Pred =
2292             InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2293         Condition = getICmpCondCode(Pred);
2294       } else {
2295         const FCmpInst *FC = cast<FCmpInst>(Cond);
2296         FCmpInst::Predicate Pred =
2297             InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2298         Condition = getFCmpCondCode(Pred);
2299         if (TM.Options.NoNaNsFPMath)
2300           Condition = getFCmpCodeWithoutNaN(Condition);
2301       }
2302 
2303       CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
2304                    TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2305       SL->SwitchCases.push_back(CB);
2306       return;
2307     }
2308   }
2309 
2310   // Create a CaseBlock record representing this branch.
2311   ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2312   CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()),
2313                nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2314   SL->SwitchCases.push_back(CB);
2315 }
2316 
2317 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
2318                                                MachineBasicBlock *TBB,
2319                                                MachineBasicBlock *FBB,
2320                                                MachineBasicBlock *CurBB,
2321                                                MachineBasicBlock *SwitchBB,
2322                                                Instruction::BinaryOps Opc,
2323                                                BranchProbability TProb,
2324                                                BranchProbability FProb,
2325                                                bool InvertCond) {
2326   // Skip over not part of the tree and remember to invert op and operands at
2327   // next level.
2328   Value *NotCond;
2329   if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) &&
2330       InBlock(NotCond, CurBB->getBasicBlock())) {
2331     FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
2332                          !InvertCond);
2333     return;
2334   }
2335 
2336   const Instruction *BOp = dyn_cast<Instruction>(Cond);
2337   const Value *BOpOp0, *BOpOp1;
2338   // Compute the effective opcode for Cond, taking into account whether it needs
2339   // to be inverted, e.g.
2340   //   and (not (or A, B)), C
2341   // gets lowered as
2342   //   and (and (not A, not B), C)
2343   Instruction::BinaryOps BOpc = (Instruction::BinaryOps)0;
2344   if (BOp) {
2345     BOpc = match(BOp, m_LogicalAnd(m_Value(BOpOp0), m_Value(BOpOp1)))
2346                ? Instruction::And
2347                : (match(BOp, m_LogicalOr(m_Value(BOpOp0), m_Value(BOpOp1)))
2348                       ? Instruction::Or
2349                       : (Instruction::BinaryOps)0);
2350     if (InvertCond) {
2351       if (BOpc == Instruction::And)
2352         BOpc = Instruction::Or;
2353       else if (BOpc == Instruction::Or)
2354         BOpc = Instruction::And;
2355     }
2356   }
2357 
2358   // If this node is not part of the or/and tree, emit it as a branch.
2359   // Note that all nodes in the tree should have same opcode.
2360   bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse();
2361   if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() ||
2362       !InBlock(BOpOp0, CurBB->getBasicBlock()) ||
2363       !InBlock(BOpOp1, CurBB->getBasicBlock())) {
2364     EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
2365                                  TProb, FProb, InvertCond);
2366     return;
2367   }
2368 
2369   //  Create TmpBB after CurBB.
2370   MachineFunction::iterator BBI(CurBB);
2371   MachineFunction &MF = DAG.getMachineFunction();
2372   MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
2373   CurBB->getParent()->insert(++BBI, TmpBB);
2374 
2375   if (Opc == Instruction::Or) {
2376     // Codegen X | Y as:
2377     // BB1:
2378     //   jmp_if_X TBB
2379     //   jmp TmpBB
2380     // TmpBB:
2381     //   jmp_if_Y TBB
2382     //   jmp FBB
2383     //
2384 
2385     // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2386     // The requirement is that
2387     //   TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
2388     //     = TrueProb for original BB.
2389     // Assuming the original probabilities are A and B, one choice is to set
2390     // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
2391     // A/(1+B) and 2B/(1+B). This choice assumes that
2392     //   TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
2393     // Another choice is to assume TrueProb for BB1 equals to TrueProb for
2394     // TmpBB, but the math is more complicated.
2395 
2396     auto NewTrueProb = TProb / 2;
2397     auto NewFalseProb = TProb / 2 + FProb;
2398     // Emit the LHS condition.
2399     FindMergedConditions(BOpOp0, TBB, TmpBB, CurBB, SwitchBB, Opc, NewTrueProb,
2400                          NewFalseProb, InvertCond);
2401 
2402     // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
2403     SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
2404     BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2405     // Emit the RHS condition into TmpBB.
2406     FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0],
2407                          Probs[1], InvertCond);
2408   } else {
2409     assert(Opc == Instruction::And && "Unknown merge op!");
2410     // Codegen X & Y as:
2411     // BB1:
2412     //   jmp_if_X TmpBB
2413     //   jmp FBB
2414     // TmpBB:
2415     //   jmp_if_Y TBB
2416     //   jmp FBB
2417     //
2418     //  This requires creation of TmpBB after CurBB.
2419 
2420     // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2421     // The requirement is that
2422     //   FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
2423     //     = FalseProb for original BB.
2424     // Assuming the original probabilities are A and B, one choice is to set
2425     // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
2426     // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
2427     // TrueProb for BB1 * FalseProb for TmpBB.
2428 
2429     auto NewTrueProb = TProb + FProb / 2;
2430     auto NewFalseProb = FProb / 2;
2431     // Emit the LHS condition.
2432     FindMergedConditions(BOpOp0, TmpBB, FBB, CurBB, SwitchBB, Opc, NewTrueProb,
2433                          NewFalseProb, InvertCond);
2434 
2435     // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
2436     SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
2437     BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2438     // Emit the RHS condition into TmpBB.
2439     FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0],
2440                          Probs[1], InvertCond);
2441   }
2442 }
2443 
2444 /// If the set of cases should be emitted as a series of branches, return true.
2445 /// If we should emit this as a bunch of and/or'd together conditions, return
2446 /// false.
2447 bool
2448 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
2449   if (Cases.size() != 2) return true;
2450 
2451   // If this is two comparisons of the same values or'd or and'd together, they
2452   // will get folded into a single comparison, so don't emit two blocks.
2453   if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2454        Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2455       (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2456        Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2457     return false;
2458   }
2459 
2460   // Handle: (X != null) | (Y != null) --> (X|Y) != 0
2461   // Handle: (X == null) & (Y == null) --> (X|Y) == 0
2462   if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2463       Cases[0].CC == Cases[1].CC &&
2464       isa<Constant>(Cases[0].CmpRHS) &&
2465       cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2466     if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2467       return false;
2468     if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2469       return false;
2470   }
2471 
2472   return true;
2473 }
2474 
2475 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
2476   MachineBasicBlock *BrMBB = FuncInfo.MBB;
2477 
2478   // Update machine-CFG edges.
2479   MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
2480 
2481   if (I.isUnconditional()) {
2482     // Update machine-CFG edges.
2483     BrMBB->addSuccessor(Succ0MBB);
2484 
2485     // If this is not a fall-through branch or optimizations are switched off,
2486     // emit the branch.
2487     if (Succ0MBB != NextBlock(BrMBB) ||
2488         TM.getOptLevel() == CodeGenOptLevel::None) {
2489       auto Br = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2490                             getControlRoot(), DAG.getBasicBlock(Succ0MBB));
2491       setValue(&I, Br);
2492       DAG.setRoot(Br);
2493     }
2494 
2495     return;
2496   }
2497 
2498   // If this condition is one of the special cases we handle, do special stuff
2499   // now.
2500   const Value *CondVal = I.getCondition();
2501   MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
2502 
2503   // If this is a series of conditions that are or'd or and'd together, emit
2504   // this as a sequence of branches instead of setcc's with and/or operations.
2505   // As long as jumps are not expensive (exceptions for multi-use logic ops,
2506   // unpredictable branches, and vector extracts because those jumps are likely
2507   // expensive for any target), this should improve performance.
2508   // For example, instead of something like:
2509   //     cmp A, B
2510   //     C = seteq
2511   //     cmp D, E
2512   //     F = setle
2513   //     or C, F
2514   //     jnz foo
2515   // Emit:
2516   //     cmp A, B
2517   //     je foo
2518   //     cmp D, E
2519   //     jle foo
2520   const Instruction *BOp = dyn_cast<Instruction>(CondVal);
2521   if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp &&
2522       BOp->hasOneUse() && !I.hasMetadata(LLVMContext::MD_unpredictable)) {
2523     Value *Vec;
2524     const Value *BOp0, *BOp1;
2525     Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0;
2526     if (match(BOp, m_LogicalAnd(m_Value(BOp0), m_Value(BOp1))))
2527       Opcode = Instruction::And;
2528     else if (match(BOp, m_LogicalOr(m_Value(BOp0), m_Value(BOp1))))
2529       Opcode = Instruction::Or;
2530 
2531     if (Opcode && !(match(BOp0, m_ExtractElt(m_Value(Vec), m_Value())) &&
2532                     match(BOp1, m_ExtractElt(m_Specific(Vec), m_Value())))) {
2533       FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, Opcode,
2534                            getEdgeProbability(BrMBB, Succ0MBB),
2535                            getEdgeProbability(BrMBB, Succ1MBB),
2536                            /*InvertCond=*/false);
2537       // If the compares in later blocks need to use values not currently
2538       // exported from this block, export them now.  This block should always
2539       // be the first entry.
2540       assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
2541 
2542       // Allow some cases to be rejected.
2543       if (ShouldEmitAsBranches(SL->SwitchCases)) {
2544         for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) {
2545           ExportFromCurrentBlock(SL->SwitchCases[i].CmpLHS);
2546           ExportFromCurrentBlock(SL->SwitchCases[i].CmpRHS);
2547         }
2548 
2549         // Emit the branch for this block.
2550         visitSwitchCase(SL->SwitchCases[0], BrMBB);
2551         SL->SwitchCases.erase(SL->SwitchCases.begin());
2552         return;
2553       }
2554 
2555       // Okay, we decided not to do this, remove any inserted MBB's and clear
2556       // SwitchCases.
2557       for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i)
2558         FuncInfo.MF->erase(SL->SwitchCases[i].ThisBB);
2559 
2560       SL->SwitchCases.clear();
2561     }
2562   }
2563 
2564   // Create a CaseBlock record representing this branch.
2565   CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2566                nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc());
2567 
2568   // Use visitSwitchCase to actually insert the fast branch sequence for this
2569   // cond branch.
2570   visitSwitchCase(CB, BrMBB);
2571 }
2572 
2573 /// visitSwitchCase - Emits the necessary code to represent a single node in
2574 /// the binary search tree resulting from lowering a switch instruction.
2575 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
2576                                           MachineBasicBlock *SwitchBB) {
2577   SDValue Cond;
2578   SDValue CondLHS = getValue(CB.CmpLHS);
2579   SDLoc dl = CB.DL;
2580 
2581   if (CB.CC == ISD::SETTRUE) {
2582     // Branch or fall through to TrueBB.
2583     addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2584     SwitchBB->normalizeSuccProbs();
2585     if (CB.TrueBB != NextBlock(SwitchBB)) {
2586       DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(),
2587                               DAG.getBasicBlock(CB.TrueBB)));
2588     }
2589     return;
2590   }
2591 
2592   auto &TLI = DAG.getTargetLoweringInfo();
2593   EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType());
2594 
2595   // Build the setcc now.
2596   if (!CB.CmpMHS) {
2597     // Fold "(X == true)" to X and "(X == false)" to !X to
2598     // handle common cases produced by branch lowering.
2599     if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
2600         CB.CC == ISD::SETEQ)
2601       Cond = CondLHS;
2602     else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
2603              CB.CC == ISD::SETEQ) {
2604       SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
2605       Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
2606     } else {
2607       SDValue CondRHS = getValue(CB.CmpRHS);
2608 
2609       // If a pointer's DAG type is larger than its memory type then the DAG
2610       // values are zero-extended. This breaks signed comparisons so truncate
2611       // back to the underlying type before doing the compare.
2612       if (CondLHS.getValueType() != MemVT) {
2613         CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT);
2614         CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT);
2615       }
2616       Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC);
2617     }
2618   } else {
2619     assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
2620 
2621     const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
2622     const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
2623 
2624     SDValue CmpOp = getValue(CB.CmpMHS);
2625     EVT VT = CmpOp.getValueType();
2626 
2627     if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
2628       Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2629                           ISD::SETLE);
2630     } else {
2631       SDValue SUB = DAG.getNode(ISD::SUB, dl,
2632                                 VT, CmpOp, DAG.getConstant(Low, dl, VT));
2633       Cond = DAG.getSetCC(dl, MVT::i1, SUB,
2634                           DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
2635     }
2636   }
2637 
2638   // Update successor info
2639   addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2640   // TrueBB and FalseBB are always different unless the incoming IR is
2641   // degenerate. This only happens when running llc on weird IR.
2642   if (CB.TrueBB != CB.FalseBB)
2643     addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
2644   SwitchBB->normalizeSuccProbs();
2645 
2646   // If the lhs block is the next block, invert the condition so that we can
2647   // fall through to the lhs instead of the rhs block.
2648   if (CB.TrueBB == NextBlock(SwitchBB)) {
2649     std::swap(CB.TrueBB, CB.FalseBB);
2650     SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
2651     Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
2652   }
2653 
2654   SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2655                                MVT::Other, getControlRoot(), Cond,
2656                                DAG.getBasicBlock(CB.TrueBB));
2657 
2658   setValue(CurInst, BrCond);
2659 
2660   // Insert the false branch. Do this even if it's a fall through branch,
2661   // this makes it easier to do DAG optimizations which require inverting
2662   // the branch condition.
2663   BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2664                        DAG.getBasicBlock(CB.FalseBB));
2665 
2666   DAG.setRoot(BrCond);
2667 }
2668 
2669 /// visitJumpTable - Emit JumpTable node in the current MBB
2670 void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) {
2671   // Emit the code for the jump table
2672   assert(JT.Reg != -1U && "Should lower JT Header first!");
2673   EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2674   SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
2675                                      JT.Reg, PTy);
2676   SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
2677   SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
2678                                     MVT::Other, Index.getValue(1),
2679                                     Table, Index);
2680   DAG.setRoot(BrJumpTable);
2681 }
2682 
2683 /// visitJumpTableHeader - This function emits necessary code to produce index
2684 /// in the JumpTable from switch case.
2685 void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT,
2686                                                JumpTableHeader &JTH,
2687                                                MachineBasicBlock *SwitchBB) {
2688   SDLoc dl = getCurSDLoc();
2689 
2690   // Subtract the lowest switch case value from the value being switched on.
2691   SDValue SwitchOp = getValue(JTH.SValue);
2692   EVT VT = SwitchOp.getValueType();
2693   SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2694                             DAG.getConstant(JTH.First, dl, VT));
2695 
2696   // The SDNode we just created, which holds the value being switched on minus
2697   // the smallest case value, needs to be copied to a virtual register so it
2698   // can be used as an index into the jump table in a subsequent basic block.
2699   // This value may be smaller or larger than the target's pointer type, and
2700   // therefore require extension or truncating.
2701   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2702   SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
2703 
2704   unsigned JumpTableReg =
2705       FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
2706   SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
2707                                     JumpTableReg, SwitchOp);
2708   JT.Reg = JumpTableReg;
2709 
2710   if (!JTH.FallthroughUnreachable) {
2711     // Emit the range check for the jump table, and branch to the default block
2712     // for the switch statement if the value being switched on exceeds the
2713     // largest case in the switch.
2714     SDValue CMP = DAG.getSetCC(
2715         dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2716                                    Sub.getValueType()),
2717         Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
2718 
2719     SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2720                                  MVT::Other, CopyTo, CMP,
2721                                  DAG.getBasicBlock(JT.Default));
2722 
2723     // Avoid emitting unnecessary branches to the next block.
2724     if (JT.MBB != NextBlock(SwitchBB))
2725       BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2726                            DAG.getBasicBlock(JT.MBB));
2727 
2728     DAG.setRoot(BrCond);
2729   } else {
2730     // Avoid emitting unnecessary branches to the next block.
2731     if (JT.MBB != NextBlock(SwitchBB))
2732       DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo,
2733                               DAG.getBasicBlock(JT.MBB)));
2734     else
2735       DAG.setRoot(CopyTo);
2736   }
2737 }
2738 
2739 /// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
2740 /// variable if there exists one.
2741 static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
2742                                  SDValue &Chain) {
2743   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2744   EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2745   EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2746   MachineFunction &MF = DAG.getMachineFunction();
2747   Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent());
2748   MachineSDNode *Node =
2749       DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
2750   if (Global) {
2751     MachinePointerInfo MPInfo(Global);
2752     auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
2753                  MachineMemOperand::MODereferenceable;
2754     MachineMemOperand *MemRef = MF.getMachineMemOperand(
2755         MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlign(PtrTy));
2756     DAG.setNodeMemRefs(Node, {MemRef});
2757   }
2758   if (PtrTy != PtrMemTy)
2759     return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy);
2760   return SDValue(Node, 0);
2761 }
2762 
2763 /// Codegen a new tail for a stack protector check ParentMBB which has had its
2764 /// tail spliced into a stack protector check success bb.
2765 ///
2766 /// For a high level explanation of how this fits into the stack protector
2767 /// generation see the comment on the declaration of class
2768 /// StackProtectorDescriptor.
2769 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
2770                                                   MachineBasicBlock *ParentBB) {
2771 
2772   // First create the loads to the guard/stack slot for the comparison.
2773   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2774   EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2775   EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2776 
2777   MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2778   int FI = MFI.getStackProtectorIndex();
2779 
2780   SDValue Guard;
2781   SDLoc dl = getCurSDLoc();
2782   SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2783   const Module &M = *ParentBB->getParent()->getFunction().getParent();
2784   Align Align =
2785       DAG.getDataLayout().getPrefTypeAlign(PointerType::get(M.getContext(), 0));
2786 
2787   // Generate code to load the content of the guard slot.
2788   SDValue GuardVal = DAG.getLoad(
2789       PtrMemTy, dl, DAG.getEntryNode(), StackSlotPtr,
2790       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
2791       MachineMemOperand::MOVolatile);
2792 
2793   if (TLI.useStackGuardXorFP())
2794     GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
2795 
2796   // Retrieve guard check function, nullptr if instrumentation is inlined.
2797   if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) {
2798     // The target provides a guard check function to validate the guard value.
2799     // Generate a call to that function with the content of the guard slot as
2800     // argument.
2801     FunctionType *FnTy = GuardCheckFn->getFunctionType();
2802     assert(FnTy->getNumParams() == 1 && "Invalid function signature");
2803 
2804     TargetLowering::ArgListTy Args;
2805     TargetLowering::ArgListEntry Entry;
2806     Entry.Node = GuardVal;
2807     Entry.Ty = FnTy->getParamType(0);
2808     if (GuardCheckFn->hasParamAttribute(0, Attribute::AttrKind::InReg))
2809       Entry.IsInReg = true;
2810     Args.push_back(Entry);
2811 
2812     TargetLowering::CallLoweringInfo CLI(DAG);
2813     CLI.setDebugLoc(getCurSDLoc())
2814         .setChain(DAG.getEntryNode())
2815         .setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(),
2816                    getValue(GuardCheckFn), std::move(Args));
2817 
2818     std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2819     DAG.setRoot(Result.second);
2820     return;
2821   }
2822 
2823   // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2824   // Otherwise, emit a volatile load to retrieve the stack guard value.
2825   SDValue Chain = DAG.getEntryNode();
2826   if (TLI.useLoadStackGuardNode()) {
2827     Guard = getLoadStackGuard(DAG, dl, Chain);
2828   } else {
2829     const Value *IRGuard = TLI.getSDagStackGuard(M);
2830     SDValue GuardPtr = getValue(IRGuard);
2831 
2832     Guard = DAG.getLoad(PtrMemTy, dl, Chain, GuardPtr,
2833                         MachinePointerInfo(IRGuard, 0), Align,
2834                         MachineMemOperand::MOVolatile);
2835   }
2836 
2837   // Perform the comparison via a getsetcc.
2838   SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2839                                                         *DAG.getContext(),
2840                                                         Guard.getValueType()),
2841                              Guard, GuardVal, ISD::SETNE);
2842 
2843   // If the guard/stackslot do not equal, branch to failure MBB.
2844   SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2845                                MVT::Other, GuardVal.getOperand(0),
2846                                Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2847   // Otherwise branch to success MBB.
2848   SDValue Br = DAG.getNode(ISD::BR, dl,
2849                            MVT::Other, BrCond,
2850                            DAG.getBasicBlock(SPD.getSuccessMBB()));
2851 
2852   DAG.setRoot(Br);
2853 }
2854 
2855 /// Codegen the failure basic block for a stack protector check.
2856 ///
2857 /// A failure stack protector machine basic block consists simply of a call to
2858 /// __stack_chk_fail().
2859 ///
2860 /// For a high level explanation of how this fits into the stack protector
2861 /// generation see the comment on the declaration of class
2862 /// StackProtectorDescriptor.
2863 void
2864 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2865   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2866   TargetLowering::MakeLibCallOptions CallOptions;
2867   CallOptions.setDiscardResult(true);
2868   SDValue Chain =
2869       TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2870                       std::nullopt, CallOptions, getCurSDLoc())
2871           .second;
2872   // On PS4/PS5, the "return address" must still be within the calling
2873   // function, even if it's at the very end, so emit an explicit TRAP here.
2874   // Passing 'true' for doesNotReturn above won't generate the trap for us.
2875   if (TM.getTargetTriple().isPS())
2876     Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2877   // WebAssembly needs an unreachable instruction after a non-returning call,
2878   // because the function return type can be different from __stack_chk_fail's
2879   // return type (void).
2880   if (TM.getTargetTriple().isWasm())
2881     Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2882 
2883   DAG.setRoot(Chain);
2884 }
2885 
2886 /// visitBitTestHeader - This function emits necessary code to produce value
2887 /// suitable for "bit tests"
2888 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2889                                              MachineBasicBlock *SwitchBB) {
2890   SDLoc dl = getCurSDLoc();
2891 
2892   // Subtract the minimum value.
2893   SDValue SwitchOp = getValue(B.SValue);
2894   EVT VT = SwitchOp.getValueType();
2895   SDValue RangeSub =
2896       DAG.getNode(ISD::SUB, dl, VT, SwitchOp, DAG.getConstant(B.First, dl, VT));
2897 
2898   // Determine the type of the test operands.
2899   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2900   bool UsePtrType = false;
2901   if (!TLI.isTypeLegal(VT)) {
2902     UsePtrType = true;
2903   } else {
2904     for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2905       if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2906         // Switch table case range are encoded into series of masks.
2907         // Just use pointer type, it's guaranteed to fit.
2908         UsePtrType = true;
2909         break;
2910       }
2911   }
2912   SDValue Sub = RangeSub;
2913   if (UsePtrType) {
2914     VT = TLI.getPointerTy(DAG.getDataLayout());
2915     Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2916   }
2917 
2918   B.RegVT = VT.getSimpleVT();
2919   B.Reg = FuncInfo.CreateReg(B.RegVT);
2920   SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2921 
2922   MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2923 
2924   if (!B.FallthroughUnreachable)
2925     addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2926   addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2927   SwitchBB->normalizeSuccProbs();
2928 
2929   SDValue Root = CopyTo;
2930   if (!B.FallthroughUnreachable) {
2931     // Conditional branch to the default block.
2932     SDValue RangeCmp = DAG.getSetCC(dl,
2933         TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2934                                RangeSub.getValueType()),
2935         RangeSub, DAG.getConstant(B.Range, dl, RangeSub.getValueType()),
2936         ISD::SETUGT);
2937 
2938     Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp,
2939                        DAG.getBasicBlock(B.Default));
2940   }
2941 
2942   // Avoid emitting unnecessary branches to the next block.
2943   if (MBB != NextBlock(SwitchBB))
2944     Root = DAG.getNode(ISD::BR, dl, MVT::Other, Root, DAG.getBasicBlock(MBB));
2945 
2946   DAG.setRoot(Root);
2947 }
2948 
2949 /// visitBitTestCase - this function produces one "bit test"
2950 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2951                                            MachineBasicBlock* NextMBB,
2952                                            BranchProbability BranchProbToNext,
2953                                            unsigned Reg,
2954                                            BitTestCase &B,
2955                                            MachineBasicBlock *SwitchBB) {
2956   SDLoc dl = getCurSDLoc();
2957   MVT VT = BB.RegVT;
2958   SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2959   SDValue Cmp;
2960   unsigned PopCount = llvm::popcount(B.Mask);
2961   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2962   if (PopCount == 1) {
2963     // Testing for a single bit; just compare the shift count with what it
2964     // would need to be to shift a 1 bit in that position.
2965     Cmp = DAG.getSetCC(
2966         dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2967         ShiftOp, DAG.getConstant(llvm::countr_zero(B.Mask), dl, VT),
2968         ISD::SETEQ);
2969   } else if (PopCount == BB.Range) {
2970     // There is only one zero bit in the range, test for it directly.
2971     Cmp = DAG.getSetCC(
2972         dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2973         ShiftOp, DAG.getConstant(llvm::countr_one(B.Mask), dl, VT), ISD::SETNE);
2974   } else {
2975     // Make desired shift
2976     SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2977                                     DAG.getConstant(1, dl, VT), ShiftOp);
2978 
2979     // Emit bit tests and jumps
2980     SDValue AndOp = DAG.getNode(ISD::AND, dl,
2981                                 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2982     Cmp = DAG.getSetCC(
2983         dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2984         AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2985   }
2986 
2987   // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2988   addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2989   // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2990   addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2991   // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2992   // one as they are relative probabilities (and thus work more like weights),
2993   // and hence we need to normalize them to let the sum of them become one.
2994   SwitchBB->normalizeSuccProbs();
2995 
2996   SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2997                               MVT::Other, getControlRoot(),
2998                               Cmp, DAG.getBasicBlock(B.TargetBB));
2999 
3000   // Avoid emitting unnecessary branches to the next block.
3001   if (NextMBB != NextBlock(SwitchBB))
3002     BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
3003                         DAG.getBasicBlock(NextMBB));
3004 
3005   DAG.setRoot(BrAnd);
3006 }
3007 
3008 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
3009   MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
3010 
3011   // Retrieve successors. Look through artificial IR level blocks like
3012   // catchswitch for successors.
3013   MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
3014   const BasicBlock *EHPadBB = I.getSuccessor(1);
3015   MachineBasicBlock *EHPadMBB = FuncInfo.MBBMap[EHPadBB];
3016 
3017   // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
3018   // have to do anything here to lower funclet bundles.
3019   assert(!I.hasOperandBundlesOtherThan(
3020              {LLVMContext::OB_deopt, LLVMContext::OB_gc_transition,
3021               LLVMContext::OB_gc_live, LLVMContext::OB_funclet,
3022               LLVMContext::OB_cfguardtarget,
3023               LLVMContext::OB_clang_arc_attachedcall}) &&
3024          "Cannot lower invokes with arbitrary operand bundles yet!");
3025 
3026   const Value *Callee(I.getCalledOperand());
3027   const Function *Fn = dyn_cast<Function>(Callee);
3028   if (isa<InlineAsm>(Callee))
3029     visitInlineAsm(I, EHPadBB);
3030   else if (Fn && Fn->isIntrinsic()) {
3031     switch (Fn->getIntrinsicID()) {
3032     default:
3033       llvm_unreachable("Cannot invoke this intrinsic");
3034     case Intrinsic::donothing:
3035       // Ignore invokes to @llvm.donothing: jump directly to the next BB.
3036     case Intrinsic::seh_try_begin:
3037     case Intrinsic::seh_scope_begin:
3038     case Intrinsic::seh_try_end:
3039     case Intrinsic::seh_scope_end:
3040       if (EHPadMBB)
3041           // a block referenced by EH table
3042           // so dtor-funclet not removed by opts
3043           EHPadMBB->setMachineBlockAddressTaken();
3044       break;
3045     case Intrinsic::experimental_patchpoint_void:
3046     case Intrinsic::experimental_patchpoint_i64:
3047       visitPatchpoint(I, EHPadBB);
3048       break;
3049     case Intrinsic::experimental_gc_statepoint:
3050       LowerStatepoint(cast<GCStatepointInst>(I), EHPadBB);
3051       break;
3052     case Intrinsic::wasm_rethrow: {
3053       // This is usually done in visitTargetIntrinsic, but this intrinsic is
3054       // special because it can be invoked, so we manually lower it to a DAG
3055       // node here.
3056       SmallVector<SDValue, 8> Ops;
3057       Ops.push_back(getRoot()); // inchain
3058       const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3059       Ops.push_back(
3060           DAG.getTargetConstant(Intrinsic::wasm_rethrow, getCurSDLoc(),
3061                                 TLI.getPointerTy(DAG.getDataLayout())));
3062       SDVTList VTs = DAG.getVTList(ArrayRef<EVT>({MVT::Other})); // outchain
3063       DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops));
3064       break;
3065     }
3066     }
3067   } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) {
3068     // Currently we do not lower any intrinsic calls with deopt operand bundles.
3069     // Eventually we will support lowering the @llvm.experimental.deoptimize
3070     // intrinsic, and right now there are no plans to support other intrinsics
3071     // with deopt state.
3072     LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
3073   } else {
3074     LowerCallTo(I, getValue(Callee), false, false, EHPadBB);
3075   }
3076 
3077   // If the value of the invoke is used outside of its defining block, make it
3078   // available as a virtual register.
3079   // We already took care of the exported value for the statepoint instruction
3080   // during call to the LowerStatepoint.
3081   if (!isa<GCStatepointInst>(I)) {
3082     CopyToExportRegsIfNeeded(&I);
3083   }
3084 
3085   SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
3086   BranchProbabilityInfo *BPI = FuncInfo.BPI;
3087   BranchProbability EHPadBBProb =
3088       BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
3089           : BranchProbability::getZero();
3090   findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
3091 
3092   // Update successor info.
3093   addSuccessorWithProb(InvokeMBB, Return);
3094   for (auto &UnwindDest : UnwindDests) {
3095     UnwindDest.first->setIsEHPad();
3096     addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
3097   }
3098   InvokeMBB->normalizeSuccProbs();
3099 
3100   // Drop into normal successor.
3101   DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(),
3102                           DAG.getBasicBlock(Return)));
3103 }
3104 
3105 void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
3106   MachineBasicBlock *CallBrMBB = FuncInfo.MBB;
3107 
3108   // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
3109   // have to do anything here to lower funclet bundles.
3110   assert(!I.hasOperandBundlesOtherThan(
3111              {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
3112          "Cannot lower callbrs with arbitrary operand bundles yet!");
3113 
3114   assert(I.isInlineAsm() && "Only know how to handle inlineasm callbr");
3115   visitInlineAsm(I);
3116   CopyToExportRegsIfNeeded(&I);
3117 
3118   // Retrieve successors.
3119   SmallPtrSet<BasicBlock *, 8> Dests;
3120   Dests.insert(I.getDefaultDest());
3121   MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()];
3122 
3123   // Update successor info.
3124   addSuccessorWithProb(CallBrMBB, Return, BranchProbability::getOne());
3125   for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) {
3126     BasicBlock *Dest = I.getIndirectDest(i);
3127     MachineBasicBlock *Target = FuncInfo.MBBMap[Dest];
3128     Target->setIsInlineAsmBrIndirectTarget();
3129     Target->setMachineBlockAddressTaken();
3130     Target->setLabelMustBeEmitted();
3131     // Don't add duplicate machine successors.
3132     if (Dests.insert(Dest).second)
3133       addSuccessorWithProb(CallBrMBB, Target, BranchProbability::getZero());
3134   }
3135   CallBrMBB->normalizeSuccProbs();
3136 
3137   // Drop into default successor.
3138   DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
3139                           MVT::Other, getControlRoot(),
3140                           DAG.getBasicBlock(Return)));
3141 }
3142 
3143 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
3144   llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
3145 }
3146 
3147 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
3148   assert(FuncInfo.MBB->isEHPad() &&
3149          "Call to landingpad not in landing pad!");
3150 
3151   // If there aren't registers to copy the values into (e.g., during SjLj
3152   // exceptions), then don't bother to create these DAG nodes.
3153   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3154   const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
3155   if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
3156       TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
3157     return;
3158 
3159   // If landingpad's return type is token type, we don't create DAG nodes
3160   // for its exception pointer and selector value. The extraction of exception
3161   // pointer or selector value from token type landingpads is not currently
3162   // supported.
3163   if (LP.getType()->isTokenTy())
3164     return;
3165 
3166   SmallVector<EVT, 2> ValueVTs;
3167   SDLoc dl = getCurSDLoc();
3168   ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
3169   assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
3170 
3171   // Get the two live-in registers as SDValues. The physregs have already been
3172   // copied into virtual registers.
3173   SDValue Ops[2];
3174   if (FuncInfo.ExceptionPointerVirtReg) {
3175     Ops[0] = DAG.getZExtOrTrunc(
3176         DAG.getCopyFromReg(DAG.getEntryNode(), dl,
3177                            FuncInfo.ExceptionPointerVirtReg,
3178                            TLI.getPointerTy(DAG.getDataLayout())),
3179         dl, ValueVTs[0]);
3180   } else {
3181     Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
3182   }
3183   Ops[1] = DAG.getZExtOrTrunc(
3184       DAG.getCopyFromReg(DAG.getEntryNode(), dl,
3185                          FuncInfo.ExceptionSelectorVirtReg,
3186                          TLI.getPointerTy(DAG.getDataLayout())),
3187       dl, ValueVTs[1]);
3188 
3189   // Merge into one.
3190   SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
3191                             DAG.getVTList(ValueVTs), Ops);
3192   setValue(&LP, Res);
3193 }
3194 
3195 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
3196                                            MachineBasicBlock *Last) {
3197   // Update JTCases.
3198   for (JumpTableBlock &JTB : SL->JTCases)
3199     if (JTB.first.HeaderBB == First)
3200       JTB.first.HeaderBB = Last;
3201 
3202   // Update BitTestCases.
3203   for (BitTestBlock &BTB : SL->BitTestCases)
3204     if (BTB.Parent == First)
3205       BTB.Parent = Last;
3206 }
3207 
3208 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
3209   MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
3210 
3211   // Update machine-CFG edges with unique successors.
3212   SmallSet<BasicBlock*, 32> Done;
3213   for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
3214     BasicBlock *BB = I.getSuccessor(i);
3215     bool Inserted = Done.insert(BB).second;
3216     if (!Inserted)
3217         continue;
3218 
3219     MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
3220     addSuccessorWithProb(IndirectBrMBB, Succ);
3221   }
3222   IndirectBrMBB->normalizeSuccProbs();
3223 
3224   DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
3225                           MVT::Other, getControlRoot(),
3226                           getValue(I.getAddress())));
3227 }
3228 
3229 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
3230   if (!DAG.getTarget().Options.TrapUnreachable)
3231     return;
3232 
3233   // We may be able to ignore unreachable behind a noreturn call.
3234   if (DAG.getTarget().Options.NoTrapAfterNoreturn) {
3235     if (const CallInst *Call = dyn_cast_or_null<CallInst>(I.getPrevNode())) {
3236       if (Call->doesNotReturn())
3237         return;
3238     }
3239   }
3240 
3241   DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
3242 }
3243 
3244 void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
3245   SDNodeFlags Flags;
3246   if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
3247     Flags.copyFMF(*FPOp);
3248 
3249   SDValue Op = getValue(I.getOperand(0));
3250   SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(),
3251                                     Op, Flags);
3252   setValue(&I, UnNodeValue);
3253 }
3254 
3255 void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
3256   SDNodeFlags Flags;
3257   if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) {
3258     Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3259     Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3260   }
3261   if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I))
3262     Flags.setExact(ExactOp->isExact());
3263   if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
3264     Flags.copyFMF(*FPOp);
3265 
3266   SDValue Op1 = getValue(I.getOperand(0));
3267   SDValue Op2 = getValue(I.getOperand(1));
3268   SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(),
3269                                      Op1, Op2, Flags);
3270   setValue(&I, BinNodeValue);
3271 }
3272 
3273 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
3274   SDValue Op1 = getValue(I.getOperand(0));
3275   SDValue Op2 = getValue(I.getOperand(1));
3276 
3277   EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
3278       Op1.getValueType(), DAG.getDataLayout());
3279 
3280   // Coerce the shift amount to the right type if we can. This exposes the
3281   // truncate or zext to optimization early.
3282   if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
3283     assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) &&
3284            "Unexpected shift type");
3285     Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy);
3286   }
3287 
3288   bool nuw = false;
3289   bool nsw = false;
3290   bool exact = false;
3291 
3292   if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3293 
3294     if (const OverflowingBinaryOperator *OFBinOp =
3295             dyn_cast<const OverflowingBinaryOperator>(&I)) {
3296       nuw = OFBinOp->hasNoUnsignedWrap();
3297       nsw = OFBinOp->hasNoSignedWrap();
3298     }
3299     if (const PossiblyExactOperator *ExactOp =
3300             dyn_cast<const PossiblyExactOperator>(&I))
3301       exact = ExactOp->isExact();
3302   }
3303   SDNodeFlags Flags;
3304   Flags.setExact(exact);
3305   Flags.setNoSignedWrap(nsw);
3306   Flags.setNoUnsignedWrap(nuw);
3307   SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
3308                             Flags);
3309   setValue(&I, Res);
3310 }
3311 
3312 void SelectionDAGBuilder::visitSDiv(const User &I) {
3313   SDValue Op1 = getValue(I.getOperand(0));
3314   SDValue Op2 = getValue(I.getOperand(1));
3315 
3316   SDNodeFlags Flags;
3317   Flags.setExact(isa<PossiblyExactOperator>(&I) &&
3318                  cast<PossiblyExactOperator>(&I)->isExact());
3319   setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
3320                            Op2, Flags));
3321 }
3322 
3323 void SelectionDAGBuilder::visitICmp(const User &I) {
3324   ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
3325   if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
3326     predicate = IC->getPredicate();
3327   else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
3328     predicate = ICmpInst::Predicate(IC->getPredicate());
3329   SDValue Op1 = getValue(I.getOperand(0));
3330   SDValue Op2 = getValue(I.getOperand(1));
3331   ISD::CondCode Opcode = getICmpCondCode(predicate);
3332 
3333   auto &TLI = DAG.getTargetLoweringInfo();
3334   EVT MemVT =
3335       TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3336 
3337   // If a pointer's DAG type is larger than its memory type then the DAG values
3338   // are zero-extended. This breaks signed comparisons so truncate back to the
3339   // underlying type before doing the compare.
3340   if (Op1.getValueType() != MemVT) {
3341     Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT);
3342     Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT);
3343   }
3344 
3345   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3346                                                         I.getType());
3347   setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
3348 }
3349 
3350 void SelectionDAGBuilder::visitFCmp(const User &I) {
3351   FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
3352   if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
3353     predicate = FC->getPredicate();
3354   else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
3355     predicate = FCmpInst::Predicate(FC->getPredicate());
3356   SDValue Op1 = getValue(I.getOperand(0));
3357   SDValue Op2 = getValue(I.getOperand(1));
3358 
3359   ISD::CondCode Condition = getFCmpCondCode(predicate);
3360   auto *FPMO = cast<FPMathOperator>(&I);
3361   if (FPMO->hasNoNaNs() || TM.Options.NoNaNsFPMath)
3362     Condition = getFCmpCodeWithoutNaN(Condition);
3363 
3364   SDNodeFlags Flags;
3365   Flags.copyFMF(*FPMO);
3366   SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
3367 
3368   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3369                                                         I.getType());
3370   setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
3371 }
3372 
3373 // Check if the condition of the select has one use or two users that are both
3374 // selects with the same condition.
3375 static bool hasOnlySelectUsers(const Value *Cond) {
3376   return llvm::all_of(Cond->users(), [](const Value *V) {
3377     return isa<SelectInst>(V);
3378   });
3379 }
3380 
3381 void SelectionDAGBuilder::visitSelect(const User &I) {
3382   SmallVector<EVT, 4> ValueVTs;
3383   ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
3384                   ValueVTs);
3385   unsigned NumValues = ValueVTs.size();
3386   if (NumValues == 0) return;
3387 
3388   SmallVector<SDValue, 4> Values(NumValues);
3389   SDValue Cond     = getValue(I.getOperand(0));
3390   SDValue LHSVal   = getValue(I.getOperand(1));
3391   SDValue RHSVal   = getValue(I.getOperand(2));
3392   SmallVector<SDValue, 1> BaseOps(1, Cond);
3393   ISD::NodeType OpCode =
3394       Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
3395 
3396   bool IsUnaryAbs = false;
3397   bool Negate = false;
3398 
3399   SDNodeFlags Flags;
3400   if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
3401     Flags.copyFMF(*FPOp);
3402 
3403   Flags.setUnpredictable(
3404       cast<SelectInst>(I).getMetadata(LLVMContext::MD_unpredictable));
3405 
3406   // Min/max matching is only viable if all output VTs are the same.
3407   if (all_equal(ValueVTs)) {
3408     EVT VT = ValueVTs[0];
3409     LLVMContext &Ctx = *DAG.getContext();
3410     auto &TLI = DAG.getTargetLoweringInfo();
3411 
3412     // We care about the legality of the operation after it has been type
3413     // legalized.
3414     while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal)
3415       VT = TLI.getTypeToTransformTo(Ctx, VT);
3416 
3417     // If the vselect is legal, assume we want to leave this as a vector setcc +
3418     // vselect. Otherwise, if this is going to be scalarized, we want to see if
3419     // min/max is legal on the scalar type.
3420     bool UseScalarMinMax = VT.isVector() &&
3421       !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
3422 
3423     // ValueTracking's select pattern matching does not account for -0.0,
3424     // so we can't lower to FMINIMUM/FMAXIMUM because those nodes specify that
3425     // -0.0 is less than +0.0.
3426     Value *LHS, *RHS;
3427     auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
3428     ISD::NodeType Opc = ISD::DELETED_NODE;
3429     switch (SPR.Flavor) {
3430     case SPF_UMAX:    Opc = ISD::UMAX; break;
3431     case SPF_UMIN:    Opc = ISD::UMIN; break;
3432     case SPF_SMAX:    Opc = ISD::SMAX; break;
3433     case SPF_SMIN:    Opc = ISD::SMIN; break;
3434     case SPF_FMINNUM:
3435       switch (SPR.NaNBehavior) {
3436       case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3437       case SPNB_RETURNS_NAN: break;
3438       case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
3439       case SPNB_RETURNS_ANY:
3440         if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ||
3441             (UseScalarMinMax &&
3442              TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType())))
3443           Opc = ISD::FMINNUM;
3444         break;
3445       }
3446       break;
3447     case SPF_FMAXNUM:
3448       switch (SPR.NaNBehavior) {
3449       case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3450       case SPNB_RETURNS_NAN: break;
3451       case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
3452       case SPNB_RETURNS_ANY:
3453         if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ||
3454             (UseScalarMinMax &&
3455              TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType())))
3456           Opc = ISD::FMAXNUM;
3457         break;
3458       }
3459       break;
3460     case SPF_NABS:
3461       Negate = true;
3462       [[fallthrough]];
3463     case SPF_ABS:
3464       IsUnaryAbs = true;
3465       Opc = ISD::ABS;
3466       break;
3467     default: break;
3468     }
3469 
3470     if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
3471         (TLI.isOperationLegalOrCustom(Opc, VT) ||
3472          (UseScalarMinMax &&
3473           TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
3474         // If the underlying comparison instruction is used by any other
3475         // instruction, the consumed instructions won't be destroyed, so it is
3476         // not profitable to convert to a min/max.
3477         hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
3478       OpCode = Opc;
3479       LHSVal = getValue(LHS);
3480       RHSVal = getValue(RHS);
3481       BaseOps.clear();
3482     }
3483 
3484     if (IsUnaryAbs) {
3485       OpCode = Opc;
3486       LHSVal = getValue(LHS);
3487       BaseOps.clear();
3488     }
3489   }
3490 
3491   if (IsUnaryAbs) {
3492     for (unsigned i = 0; i != NumValues; ++i) {
3493       SDLoc dl = getCurSDLoc();
3494       EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i);
3495       Values[i] =
3496           DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i));
3497       if (Negate)
3498         Values[i] = DAG.getNegative(Values[i], dl, VT);
3499     }
3500   } else {
3501     for (unsigned i = 0; i != NumValues; ++i) {
3502       SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3503       Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3504       Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3505       Values[i] = DAG.getNode(
3506           OpCode, getCurSDLoc(),
3507           LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags);
3508     }
3509   }
3510 
3511   setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3512                            DAG.getVTList(ValueVTs), Values));
3513 }
3514 
3515 void SelectionDAGBuilder::visitTrunc(const User &I) {
3516   // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3517   SDValue N = getValue(I.getOperand(0));
3518   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3519                                                         I.getType());
3520   setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3521 }
3522 
3523 void SelectionDAGBuilder::visitZExt(const User &I) {
3524   // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3525   // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3526   SDValue N = getValue(I.getOperand(0));
3527   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3528                                                         I.getType());
3529   setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3530 }
3531 
3532 void SelectionDAGBuilder::visitSExt(const User &I) {
3533   // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3534   // SExt also can't be a cast to bool for same reason. So, nothing much to do
3535   SDValue N = getValue(I.getOperand(0));
3536   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3537                                                         I.getType());
3538   setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3539 }
3540 
3541 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3542   // FPTrunc is never a no-op cast, no need to check
3543   SDValue N = getValue(I.getOperand(0));
3544   SDLoc dl = getCurSDLoc();
3545   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3546   EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3547   setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
3548                            DAG.getTargetConstant(
3549                                0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
3550 }
3551 
3552 void SelectionDAGBuilder::visitFPExt(const User &I) {
3553   // FPExt is never a no-op cast, no need to check
3554   SDValue N = getValue(I.getOperand(0));
3555   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3556                                                         I.getType());
3557   setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3558 }
3559 
3560 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3561   // FPToUI is never a no-op cast, no need to check
3562   SDValue N = getValue(I.getOperand(0));
3563   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3564                                                         I.getType());
3565   setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3566 }
3567 
3568 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3569   // FPToSI is never a no-op cast, no need to check
3570   SDValue N = getValue(I.getOperand(0));
3571   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3572                                                         I.getType());
3573   setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3574 }
3575 
3576 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3577   // UIToFP is never a no-op cast, no need to check
3578   SDValue N = getValue(I.getOperand(0));
3579   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3580                                                         I.getType());
3581   setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3582 }
3583 
3584 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3585   // SIToFP is never a no-op cast, no need to check
3586   SDValue N = getValue(I.getOperand(0));
3587   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3588                                                         I.getType());
3589   setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3590 }
3591 
3592 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3593   // What to do depends on the size of the integer and the size of the pointer.
3594   // We can either truncate, zero extend, or no-op, accordingly.
3595   SDValue N = getValue(I.getOperand(0));
3596   auto &TLI = DAG.getTargetLoweringInfo();
3597   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3598                                                         I.getType());
3599   EVT PtrMemVT =
3600       TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3601   N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3602   N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT);
3603   setValue(&I, N);
3604 }
3605 
3606 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3607   // What to do depends on the size of the integer and the size of the pointer.
3608   // We can either truncate, zero extend, or no-op, accordingly.
3609   SDValue N = getValue(I.getOperand(0));
3610   auto &TLI = DAG.getTargetLoweringInfo();
3611   EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3612   EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
3613   N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3614   N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT);
3615   setValue(&I, N);
3616 }
3617 
3618 void SelectionDAGBuilder::visitBitCast(const User &I) {
3619   SDValue N = getValue(I.getOperand(0));
3620   SDLoc dl = getCurSDLoc();
3621   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3622                                                         I.getType());
3623 
3624   // BitCast assures us that source and destination are the same size so this is
3625   // either a BITCAST or a no-op.
3626   if (DestVT != N.getValueType())
3627     setValue(&I, DAG.getNode(ISD::BITCAST, dl,
3628                              DestVT, N)); // convert types.
3629   // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3630   // might fold any kind of constant expression to an integer constant and that
3631   // is not what we are looking for. Only recognize a bitcast of a genuine
3632   // constant integer as an opaque constant.
3633   else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3634     setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
3635                                  /*isOpaque*/true));
3636   else
3637     setValue(&I, N);            // noop cast.
3638 }
3639 
3640 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3641   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3642   const Value *SV = I.getOperand(0);
3643   SDValue N = getValue(SV);
3644   EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3645 
3646   unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3647   unsigned DestAS = I.getType()->getPointerAddressSpace();
3648 
3649   if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS))
3650     N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3651 
3652   setValue(&I, N);
3653 }
3654 
3655 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3656   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3657   SDValue InVec = getValue(I.getOperand(0));
3658   SDValue InVal = getValue(I.getOperand(1));
3659   SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
3660                                      TLI.getVectorIdxTy(DAG.getDataLayout()));
3661   setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3662                            TLI.getValueType(DAG.getDataLayout(), I.getType()),
3663                            InVec, InVal, InIdx));
3664 }
3665 
3666 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3667   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3668   SDValue InVec = getValue(I.getOperand(0));
3669   SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
3670                                      TLI.getVectorIdxTy(DAG.getDataLayout()));
3671   setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3672                            TLI.getValueType(DAG.getDataLayout(), I.getType()),
3673                            InVec, InIdx));
3674 }
3675 
3676 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3677   SDValue Src1 = getValue(I.getOperand(0));
3678   SDValue Src2 = getValue(I.getOperand(1));
3679   ArrayRef<int> Mask;
3680   if (auto *SVI = dyn_cast<ShuffleVectorInst>(&I))
3681     Mask = SVI->getShuffleMask();
3682   else
3683     Mask = cast<ConstantExpr>(I).getShuffleMask();
3684   SDLoc DL = getCurSDLoc();
3685   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3686   EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3687   EVT SrcVT = Src1.getValueType();
3688 
3689   if (all_of(Mask, [](int Elem) { return Elem == 0; }) &&
3690       VT.isScalableVector()) {
3691     // Canonical splat form of first element of first input vector.
3692     SDValue FirstElt =
3693         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcVT.getScalarType(), Src1,
3694                     DAG.getVectorIdxConstant(0, DL));
3695     setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt));
3696     return;
3697   }
3698 
3699   // For now, we only handle splats for scalable vectors.
3700   // The DAGCombiner will perform a BUILD_VECTOR -> SPLAT_VECTOR transformation
3701   // for targets that support a SPLAT_VECTOR for non-scalable vector types.
3702   assert(!VT.isScalableVector() && "Unsupported scalable vector shuffle");
3703 
3704   unsigned SrcNumElts = SrcVT.getVectorNumElements();
3705   unsigned MaskNumElts = Mask.size();
3706 
3707   if (SrcNumElts == MaskNumElts) {
3708     setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
3709     return;
3710   }
3711 
3712   // Normalize the shuffle vector since mask and vector length don't match.
3713   if (SrcNumElts < MaskNumElts) {
3714     // Mask is longer than the source vectors. We can use concatenate vector to
3715     // make the mask and vectors lengths match.
3716 
3717     if (MaskNumElts % SrcNumElts == 0) {
3718       // Mask length is a multiple of the source vector length.
3719       // Check if the shuffle is some kind of concatenation of the input
3720       // vectors.
3721       unsigned NumConcat = MaskNumElts / SrcNumElts;
3722       bool IsConcat = true;
3723       SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
3724       for (unsigned i = 0; i != MaskNumElts; ++i) {
3725         int Idx = Mask[i];
3726         if (Idx < 0)
3727           continue;
3728         // Ensure the indices in each SrcVT sized piece are sequential and that
3729         // the same source is used for the whole piece.
3730         if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3731             (ConcatSrcs[i / SrcNumElts] >= 0 &&
3732              ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3733           IsConcat = false;
3734           break;
3735         }
3736         // Remember which source this index came from.
3737         ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3738       }
3739 
3740       // The shuffle is concatenating multiple vectors together. Just emit
3741       // a CONCAT_VECTORS operation.
3742       if (IsConcat) {
3743         SmallVector<SDValue, 8> ConcatOps;
3744         for (auto Src : ConcatSrcs) {
3745           if (Src < 0)
3746             ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3747           else if (Src == 0)
3748             ConcatOps.push_back(Src1);
3749           else
3750             ConcatOps.push_back(Src2);
3751         }
3752         setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3753         return;
3754       }
3755     }
3756 
3757     unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3758     unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3759     EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3760                                     PaddedMaskNumElts);
3761 
3762     // Pad both vectors with undefs to make them the same length as the mask.
3763     SDValue UndefVal = DAG.getUNDEF(SrcVT);
3764 
3765     SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3766     SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3767     MOps1[0] = Src1;
3768     MOps2[0] = Src2;
3769 
3770     Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3771     Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3772 
3773     // Readjust mask for new input vector length.
3774     SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3775     for (unsigned i = 0; i != MaskNumElts; ++i) {
3776       int Idx = Mask[i];
3777       if (Idx >= (int)SrcNumElts)
3778         Idx -= SrcNumElts - PaddedMaskNumElts;
3779       MappedOps[i] = Idx;
3780     }
3781 
3782     SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3783 
3784     // If the concatenated vector was padded, extract a subvector with the
3785     // correct number of elements.
3786     if (MaskNumElts != PaddedMaskNumElts)
3787       Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3788                            DAG.getVectorIdxConstant(0, DL));
3789 
3790     setValue(&I, Result);
3791     return;
3792   }
3793 
3794   if (SrcNumElts > MaskNumElts) {
3795     // Analyze the access pattern of the vector to see if we can extract
3796     // two subvectors and do the shuffle.
3797     int StartIdx[2] = { -1, -1 };  // StartIdx to extract from
3798     bool CanExtract = true;
3799     for (int Idx : Mask) {
3800       unsigned Input = 0;
3801       if (Idx < 0)
3802         continue;
3803 
3804       if (Idx >= (int)SrcNumElts) {
3805         Input = 1;
3806         Idx -= SrcNumElts;
3807       }
3808 
3809       // If all the indices come from the same MaskNumElts sized portion of
3810       // the sources we can use extract. Also make sure the extract wouldn't
3811       // extract past the end of the source.
3812       int NewStartIdx = alignDown(Idx, MaskNumElts);
3813       if (NewStartIdx + MaskNumElts > SrcNumElts ||
3814           (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
3815         CanExtract = false;
3816       // Make sure we always update StartIdx as we use it to track if all
3817       // elements are undef.
3818       StartIdx[Input] = NewStartIdx;
3819     }
3820 
3821     if (StartIdx[0] < 0 && StartIdx[1] < 0) {
3822       setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3823       return;
3824     }
3825     if (CanExtract) {
3826       // Extract appropriate subvector and generate a vector shuffle
3827       for (unsigned Input = 0; Input < 2; ++Input) {
3828         SDValue &Src = Input == 0 ? Src1 : Src2;
3829         if (StartIdx[Input] < 0)
3830           Src = DAG.getUNDEF(VT);
3831         else {
3832           Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3833                             DAG.getVectorIdxConstant(StartIdx[Input], DL));
3834         }
3835       }
3836 
3837       // Calculate new mask.
3838       SmallVector<int, 8> MappedOps(Mask);
3839       for (int &Idx : MappedOps) {
3840         if (Idx >= (int)SrcNumElts)
3841           Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3842         else if (Idx >= 0)
3843           Idx -= StartIdx[0];
3844       }
3845 
3846       setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3847       return;
3848     }
3849   }
3850 
3851   // We can't use either concat vectors or extract subvectors so fall back to
3852   // replacing the shuffle with extract and build vector.
3853   // to insert and build vector.
3854   EVT EltVT = VT.getVectorElementType();
3855   SmallVector<SDValue,8> Ops;
3856   for (int Idx : Mask) {
3857     SDValue Res;
3858 
3859     if (Idx < 0) {
3860       Res = DAG.getUNDEF(EltVT);
3861     } else {
3862       SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3863       if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3864 
3865       Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src,
3866                         DAG.getVectorIdxConstant(Idx, DL));
3867     }
3868 
3869     Ops.push_back(Res);
3870   }
3871 
3872   setValue(&I, DAG.getBuildVector(VT, DL, Ops));
3873 }
3874 
3875 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3876   ArrayRef<unsigned> Indices = I.getIndices();
3877   const Value *Op0 = I.getOperand(0);
3878   const Value *Op1 = I.getOperand(1);
3879   Type *AggTy = I.getType();
3880   Type *ValTy = Op1->getType();
3881   bool IntoUndef = isa<UndefValue>(Op0);
3882   bool FromUndef = isa<UndefValue>(Op1);
3883 
3884   unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3885 
3886   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3887   SmallVector<EVT, 4> AggValueVTs;
3888   ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3889   SmallVector<EVT, 4> ValValueVTs;
3890   ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3891 
3892   unsigned NumAggValues = AggValueVTs.size();
3893   unsigned NumValValues = ValValueVTs.size();
3894   SmallVector<SDValue, 4> Values(NumAggValues);
3895 
3896   // Ignore an insertvalue that produces an empty object
3897   if (!NumAggValues) {
3898     setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3899     return;
3900   }
3901 
3902   SDValue Agg = getValue(Op0);
3903   unsigned i = 0;
3904   // Copy the beginning value(s) from the original aggregate.
3905   for (; i != LinearIndex; ++i)
3906     Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3907                 SDValue(Agg.getNode(), Agg.getResNo() + i);
3908   // Copy values from the inserted value(s).
3909   if (NumValValues) {
3910     SDValue Val = getValue(Op1);
3911     for (; i != LinearIndex + NumValValues; ++i)
3912       Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3913                   SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3914   }
3915   // Copy remaining value(s) from the original aggregate.
3916   for (; i != NumAggValues; ++i)
3917     Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3918                 SDValue(Agg.getNode(), Agg.getResNo() + i);
3919 
3920   setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3921                            DAG.getVTList(AggValueVTs), Values));
3922 }
3923 
3924 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3925   ArrayRef<unsigned> Indices = I.getIndices();
3926   const Value *Op0 = I.getOperand(0);
3927   Type *AggTy = Op0->getType();
3928   Type *ValTy = I.getType();
3929   bool OutOfUndef = isa<UndefValue>(Op0);
3930 
3931   unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3932 
3933   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3934   SmallVector<EVT, 4> ValValueVTs;
3935   ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3936 
3937   unsigned NumValValues = ValValueVTs.size();
3938 
3939   // Ignore a extractvalue that produces an empty object
3940   if (!NumValValues) {
3941     setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3942     return;
3943   }
3944 
3945   SmallVector<SDValue, 4> Values(NumValValues);
3946 
3947   SDValue Agg = getValue(Op0);
3948   // Copy out the selected value(s).
3949   for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3950     Values[i - LinearIndex] =
3951       OutOfUndef ?
3952         DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3953         SDValue(Agg.getNode(), Agg.getResNo() + i);
3954 
3955   setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3956                            DAG.getVTList(ValValueVTs), Values));
3957 }
3958 
3959 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3960   Value *Op0 = I.getOperand(0);
3961   // Note that the pointer operand may be a vector of pointers. Take the scalar
3962   // element which holds a pointer.
3963   unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3964   SDValue N = getValue(Op0);
3965   SDLoc dl = getCurSDLoc();
3966   auto &TLI = DAG.getTargetLoweringInfo();
3967 
3968   // Normalize Vector GEP - all scalar operands should be converted to the
3969   // splat vector.
3970   bool IsVectorGEP = I.getType()->isVectorTy();
3971   ElementCount VectorElementCount =
3972       IsVectorGEP ? cast<VectorType>(I.getType())->getElementCount()
3973                   : ElementCount::getFixed(0);
3974 
3975   if (IsVectorGEP && !N.getValueType().isVector()) {
3976     LLVMContext &Context = *DAG.getContext();
3977     EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorElementCount);
3978     N = DAG.getSplat(VT, dl, N);
3979   }
3980 
3981   for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3982        GTI != E; ++GTI) {
3983     const Value *Idx = GTI.getOperand();
3984     if (StructType *StTy = GTI.getStructTypeOrNull()) {
3985       unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3986       if (Field) {
3987         // N = N + Offset
3988         uint64_t Offset =
3989             DAG.getDataLayout().getStructLayout(StTy)->getElementOffset(Field);
3990 
3991         // In an inbounds GEP with an offset that is nonnegative even when
3992         // interpreted as signed, assume there is no unsigned overflow.
3993         SDNodeFlags Flags;
3994         if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3995           Flags.setNoUnsignedWrap(true);
3996 
3997         N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3998                         DAG.getConstant(Offset, dl, N.getValueType()), Flags);
3999       }
4000     } else {
4001       // IdxSize is the width of the arithmetic according to IR semantics.
4002       // In SelectionDAG, we may prefer to do arithmetic in a wider bitwidth
4003       // (and fix up the result later).
4004       unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
4005       MVT IdxTy = MVT::getIntegerVT(IdxSize);
4006       TypeSize ElementSize =
4007           DAG.getDataLayout().getTypeAllocSize(GTI.getIndexedType());
4008       // We intentionally mask away the high bits here; ElementSize may not
4009       // fit in IdxTy.
4010       APInt ElementMul(IdxSize, ElementSize.getKnownMinValue());
4011       bool ElementScalable = ElementSize.isScalable();
4012 
4013       // If this is a scalar constant or a splat vector of constants,
4014       // handle it quickly.
4015       const auto *C = dyn_cast<Constant>(Idx);
4016       if (C && isa<VectorType>(C->getType()))
4017         C = C->getSplatValue();
4018 
4019       const auto *CI = dyn_cast_or_null<ConstantInt>(C);
4020       if (CI && CI->isZero())
4021         continue;
4022       if (CI && !ElementScalable) {
4023         APInt Offs = ElementMul * CI->getValue().sextOrTrunc(IdxSize);
4024         LLVMContext &Context = *DAG.getContext();
4025         SDValue OffsVal;
4026         if (IsVectorGEP)
4027           OffsVal = DAG.getConstant(
4028               Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorElementCount));
4029         else
4030           OffsVal = DAG.getConstant(Offs, dl, IdxTy);
4031 
4032         // In an inbounds GEP with an offset that is nonnegative even when
4033         // interpreted as signed, assume there is no unsigned overflow.
4034         SDNodeFlags Flags;
4035         if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
4036           Flags.setNoUnsignedWrap(true);
4037 
4038         OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType());
4039 
4040         N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags);
4041         continue;
4042       }
4043 
4044       // N = N + Idx * ElementMul;
4045       SDValue IdxN = getValue(Idx);
4046 
4047       if (!IdxN.getValueType().isVector() && IsVectorGEP) {
4048         EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(),
4049                                   VectorElementCount);
4050         IdxN = DAG.getSplat(VT, dl, IdxN);
4051       }
4052 
4053       // If the index is smaller or larger than intptr_t, truncate or extend
4054       // it.
4055       IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
4056 
4057       if (ElementScalable) {
4058         EVT VScaleTy = N.getValueType().getScalarType();
4059         SDValue VScale = DAG.getNode(
4060             ISD::VSCALE, dl, VScaleTy,
4061             DAG.getConstant(ElementMul.getZExtValue(), dl, VScaleTy));
4062         if (IsVectorGEP)
4063           VScale = DAG.getSplatVector(N.getValueType(), dl, VScale);
4064         IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale);
4065       } else {
4066         // If this is a multiply by a power of two, turn it into a shl
4067         // immediately.  This is a very common case.
4068         if (ElementMul != 1) {
4069           if (ElementMul.isPowerOf2()) {
4070             unsigned Amt = ElementMul.logBase2();
4071             IdxN = DAG.getNode(ISD::SHL, dl,
4072                                N.getValueType(), IdxN,
4073                                DAG.getConstant(Amt, dl, IdxN.getValueType()));
4074           } else {
4075             SDValue Scale = DAG.getConstant(ElementMul.getZExtValue(), dl,
4076                                             IdxN.getValueType());
4077             IdxN = DAG.getNode(ISD::MUL, dl,
4078                                N.getValueType(), IdxN, Scale);
4079           }
4080         }
4081       }
4082 
4083       N = DAG.getNode(ISD::ADD, dl,
4084                       N.getValueType(), N, IdxN);
4085     }
4086   }
4087 
4088   MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS);
4089   MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS);
4090   if (IsVectorGEP) {
4091     PtrTy = MVT::getVectorVT(PtrTy, VectorElementCount);
4092     PtrMemTy = MVT::getVectorVT(PtrMemTy, VectorElementCount);
4093   }
4094 
4095   if (PtrMemTy != PtrTy && !cast<GEPOperator>(I).isInBounds())
4096     N = DAG.getPtrExtendInReg(N, dl, PtrMemTy);
4097 
4098   setValue(&I, N);
4099 }
4100 
4101 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
4102   // If this is a fixed sized alloca in the entry block of the function,
4103   // allocate it statically on the stack.
4104   if (FuncInfo.StaticAllocaMap.count(&I))
4105     return;   // getValue will auto-populate this.
4106 
4107   SDLoc dl = getCurSDLoc();
4108   Type *Ty = I.getAllocatedType();
4109   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4110   auto &DL = DAG.getDataLayout();
4111   TypeSize TySize = DL.getTypeAllocSize(Ty);
4112   MaybeAlign Alignment = std::max(DL.getPrefTypeAlign(Ty), I.getAlign());
4113 
4114   SDValue AllocSize = getValue(I.getArraySize());
4115 
4116   EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), I.getAddressSpace());
4117   if (AllocSize.getValueType() != IntPtr)
4118     AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
4119 
4120   if (TySize.isScalable())
4121     AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize,
4122                             DAG.getVScale(dl, IntPtr,
4123                                           APInt(IntPtr.getScalarSizeInBits(),
4124                                                 TySize.getKnownMinValue())));
4125   else
4126     AllocSize =
4127         DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize,
4128                     DAG.getConstant(TySize.getFixedValue(), dl, IntPtr));
4129 
4130   // Handle alignment.  If the requested alignment is less than or equal to
4131   // the stack alignment, ignore it.  If the size is greater than or equal to
4132   // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
4133   Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign();
4134   if (*Alignment <= StackAlign)
4135     Alignment = std::nullopt;
4136 
4137   const uint64_t StackAlignMask = StackAlign.value() - 1U;
4138   // Round the size of the allocation up to the stack alignment size
4139   // by add SA-1 to the size. This doesn't overflow because we're computing
4140   // an address inside an alloca.
4141   SDNodeFlags Flags;
4142   Flags.setNoUnsignedWrap(true);
4143   AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
4144                           DAG.getConstant(StackAlignMask, dl, IntPtr), Flags);
4145 
4146   // Mask out the low bits for alignment purposes.
4147   AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
4148                           DAG.getConstant(~StackAlignMask, dl, IntPtr));
4149 
4150   SDValue Ops[] = {
4151       getRoot(), AllocSize,
4152       DAG.getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)};
4153   SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
4154   SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
4155   setValue(&I, DSA);
4156   DAG.setRoot(DSA.getValue(1));
4157 
4158   assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects());
4159 }
4160 
4161 static const MDNode *getRangeMetadata(const Instruction &I) {
4162   // If !noundef is not present, then !range violation results in a poison
4163   // value rather than immediate undefined behavior. In theory, transferring
4164   // these annotations to SDAG is fine, but in practice there are key SDAG
4165   // transforms that are known not to be poison-safe, such as folding logical
4166   // and/or to bitwise and/or. For now, only transfer !range if !noundef is
4167   // also present.
4168   if (!I.hasMetadata(LLVMContext::MD_noundef))
4169     return nullptr;
4170   return I.getMetadata(LLVMContext::MD_range);
4171 }
4172 
4173 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
4174   if (I.isAtomic())
4175     return visitAtomicLoad(I);
4176 
4177   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4178   const Value *SV = I.getOperand(0);
4179   if (TLI.supportSwiftError()) {
4180     // Swifterror values can come from either a function parameter with
4181     // swifterror attribute or an alloca with swifterror attribute.
4182     if (const Argument *Arg = dyn_cast<Argument>(SV)) {
4183       if (Arg->hasSwiftErrorAttr())
4184         return visitLoadFromSwiftError(I);
4185     }
4186 
4187     if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
4188       if (Alloca->isSwiftError())
4189         return visitLoadFromSwiftError(I);
4190     }
4191   }
4192 
4193   SDValue Ptr = getValue(SV);
4194 
4195   Type *Ty = I.getType();
4196   SmallVector<EVT, 4> ValueVTs, MemVTs;
4197   SmallVector<TypeSize, 4> Offsets;
4198   ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets, 0);
4199   unsigned NumValues = ValueVTs.size();
4200   if (NumValues == 0)
4201     return;
4202 
4203   Align Alignment = I.getAlign();
4204   AAMDNodes AAInfo = I.getAAMetadata();
4205   const MDNode *Ranges = getRangeMetadata(I);
4206   bool isVolatile = I.isVolatile();
4207   MachineMemOperand::Flags MMOFlags =
4208       TLI.getLoadMemOperandFlags(I, DAG.getDataLayout(), AC, LibInfo);
4209 
4210   SDValue Root;
4211   bool ConstantMemory = false;
4212   if (isVolatile)
4213     // Serialize volatile loads with other side effects.
4214     Root = getRoot();
4215   else if (NumValues > MaxParallelChains)
4216     Root = getMemoryRoot();
4217   else if (AA &&
4218            AA->pointsToConstantMemory(MemoryLocation(
4219                SV,
4220                LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
4221                AAInfo))) {
4222     // Do not serialize (non-volatile) loads of constant memory with anything.
4223     Root = DAG.getEntryNode();
4224     ConstantMemory = true;
4225     MMOFlags |= MachineMemOperand::MOInvariant;
4226   } else {
4227     // Do not serialize non-volatile loads against each other.
4228     Root = DAG.getRoot();
4229   }
4230 
4231   SDLoc dl = getCurSDLoc();
4232 
4233   if (isVolatile)
4234     Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
4235 
4236   SmallVector<SDValue, 4> Values(NumValues);
4237   SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4238 
4239   unsigned ChainI = 0;
4240   for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4241     // Serializing loads here may result in excessive register pressure, and
4242     // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
4243     // could recover a bit by hoisting nodes upward in the chain by recognizing
4244     // they are side-effect free or do not alias. The optimizer should really
4245     // avoid this case by converting large object/array copies to llvm.memcpy
4246     // (MaxParallelChains should always remain as failsafe).
4247     if (ChainI == MaxParallelChains) {
4248       assert(PendingLoads.empty() && "PendingLoads must be serialized first");
4249       SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4250                                   ArrayRef(Chains.data(), ChainI));
4251       Root = Chain;
4252       ChainI = 0;
4253     }
4254 
4255     // TODO: MachinePointerInfo only supports a fixed length offset.
4256     MachinePointerInfo PtrInfo =
4257         !Offsets[i].isScalable() || Offsets[i].isZero()
4258             ? MachinePointerInfo(SV, Offsets[i].getKnownMinValue())
4259             : MachinePointerInfo();
4260 
4261     SDValue A = DAG.getObjectPtrOffset(dl, Ptr, Offsets[i]);
4262     SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A, PtrInfo, Alignment,
4263                             MMOFlags, AAInfo, Ranges);
4264     Chains[ChainI] = L.getValue(1);
4265 
4266     if (MemVTs[i] != ValueVTs[i])
4267       L = DAG.getPtrExtOrTrunc(L, dl, ValueVTs[i]);
4268 
4269     Values[i] = L;
4270   }
4271 
4272   if (!ConstantMemory) {
4273     SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4274                                 ArrayRef(Chains.data(), ChainI));
4275     if (isVolatile)
4276       DAG.setRoot(Chain);
4277     else
4278       PendingLoads.push_back(Chain);
4279   }
4280 
4281   setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
4282                            DAG.getVTList(ValueVTs), Values));
4283 }
4284 
4285 void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
4286   assert(DAG.getTargetLoweringInfo().supportSwiftError() &&
4287          "call visitStoreToSwiftError when backend supports swifterror");
4288 
4289   SmallVector<EVT, 4> ValueVTs;
4290   SmallVector<uint64_t, 4> Offsets;
4291   const Value *SrcV = I.getOperand(0);
4292   ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
4293                   SrcV->getType(), ValueVTs, &Offsets, 0);
4294   assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4295          "expect a single EVT for swifterror");
4296 
4297   SDValue Src = getValue(SrcV);
4298   // Create a virtual register, then update the virtual register.
4299   Register VReg =
4300       SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand());
4301   // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
4302   // Chain can be getRoot or getControlRoot.
4303   SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
4304                                       SDValue(Src.getNode(), Src.getResNo()));
4305   DAG.setRoot(CopyNode);
4306 }
4307 
4308 void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
4309   assert(DAG.getTargetLoweringInfo().supportSwiftError() &&
4310          "call visitLoadFromSwiftError when backend supports swifterror");
4311 
4312   assert(!I.isVolatile() &&
4313          !I.hasMetadata(LLVMContext::MD_nontemporal) &&
4314          !I.hasMetadata(LLVMContext::MD_invariant_load) &&
4315          "Support volatile, non temporal, invariant for load_from_swift_error");
4316 
4317   const Value *SV = I.getOperand(0);
4318   Type *Ty = I.getType();
4319   assert(
4320       (!AA ||
4321        !AA->pointsToConstantMemory(MemoryLocation(
4322            SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
4323            I.getAAMetadata()))) &&
4324       "load_from_swift_error should not be constant memory");
4325 
4326   SmallVector<EVT, 4> ValueVTs;
4327   SmallVector<uint64_t, 4> Offsets;
4328   ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty,
4329                   ValueVTs, &Offsets, 0);
4330   assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4331          "expect a single EVT for swifterror");
4332 
4333   // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
4334   SDValue L = DAG.getCopyFromReg(
4335       getRoot(), getCurSDLoc(),
4336       SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), ValueVTs[0]);
4337 
4338   setValue(&I, L);
4339 }
4340 
4341 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
4342   if (I.isAtomic())
4343     return visitAtomicStore(I);
4344 
4345   const Value *SrcV = I.getOperand(0);
4346   const Value *PtrV = I.getOperand(1);
4347 
4348   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4349   if (TLI.supportSwiftError()) {
4350     // Swifterror values can come from either a function parameter with
4351     // swifterror attribute or an alloca with swifterror attribute.
4352     if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4353       if (Arg->hasSwiftErrorAttr())
4354         return visitStoreToSwiftError(I);
4355     }
4356 
4357     if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4358       if (Alloca->isSwiftError())
4359         return visitStoreToSwiftError(I);
4360     }
4361   }
4362 
4363   SmallVector<EVT, 4> ValueVTs, MemVTs;
4364   SmallVector<TypeSize, 4> Offsets;
4365   ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
4366                   SrcV->getType(), ValueVTs, &MemVTs, &Offsets, 0);
4367   unsigned NumValues = ValueVTs.size();
4368   if (NumValues == 0)
4369     return;
4370 
4371   // Get the lowered operands. Note that we do this after
4372   // checking if NumResults is zero, because with zero results
4373   // the operands won't have values in the map.
4374   SDValue Src = getValue(SrcV);
4375   SDValue Ptr = getValue(PtrV);
4376 
4377   SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot();
4378   SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4379   SDLoc dl = getCurSDLoc();
4380   Align Alignment = I.getAlign();
4381   AAMDNodes AAInfo = I.getAAMetadata();
4382 
4383   auto MMOFlags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
4384 
4385   unsigned ChainI = 0;
4386   for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4387     // See visitLoad comments.
4388     if (ChainI == MaxParallelChains) {
4389       SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4390                                   ArrayRef(Chains.data(), ChainI));
4391       Root = Chain;
4392       ChainI = 0;
4393     }
4394 
4395     // TODO: MachinePointerInfo only supports a fixed length offset.
4396     MachinePointerInfo PtrInfo =
4397         !Offsets[i].isScalable() || Offsets[i].isZero()
4398             ? MachinePointerInfo(PtrV, Offsets[i].getKnownMinValue())
4399             : MachinePointerInfo();
4400 
4401     SDValue Add = DAG.getObjectPtrOffset(dl, Ptr, Offsets[i]);
4402     SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
4403     if (MemVTs[i] != ValueVTs[i])
4404       Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
4405     SDValue St =
4406         DAG.getStore(Root, dl, Val, Add, PtrInfo, Alignment, MMOFlags, AAInfo);
4407     Chains[ChainI] = St;
4408   }
4409 
4410   SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4411                                   ArrayRef(Chains.data(), ChainI));
4412   setValue(&I, StoreNode);
4413   DAG.setRoot(StoreNode);
4414 }
4415 
4416 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
4417                                            bool IsCompressing) {
4418   SDLoc sdl = getCurSDLoc();
4419 
4420   auto getMaskedStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4421                                MaybeAlign &Alignment) {
4422     // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
4423     Src0 = I.getArgOperand(0);
4424     Ptr = I.getArgOperand(1);
4425     Alignment = cast<ConstantInt>(I.getArgOperand(2))->getMaybeAlignValue();
4426     Mask = I.getArgOperand(3);
4427   };
4428   auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4429                                     MaybeAlign &Alignment) {
4430     // llvm.masked.compressstore.*(Src0, Ptr, Mask)
4431     Src0 = I.getArgOperand(0);
4432     Ptr = I.getArgOperand(1);
4433     Mask = I.getArgOperand(2);
4434     Alignment = std::nullopt;
4435   };
4436 
4437   Value  *PtrOperand, *MaskOperand, *Src0Operand;
4438   MaybeAlign Alignment;
4439   if (IsCompressing)
4440     getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4441   else
4442     getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4443 
4444   SDValue Ptr = getValue(PtrOperand);
4445   SDValue Src0 = getValue(Src0Operand);
4446   SDValue Mask = getValue(MaskOperand);
4447   SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
4448 
4449   EVT VT = Src0.getValueType();
4450   if (!Alignment)
4451     Alignment = DAG.getEVTAlign(VT);
4452 
4453   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4454       MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore,
4455       MemoryLocation::UnknownSize, *Alignment, I.getAAMetadata());
4456   SDValue StoreNode =
4457       DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO,
4458                          ISD::UNINDEXED, false /* Truncating */, IsCompressing);
4459   DAG.setRoot(StoreNode);
4460   setValue(&I, StoreNode);
4461 }
4462 
4463 // Get a uniform base for the Gather/Scatter intrinsic.
4464 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
4465 // We try to represent it as a base pointer + vector of indices.
4466 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
4467 // The first operand of the GEP may be a single pointer or a vector of pointers
4468 // Example:
4469 //   %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
4470 //  or
4471 //   %gep.ptr = getelementptr i32, i32* %ptr,        <8 x i32> %ind
4472 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
4473 //
4474 // When the first GEP operand is a single pointer - it is the uniform base we
4475 // are looking for. If first operand of the GEP is a splat vector - we
4476 // extract the splat value and use it as a uniform base.
4477 // In all other cases the function returns 'false'.
4478 static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index,
4479                            ISD::MemIndexType &IndexType, SDValue &Scale,
4480                            SelectionDAGBuilder *SDB, const BasicBlock *CurBB,
4481                            uint64_t ElemSize) {
4482   SelectionDAG& DAG = SDB->DAG;
4483   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4484   const DataLayout &DL = DAG.getDataLayout();
4485 
4486   assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
4487 
4488   // Handle splat constant pointer.
4489   if (auto *C = dyn_cast<Constant>(Ptr)) {
4490     C = C->getSplatValue();
4491     if (!C)
4492       return false;
4493 
4494     Base = SDB->getValue(C);
4495 
4496     ElementCount NumElts = cast<VectorType>(Ptr->getType())->getElementCount();
4497     EVT VT = EVT::getVectorVT(*DAG.getContext(), TLI.getPointerTy(DL), NumElts);
4498     Index = DAG.getConstant(0, SDB->getCurSDLoc(), VT);
4499     IndexType = ISD::SIGNED_SCALED;
4500     Scale = DAG.getTargetConstant(1, SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4501     return true;
4502   }
4503 
4504   const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
4505   if (!GEP || GEP->getParent() != CurBB)
4506     return false;
4507 
4508   if (GEP->getNumOperands() != 2)
4509     return false;
4510 
4511   const Value *BasePtr = GEP->getPointerOperand();
4512   const Value *IndexVal = GEP->getOperand(GEP->getNumOperands() - 1);
4513 
4514   // Make sure the base is scalar and the index is a vector.
4515   if (BasePtr->getType()->isVectorTy() || !IndexVal->getType()->isVectorTy())
4516     return false;
4517 
4518   TypeSize ScaleVal = DL.getTypeAllocSize(GEP->getResultElementType());
4519   if (ScaleVal.isScalable())
4520     return false;
4521 
4522   // Target may not support the required addressing mode.
4523   if (ScaleVal != 1 &&
4524       !TLI.isLegalScaleForGatherScatter(ScaleVal.getFixedValue(), ElemSize))
4525     return false;
4526 
4527   Base = SDB->getValue(BasePtr);
4528   Index = SDB->getValue(IndexVal);
4529   IndexType = ISD::SIGNED_SCALED;
4530 
4531   Scale =
4532       DAG.getTargetConstant(ScaleVal, SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4533   return true;
4534 }
4535 
4536 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
4537   SDLoc sdl = getCurSDLoc();
4538 
4539   // llvm.masked.scatter.*(Src0, Ptrs, alignment, Mask)
4540   const Value *Ptr = I.getArgOperand(1);
4541   SDValue Src0 = getValue(I.getArgOperand(0));
4542   SDValue Mask = getValue(I.getArgOperand(3));
4543   EVT VT = Src0.getValueType();
4544   Align Alignment = cast<ConstantInt>(I.getArgOperand(2))
4545                         ->getMaybeAlignValue()
4546                         .value_or(DAG.getEVTAlign(VT.getScalarType()));
4547   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4548 
4549   SDValue Base;
4550   SDValue Index;
4551   ISD::MemIndexType IndexType;
4552   SDValue Scale;
4553   bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this,
4554                                     I.getParent(), VT.getScalarStoreSize());
4555 
4556   unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
4557   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4558       MachinePointerInfo(AS), MachineMemOperand::MOStore,
4559       // TODO: Make MachineMemOperands aware of scalable
4560       // vectors.
4561       MemoryLocation::UnknownSize, Alignment, I.getAAMetadata());
4562   if (!UniformBase) {
4563     Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4564     Index = getValue(Ptr);
4565     IndexType = ISD::SIGNED_SCALED;
4566     Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4567   }
4568 
4569   EVT IdxVT = Index.getValueType();
4570   EVT EltTy = IdxVT.getVectorElementType();
4571   if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) {
4572     EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy);
4573     Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index);
4574   }
4575 
4576   SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale };
4577   SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
4578                                          Ops, MMO, IndexType, false);
4579   DAG.setRoot(Scatter);
4580   setValue(&I, Scatter);
4581 }
4582 
4583 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
4584   SDLoc sdl = getCurSDLoc();
4585 
4586   auto getMaskedLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4587                               MaybeAlign &Alignment) {
4588     // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
4589     Ptr = I.getArgOperand(0);
4590     Alignment = cast<ConstantInt>(I.getArgOperand(1))->getMaybeAlignValue();
4591     Mask = I.getArgOperand(2);
4592     Src0 = I.getArgOperand(3);
4593   };
4594   auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4595                                  MaybeAlign &Alignment) {
4596     // @llvm.masked.expandload.*(Ptr, Mask, Src0)
4597     Ptr = I.getArgOperand(0);
4598     Alignment = std::nullopt;
4599     Mask = I.getArgOperand(1);
4600     Src0 = I.getArgOperand(2);
4601   };
4602 
4603   Value  *PtrOperand, *MaskOperand, *Src0Operand;
4604   MaybeAlign Alignment;
4605   if (IsExpanding)
4606     getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4607   else
4608     getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4609 
4610   SDValue Ptr = getValue(PtrOperand);
4611   SDValue Src0 = getValue(Src0Operand);
4612   SDValue Mask = getValue(MaskOperand);
4613   SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
4614 
4615   EVT VT = Src0.getValueType();
4616   if (!Alignment)
4617     Alignment = DAG.getEVTAlign(VT);
4618 
4619   AAMDNodes AAInfo = I.getAAMetadata();
4620   const MDNode *Ranges = getRangeMetadata(I);
4621 
4622   // Do not serialize masked loads of constant memory with anything.
4623   MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo);
4624   bool AddToChain = !AA || !AA->pointsToConstantMemory(ML);
4625 
4626   SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
4627 
4628   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4629       MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad,
4630       MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges);
4631 
4632   SDValue Load =
4633       DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Offset, Mask, Src0, VT, MMO,
4634                         ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding);
4635   if (AddToChain)
4636     PendingLoads.push_back(Load.getValue(1));
4637   setValue(&I, Load);
4638 }
4639 
4640 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
4641   SDLoc sdl = getCurSDLoc();
4642 
4643   // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
4644   const Value *Ptr = I.getArgOperand(0);
4645   SDValue Src0 = getValue(I.getArgOperand(3));
4646   SDValue Mask = getValue(I.getArgOperand(2));
4647 
4648   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4649   EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4650   Align Alignment = cast<ConstantInt>(I.getArgOperand(1))
4651                         ->getMaybeAlignValue()
4652                         .value_or(DAG.getEVTAlign(VT.getScalarType()));
4653 
4654   const MDNode *Ranges = getRangeMetadata(I);
4655 
4656   SDValue Root = DAG.getRoot();
4657   SDValue Base;
4658   SDValue Index;
4659   ISD::MemIndexType IndexType;
4660   SDValue Scale;
4661   bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this,
4662                                     I.getParent(), VT.getScalarStoreSize());
4663   unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
4664   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4665       MachinePointerInfo(AS), MachineMemOperand::MOLoad,
4666       // TODO: Make MachineMemOperands aware of scalable
4667       // vectors.
4668       MemoryLocation::UnknownSize, Alignment, I.getAAMetadata(), Ranges);
4669 
4670   if (!UniformBase) {
4671     Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4672     Index = getValue(Ptr);
4673     IndexType = ISD::SIGNED_SCALED;
4674     Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4675   }
4676 
4677   EVT IdxVT = Index.getValueType();
4678   EVT EltTy = IdxVT.getVectorElementType();
4679   if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) {
4680     EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy);
4681     Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index);
4682   }
4683 
4684   SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
4685   SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
4686                                        Ops, MMO, IndexType, ISD::NON_EXTLOAD);
4687 
4688   PendingLoads.push_back(Gather.getValue(1));
4689   setValue(&I, Gather);
4690 }
4691 
4692 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
4693   SDLoc dl = getCurSDLoc();
4694   AtomicOrdering SuccessOrdering = I.getSuccessOrdering();
4695   AtomicOrdering FailureOrdering = I.getFailureOrdering();
4696   SyncScope::ID SSID = I.getSyncScopeID();
4697 
4698   SDValue InChain = getRoot();
4699 
4700   MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4701   SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
4702 
4703   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4704   auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout());
4705 
4706   MachineFunction &MF = DAG.getMachineFunction();
4707   MachineMemOperand *MMO = MF.getMachineMemOperand(
4708       MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4709       DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, SuccessOrdering,
4710       FailureOrdering);
4711 
4712   SDValue L = DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
4713                                    dl, MemVT, VTs, InChain,
4714                                    getValue(I.getPointerOperand()),
4715                                    getValue(I.getCompareOperand()),
4716                                    getValue(I.getNewValOperand()), MMO);
4717 
4718   SDValue OutChain = L.getValue(2);
4719 
4720   setValue(&I, L);
4721   DAG.setRoot(OutChain);
4722 }
4723 
4724 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
4725   SDLoc dl = getCurSDLoc();
4726   ISD::NodeType NT;
4727   switch (I.getOperation()) {
4728   default: llvm_unreachable("Unknown atomicrmw operation");
4729   case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
4730   case AtomicRMWInst::Add:  NT = ISD::ATOMIC_LOAD_ADD; break;
4731   case AtomicRMWInst::Sub:  NT = ISD::ATOMIC_LOAD_SUB; break;
4732   case AtomicRMWInst::And:  NT = ISD::ATOMIC_LOAD_AND; break;
4733   case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
4734   case AtomicRMWInst::Or:   NT = ISD::ATOMIC_LOAD_OR; break;
4735   case AtomicRMWInst::Xor:  NT = ISD::ATOMIC_LOAD_XOR; break;
4736   case AtomicRMWInst::Max:  NT = ISD::ATOMIC_LOAD_MAX; break;
4737   case AtomicRMWInst::Min:  NT = ISD::ATOMIC_LOAD_MIN; break;
4738   case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
4739   case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
4740   case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
4741   case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
4742   case AtomicRMWInst::FMax: NT = ISD::ATOMIC_LOAD_FMAX; break;
4743   case AtomicRMWInst::FMin: NT = ISD::ATOMIC_LOAD_FMIN; break;
4744   case AtomicRMWInst::UIncWrap:
4745     NT = ISD::ATOMIC_LOAD_UINC_WRAP;
4746     break;
4747   case AtomicRMWInst::UDecWrap:
4748     NT = ISD::ATOMIC_LOAD_UDEC_WRAP;
4749     break;
4750   }
4751   AtomicOrdering Ordering = I.getOrdering();
4752   SyncScope::ID SSID = I.getSyncScopeID();
4753 
4754   SDValue InChain = getRoot();
4755 
4756   auto MemVT = getValue(I.getValOperand()).getSimpleValueType();
4757   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4758   auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout());
4759 
4760   MachineFunction &MF = DAG.getMachineFunction();
4761   MachineMemOperand *MMO = MF.getMachineMemOperand(
4762       MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4763       DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, Ordering);
4764 
4765   SDValue L =
4766     DAG.getAtomic(NT, dl, MemVT, InChain,
4767                   getValue(I.getPointerOperand()), getValue(I.getValOperand()),
4768                   MMO);
4769 
4770   SDValue OutChain = L.getValue(1);
4771 
4772   setValue(&I, L);
4773   DAG.setRoot(OutChain);
4774 }
4775 
4776 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
4777   SDLoc dl = getCurSDLoc();
4778   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4779   SDValue Ops[3];
4780   Ops[0] = getRoot();
4781   Ops[1] = DAG.getTargetConstant((unsigned)I.getOrdering(), dl,
4782                                  TLI.getFenceOperandTy(DAG.getDataLayout()));
4783   Ops[2] = DAG.getTargetConstant(I.getSyncScopeID(), dl,
4784                                  TLI.getFenceOperandTy(DAG.getDataLayout()));
4785   SDValue N = DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
4786   setValue(&I, N);
4787   DAG.setRoot(N);
4788 }
4789 
4790 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
4791   SDLoc dl = getCurSDLoc();
4792   AtomicOrdering Order = I.getOrdering();
4793   SyncScope::ID SSID = I.getSyncScopeID();
4794 
4795   SDValue InChain = getRoot();
4796 
4797   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4798   EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4799   EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
4800 
4801   if (!TLI.supportsUnalignedAtomics() &&
4802       I.getAlign().value() < MemVT.getSizeInBits() / 8)
4803     report_fatal_error("Cannot generate unaligned atomic load");
4804 
4805   auto Flags = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout(), AC, LibInfo);
4806 
4807   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4808       MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4809       I.getAlign(), AAMDNodes(), nullptr, SSID, Order);
4810 
4811   InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4812 
4813   SDValue Ptr = getValue(I.getPointerOperand());
4814 
4815   if (TLI.lowerAtomicLoadAsLoadSDNode(I)) {
4816     // TODO: Once this is better exercised by tests, it should be merged with
4817     // the normal path for loads to prevent future divergence.
4818     SDValue L = DAG.getLoad(MemVT, dl, InChain, Ptr, MMO);
4819     if (MemVT != VT)
4820       L = DAG.getPtrExtOrTrunc(L, dl, VT);
4821 
4822     setValue(&I, L);
4823     SDValue OutChain = L.getValue(1);
4824     if (!I.isUnordered())
4825       DAG.setRoot(OutChain);
4826     else
4827       PendingLoads.push_back(OutChain);
4828     return;
4829   }
4830 
4831   SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain,
4832                             Ptr, MMO);
4833 
4834   SDValue OutChain = L.getValue(1);
4835   if (MemVT != VT)
4836     L = DAG.getPtrExtOrTrunc(L, dl, VT);
4837 
4838   setValue(&I, L);
4839   DAG.setRoot(OutChain);
4840 }
4841 
4842 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4843   SDLoc dl = getCurSDLoc();
4844 
4845   AtomicOrdering Ordering = I.getOrdering();
4846   SyncScope::ID SSID = I.getSyncScopeID();
4847 
4848   SDValue InChain = getRoot();
4849 
4850   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4851   EVT MemVT =
4852       TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
4853 
4854   if (!TLI.supportsUnalignedAtomics() &&
4855       I.getAlign().value() < MemVT.getSizeInBits() / 8)
4856     report_fatal_error("Cannot generate unaligned atomic store");
4857 
4858   auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
4859 
4860   MachineFunction &MF = DAG.getMachineFunction();
4861   MachineMemOperand *MMO = MF.getMachineMemOperand(
4862       MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4863       I.getAlign(), AAMDNodes(), nullptr, SSID, Ordering);
4864 
4865   SDValue Val = getValue(I.getValueOperand());
4866   if (Val.getValueType() != MemVT)
4867     Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT);
4868   SDValue Ptr = getValue(I.getPointerOperand());
4869 
4870   if (TLI.lowerAtomicStoreAsStoreSDNode(I)) {
4871     // TODO: Once this is better exercised by tests, it should be merged with
4872     // the normal path for stores to prevent future divergence.
4873     SDValue S = DAG.getStore(InChain, dl, Val, Ptr, MMO);
4874     setValue(&I, S);
4875     DAG.setRoot(S);
4876     return;
4877   }
4878   SDValue OutChain =
4879       DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain, Val, Ptr, MMO);
4880 
4881   setValue(&I, OutChain);
4882   DAG.setRoot(OutChain);
4883 }
4884 
4885 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4886 /// node.
4887 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4888                                                unsigned Intrinsic) {
4889   // Ignore the callsite's attributes. A specific call site may be marked with
4890   // readnone, but the lowering code will expect the chain based on the
4891   // definition.
4892   const Function *F = I.getCalledFunction();
4893   bool HasChain = !F->doesNotAccessMemory();
4894   bool OnlyLoad = HasChain && F->onlyReadsMemory();
4895 
4896   // Build the operand list.
4897   SmallVector<SDValue, 8> Ops;
4898   if (HasChain) {  // If this intrinsic has side-effects, chainify it.
4899     if (OnlyLoad) {
4900       // We don't need to serialize loads against other loads.
4901       Ops.push_back(DAG.getRoot());
4902     } else {
4903       Ops.push_back(getRoot());
4904     }
4905   }
4906 
4907   // Info is set by getTgtMemIntrinsic
4908   TargetLowering::IntrinsicInfo Info;
4909   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4910   bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I,
4911                                                DAG.getMachineFunction(),
4912                                                Intrinsic);
4913 
4914   // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4915   if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4916       Info.opc == ISD::INTRINSIC_W_CHAIN)
4917     Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4918                                         TLI.getPointerTy(DAG.getDataLayout())));
4919 
4920   // Add all operands of the call to the operand list.
4921   for (unsigned i = 0, e = I.arg_size(); i != e; ++i) {
4922     const Value *Arg = I.getArgOperand(i);
4923     if (!I.paramHasAttr(i, Attribute::ImmArg)) {
4924       Ops.push_back(getValue(Arg));
4925       continue;
4926     }
4927 
4928     // Use TargetConstant instead of a regular constant for immarg.
4929     EVT VT = TLI.getValueType(DAG.getDataLayout(), Arg->getType(), true);
4930     if (const ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) {
4931       assert(CI->getBitWidth() <= 64 &&
4932              "large intrinsic immediates not handled");
4933       Ops.push_back(DAG.getTargetConstant(*CI, SDLoc(), VT));
4934     } else {
4935       Ops.push_back(
4936           DAG.getTargetConstantFP(*cast<ConstantFP>(Arg), SDLoc(), VT));
4937     }
4938   }
4939 
4940   SmallVector<EVT, 4> ValueVTs;
4941   ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4942 
4943   if (HasChain)
4944     ValueVTs.push_back(MVT::Other);
4945 
4946   SDVTList VTs = DAG.getVTList(ValueVTs);
4947 
4948   // Propagate fast-math-flags from IR to node(s).
4949   SDNodeFlags Flags;
4950   if (auto *FPMO = dyn_cast<FPMathOperator>(&I))
4951     Flags.copyFMF(*FPMO);
4952   SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
4953 
4954   // Create the node.
4955   SDValue Result;
4956   // In some cases, custom collection of operands from CallInst I may be needed.
4957   TLI.CollectTargetIntrinsicOperands(I, Ops, DAG);
4958   if (IsTgtIntrinsic) {
4959     // This is target intrinsic that touches memory
4960     //
4961     // TODO: We currently just fallback to address space 0 if getTgtMemIntrinsic
4962     //       didn't yield anything useful.
4963     MachinePointerInfo MPI;
4964     if (Info.ptrVal)
4965       MPI = MachinePointerInfo(Info.ptrVal, Info.offset);
4966     else if (Info.fallbackAddressSpace)
4967       MPI = MachinePointerInfo(*Info.fallbackAddressSpace);
4968     Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops,
4969                                      Info.memVT, MPI, Info.align, Info.flags,
4970                                      Info.size, I.getAAMetadata());
4971   } else if (!HasChain) {
4972     Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4973   } else if (!I.getType()->isVoidTy()) {
4974     Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4975   } else {
4976     Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4977   }
4978 
4979   if (HasChain) {
4980     SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4981     if (OnlyLoad)
4982       PendingLoads.push_back(Chain);
4983     else
4984       DAG.setRoot(Chain);
4985   }
4986 
4987   if (!I.getType()->isVoidTy()) {
4988     if (!isa<VectorType>(I.getType()))
4989       Result = lowerRangeToAssertZExt(DAG, I, Result);
4990 
4991     MaybeAlign Alignment = I.getRetAlign();
4992 
4993     // Insert `assertalign` node if there's an alignment.
4994     if (InsertAssertAlign && Alignment) {
4995       Result =
4996           DAG.getAssertAlign(getCurSDLoc(), Result, Alignment.valueOrOne());
4997     }
4998 
4999     setValue(&I, Result);
5000   }
5001 }
5002 
5003 /// GetSignificand - Get the significand and build it into a floating-point
5004 /// number with exponent of 1:
5005 ///
5006 ///   Op = (Op & 0x007fffff) | 0x3f800000;
5007 ///
5008 /// where Op is the hexadecimal representation of floating point value.
5009 static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
5010   SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
5011                            DAG.getConstant(0x007fffff, dl, MVT::i32));
5012   SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
5013                            DAG.getConstant(0x3f800000, dl, MVT::i32));
5014   return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
5015 }
5016 
5017 /// GetExponent - Get the exponent:
5018 ///
5019 ///   (float)(int)(((Op & 0x7f800000) >> 23) - 127);
5020 ///
5021 /// where Op is the hexadecimal representation of floating point value.
5022 static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
5023                            const TargetLowering &TLI, const SDLoc &dl) {
5024   SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
5025                            DAG.getConstant(0x7f800000, dl, MVT::i32));
5026   SDValue t1 = DAG.getNode(
5027       ISD::SRL, dl, MVT::i32, t0,
5028       DAG.getConstant(23, dl,
5029                       TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout())));
5030   SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
5031                            DAG.getConstant(127, dl, MVT::i32));
5032   return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
5033 }
5034 
5035 /// getF32Constant - Get 32-bit floating point constant.
5036 static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
5037                               const SDLoc &dl) {
5038   return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
5039                            MVT::f32);
5040 }
5041 
5042 static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
5043                                        SelectionDAG &DAG) {
5044   // TODO: What fast-math-flags should be set on the floating-point nodes?
5045 
5046   //   IntegerPartOfX = ((int32_t)(t0);
5047   SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
5048 
5049   //   FractionalPartOfX = t0 - (float)IntegerPartOfX;
5050   SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
5051   SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
5052 
5053   //   IntegerPartOfX <<= 23;
5054   IntegerPartOfX =
5055       DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
5056                   DAG.getConstant(23, dl,
5057                                   DAG.getTargetLoweringInfo().getShiftAmountTy(
5058                                       MVT::i32, DAG.getDataLayout())));
5059 
5060   SDValue TwoToFractionalPartOfX;
5061   if (LimitFloatPrecision <= 6) {
5062     // For floating-point precision of 6:
5063     //
5064     //   TwoToFractionalPartOfX =
5065     //     0.997535578f +
5066     //       (0.735607626f + 0.252464424f * x) * x;
5067     //
5068     // error 0.0144103317, which is 6 bits
5069     SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5070                              getF32Constant(DAG, 0x3e814304, dl));
5071     SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5072                              getF32Constant(DAG, 0x3f3c50c8, dl));
5073     SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5074     TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5075                                          getF32Constant(DAG, 0x3f7f5e7e, dl));
5076   } else if (LimitFloatPrecision <= 12) {
5077     // For floating-point precision of 12:
5078     //
5079     //   TwoToFractionalPartOfX =
5080     //     0.999892986f +
5081     //       (0.696457318f +
5082     //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
5083     //
5084     // error 0.000107046256, which is 13 to 14 bits
5085     SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5086                              getF32Constant(DAG, 0x3da235e3, dl));
5087     SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5088                              getF32Constant(DAG, 0x3e65b8f3, dl));
5089     SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5090     SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5091                              getF32Constant(DAG, 0x3f324b07, dl));
5092     SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5093     TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5094                                          getF32Constant(DAG, 0x3f7ff8fd, dl));
5095   } else { // LimitFloatPrecision <= 18
5096     // For floating-point precision of 18:
5097     //
5098     //   TwoToFractionalPartOfX =
5099     //     0.999999982f +
5100     //       (0.693148872f +
5101     //         (0.240227044f +
5102     //           (0.554906021e-1f +
5103     //             (0.961591928e-2f +
5104     //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
5105     // error 2.47208000*10^(-7), which is better than 18 bits
5106     SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5107                              getF32Constant(DAG, 0x3924b03e, dl));
5108     SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5109                              getF32Constant(DAG, 0x3ab24b87, dl));
5110     SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5111     SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5112                              getF32Constant(DAG, 0x3c1d8c17, dl));
5113     SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5114     SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5115                              getF32Constant(DAG, 0x3d634a1d, dl));
5116     SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5117     SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5118                              getF32Constant(DAG, 0x3e75fe14, dl));
5119     SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5120     SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
5121                               getF32Constant(DAG, 0x3f317234, dl));
5122     SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
5123     TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
5124                                          getF32Constant(DAG, 0x3f800000, dl));
5125   }
5126 
5127   // Add the exponent into the result in integer domain.
5128   SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
5129   return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5130                      DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
5131 }
5132 
5133 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
5134 /// limited-precision mode.
5135 static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5136                          const TargetLowering &TLI, SDNodeFlags Flags) {
5137   if (Op.getValueType() == MVT::f32 &&
5138       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5139 
5140     // Put the exponent in the right bit position for later addition to the
5141     // final result:
5142     //
5143     // t0 = Op * log2(e)
5144 
5145     // TODO: What fast-math-flags should be set here?
5146     SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
5147                              DAG.getConstantFP(numbers::log2ef, dl, MVT::f32));
5148     return getLimitedPrecisionExp2(t0, dl, DAG);
5149   }
5150 
5151   // No special expansion.
5152   return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags);
5153 }
5154 
5155 /// expandLog - Lower a log intrinsic. Handles the special sequences for
5156 /// limited-precision mode.
5157 static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5158                          const TargetLowering &TLI, SDNodeFlags Flags) {
5159   // TODO: What fast-math-flags should be set on the floating-point nodes?
5160 
5161   if (Op.getValueType() == MVT::f32 &&
5162       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5163     SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5164 
5165     // Scale the exponent by log(2).
5166     SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
5167     SDValue LogOfExponent =
5168         DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5169                     DAG.getConstantFP(numbers::ln2f, dl, MVT::f32));
5170 
5171     // Get the significand and build it into a floating-point number with
5172     // exponent of 1.
5173     SDValue X = GetSignificand(DAG, Op1, dl);
5174 
5175     SDValue LogOfMantissa;
5176     if (LimitFloatPrecision <= 6) {
5177       // For floating-point precision of 6:
5178       //
5179       //   LogofMantissa =
5180       //     -1.1609546f +
5181       //       (1.4034025f - 0.23903021f * x) * x;
5182       //
5183       // error 0.0034276066, which is better than 8 bits
5184       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5185                                getF32Constant(DAG, 0xbe74c456, dl));
5186       SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5187                                getF32Constant(DAG, 0x3fb3a2b1, dl));
5188       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5189       LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5190                                   getF32Constant(DAG, 0x3f949a29, dl));
5191     } else if (LimitFloatPrecision <= 12) {
5192       // For floating-point precision of 12:
5193       //
5194       //   LogOfMantissa =
5195       //     -1.7417939f +
5196       //       (2.8212026f +
5197       //         (-1.4699568f +
5198       //           (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
5199       //
5200       // error 0.000061011436, which is 14 bits
5201       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5202                                getF32Constant(DAG, 0xbd67b6d6, dl));
5203       SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5204                                getF32Constant(DAG, 0x3ee4f4b8, dl));
5205       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5206       SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5207                                getF32Constant(DAG, 0x3fbc278b, dl));
5208       SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5209       SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5210                                getF32Constant(DAG, 0x40348e95, dl));
5211       SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5212       LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5213                                   getF32Constant(DAG, 0x3fdef31a, dl));
5214     } else { // LimitFloatPrecision <= 18
5215       // For floating-point precision of 18:
5216       //
5217       //   LogOfMantissa =
5218       //     -2.1072184f +
5219       //       (4.2372794f +
5220       //         (-3.7029485f +
5221       //           (2.2781945f +
5222       //             (-0.87823314f +
5223       //               (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
5224       //
5225       // error 0.0000023660568, which is better than 18 bits
5226       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5227                                getF32Constant(DAG, 0xbc91e5ac, dl));
5228       SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5229                                getF32Constant(DAG, 0x3e4350aa, dl));
5230       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5231       SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5232                                getF32Constant(DAG, 0x3f60d3e3, dl));
5233       SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5234       SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5235                                getF32Constant(DAG, 0x4011cdf0, dl));
5236       SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5237       SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5238                                getF32Constant(DAG, 0x406cfd1c, dl));
5239       SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5240       SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5241                                getF32Constant(DAG, 0x408797cb, dl));
5242       SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5243       LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5244                                   getF32Constant(DAG, 0x4006dcab, dl));
5245     }
5246 
5247     return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
5248   }
5249 
5250   // No special expansion.
5251   return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op, Flags);
5252 }
5253 
5254 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
5255 /// limited-precision mode.
5256 static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5257                           const TargetLowering &TLI, SDNodeFlags Flags) {
5258   // TODO: What fast-math-flags should be set on the floating-point nodes?
5259 
5260   if (Op.getValueType() == MVT::f32 &&
5261       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5262     SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5263 
5264     // Get the exponent.
5265     SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
5266 
5267     // Get the significand and build it into a floating-point number with
5268     // exponent of 1.
5269     SDValue X = GetSignificand(DAG, Op1, dl);
5270 
5271     // Different possible minimax approximations of significand in
5272     // floating-point for various degrees of accuracy over [1,2].
5273     SDValue Log2ofMantissa;
5274     if (LimitFloatPrecision <= 6) {
5275       // For floating-point precision of 6:
5276       //
5277       //   Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
5278       //
5279       // error 0.0049451742, which is more than 7 bits
5280       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5281                                getF32Constant(DAG, 0xbeb08fe0, dl));
5282       SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5283                                getF32Constant(DAG, 0x40019463, dl));
5284       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5285       Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5286                                    getF32Constant(DAG, 0x3fd6633d, dl));
5287     } else if (LimitFloatPrecision <= 12) {
5288       // For floating-point precision of 12:
5289       //
5290       //   Log2ofMantissa =
5291       //     -2.51285454f +
5292       //       (4.07009056f +
5293       //         (-2.12067489f +
5294       //           (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
5295       //
5296       // error 0.0000876136000, which is better than 13 bits
5297       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5298                                getF32Constant(DAG, 0xbda7262e, dl));
5299       SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5300                                getF32Constant(DAG, 0x3f25280b, dl));
5301       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5302       SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5303                                getF32Constant(DAG, 0x4007b923, dl));
5304       SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5305       SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5306                                getF32Constant(DAG, 0x40823e2f, dl));
5307       SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5308       Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5309                                    getF32Constant(DAG, 0x4020d29c, dl));
5310     } else { // LimitFloatPrecision <= 18
5311       // For floating-point precision of 18:
5312       //
5313       //   Log2ofMantissa =
5314       //     -3.0400495f +
5315       //       (6.1129976f +
5316       //         (-5.3420409f +
5317       //           (3.2865683f +
5318       //             (-1.2669343f +
5319       //               (0.27515199f -
5320       //                 0.25691327e-1f * x) * x) * x) * x) * x) * x;
5321       //
5322       // error 0.0000018516, which is better than 18 bits
5323       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5324                                getF32Constant(DAG, 0xbcd2769e, dl));
5325       SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5326                                getF32Constant(DAG, 0x3e8ce0b9, dl));
5327       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5328       SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5329                                getF32Constant(DAG, 0x3fa22ae7, dl));
5330       SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5331       SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5332                                getF32Constant(DAG, 0x40525723, dl));
5333       SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5334       SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5335                                getF32Constant(DAG, 0x40aaf200, dl));
5336       SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5337       SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5338                                getF32Constant(DAG, 0x40c39dad, dl));
5339       SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5340       Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5341                                    getF32Constant(DAG, 0x4042902c, dl));
5342     }
5343 
5344     return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5345   }
5346 
5347   // No special expansion.
5348   return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags);
5349 }
5350 
5351 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
5352 /// limited-precision mode.
5353 static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5354                            const TargetLowering &TLI, SDNodeFlags Flags) {
5355   // TODO: What fast-math-flags should be set on the floating-point nodes?
5356 
5357   if (Op.getValueType() == MVT::f32 &&
5358       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5359     SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5360 
5361     // Scale the exponent by log10(2) [0.30102999f].
5362     SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
5363     SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5364                                         getF32Constant(DAG, 0x3e9a209a, dl));
5365 
5366     // Get the significand and build it into a floating-point number with
5367     // exponent of 1.
5368     SDValue X = GetSignificand(DAG, Op1, dl);
5369 
5370     SDValue Log10ofMantissa;
5371     if (LimitFloatPrecision <= 6) {
5372       // For floating-point precision of 6:
5373       //
5374       //   Log10ofMantissa =
5375       //     -0.50419619f +
5376       //       (0.60948995f - 0.10380950f * x) * x;
5377       //
5378       // error 0.0014886165, which is 6 bits
5379       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5380                                getF32Constant(DAG, 0xbdd49a13, dl));
5381       SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5382                                getF32Constant(DAG, 0x3f1c0789, dl));
5383       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5384       Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5385                                     getF32Constant(DAG, 0x3f011300, dl));
5386     } else if (LimitFloatPrecision <= 12) {
5387       // For floating-point precision of 12:
5388       //
5389       //   Log10ofMantissa =
5390       //     -0.64831180f +
5391       //       (0.91751397f +
5392       //         (-0.31664806f + 0.47637168e-1f * x) * x) * x;
5393       //
5394       // error 0.00019228036, which is better than 12 bits
5395       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5396                                getF32Constant(DAG, 0x3d431f31, dl));
5397       SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5398                                getF32Constant(DAG, 0x3ea21fb2, dl));
5399       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5400       SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5401                                getF32Constant(DAG, 0x3f6ae232, dl));
5402       SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5403       Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5404                                     getF32Constant(DAG, 0x3f25f7c3, dl));
5405     } else { // LimitFloatPrecision <= 18
5406       // For floating-point precision of 18:
5407       //
5408       //   Log10ofMantissa =
5409       //     -0.84299375f +
5410       //       (1.5327582f +
5411       //         (-1.0688956f +
5412       //           (0.49102474f +
5413       //             (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
5414       //
5415       // error 0.0000037995730, which is better than 18 bits
5416       SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5417                                getF32Constant(DAG, 0x3c5d51ce, dl));
5418       SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5419                                getF32Constant(DAG, 0x3e00685a, dl));
5420       SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5421       SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5422                                getF32Constant(DAG, 0x3efb6798, dl));
5423       SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5424       SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5425                                getF32Constant(DAG, 0x3f88d192, dl));
5426       SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5427       SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5428                                getF32Constant(DAG, 0x3fc4316c, dl));
5429       SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5430       Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
5431                                     getF32Constant(DAG, 0x3f57ce70, dl));
5432     }
5433 
5434     return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
5435   }
5436 
5437   // No special expansion.
5438   return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op, Flags);
5439 }
5440 
5441 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
5442 /// limited-precision mode.
5443 static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5444                           const TargetLowering &TLI, SDNodeFlags Flags) {
5445   if (Op.getValueType() == MVT::f32 &&
5446       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
5447     return getLimitedPrecisionExp2(Op, dl, DAG);
5448 
5449   // No special expansion.
5450   return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags);
5451 }
5452 
5453 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
5454 /// limited-precision mode with x == 10.0f.
5455 static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
5456                          SelectionDAG &DAG, const TargetLowering &TLI,
5457                          SDNodeFlags Flags) {
5458   bool IsExp10 = false;
5459   if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
5460       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5461     if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
5462       APFloat Ten(10.0f);
5463       IsExp10 = LHSC->isExactlyValue(Ten);
5464     }
5465   }
5466 
5467   // TODO: What fast-math-flags should be set on the FMUL node?
5468   if (IsExp10) {
5469     // Put the exponent in the right bit position for later addition to the
5470     // final result:
5471     //
5472     //   #define LOG2OF10 3.3219281f
5473     //   t0 = Op * LOG2OF10;
5474     SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
5475                              getF32Constant(DAG, 0x40549a78, dl));
5476     return getLimitedPrecisionExp2(t0, dl, DAG);
5477   }
5478 
5479   // No special expansion.
5480   return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS, Flags);
5481 }
5482 
5483 /// ExpandPowI - Expand a llvm.powi intrinsic.
5484 static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
5485                           SelectionDAG &DAG) {
5486   // If RHS is a constant, we can expand this out to a multiplication tree if
5487   // it's beneficial on the target, otherwise we end up lowering to a call to
5488   // __powidf2 (for example).
5489   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
5490     unsigned Val = RHSC->getSExtValue();
5491 
5492     // powi(x, 0) -> 1.0
5493     if (Val == 0)
5494       return DAG.getConstantFP(1.0, DL, LHS.getValueType());
5495 
5496     if (DAG.getTargetLoweringInfo().isBeneficialToExpandPowI(
5497             Val, DAG.shouldOptForSize())) {
5498       // Get the exponent as a positive value.
5499       if ((int)Val < 0)
5500         Val = -Val;
5501       // We use the simple binary decomposition method to generate the multiply
5502       // sequence.  There are more optimal ways to do this (for example,
5503       // powi(x,15) generates one more multiply than it should), but this has
5504       // the benefit of being both really simple and much better than a libcall.
5505       SDValue Res; // Logically starts equal to 1.0
5506       SDValue CurSquare = LHS;
5507       // TODO: Intrinsics should have fast-math-flags that propagate to these
5508       // nodes.
5509       while (Val) {
5510         if (Val & 1) {
5511           if (Res.getNode())
5512             Res =
5513                 DAG.getNode(ISD::FMUL, DL, Res.getValueType(), Res, CurSquare);
5514           else
5515             Res = CurSquare; // 1.0*CurSquare.
5516         }
5517 
5518         CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
5519                                 CurSquare, CurSquare);
5520         Val >>= 1;
5521       }
5522 
5523       // If the original was negative, invert the result, producing 1/(x*x*x).
5524       if (RHSC->getSExtValue() < 0)
5525         Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
5526                           DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
5527       return Res;
5528     }
5529   }
5530 
5531   // Otherwise, expand to a libcall.
5532   return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
5533 }
5534 
5535 static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
5536                             SDValue LHS, SDValue RHS, SDValue Scale,
5537                             SelectionDAG &DAG, const TargetLowering &TLI) {
5538   EVT VT = LHS.getValueType();
5539   bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT;
5540   bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT;
5541   LLVMContext &Ctx = *DAG.getContext();
5542 
5543   // If the type is legal but the operation isn't, this node might survive all
5544   // the way to operation legalization. If we end up there and we do not have
5545   // the ability to widen the type (if VT*2 is not legal), we cannot expand the
5546   // node.
5547 
5548   // Coax the legalizer into expanding the node during type legalization instead
5549   // by bumping the size by one bit. This will force it to Promote, enabling the
5550   // early expansion and avoiding the need to expand later.
5551 
5552   // We don't have to do this if Scale is 0; that can always be expanded, unless
5553   // it's a saturating signed operation. Those can experience true integer
5554   // division overflow, a case which we must avoid.
5555 
5556   // FIXME: We wouldn't have to do this (or any of the early
5557   // expansion/promotion) if it was possible to expand a libcall of an
5558   // illegal type during operation legalization. But it's not, so things
5559   // get a bit hacky.
5560   unsigned ScaleInt = cast<ConstantSDNode>(Scale)->getZExtValue();
5561   if ((ScaleInt > 0 || (Saturating && Signed)) &&
5562       (TLI.isTypeLegal(VT) ||
5563        (VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) {
5564     TargetLowering::LegalizeAction Action = TLI.getFixedPointOperationAction(
5565         Opcode, VT, ScaleInt);
5566     if (Action != TargetLowering::Legal && Action != TargetLowering::Custom) {
5567       EVT PromVT;
5568       if (VT.isScalarInteger())
5569         PromVT = EVT::getIntegerVT(Ctx, VT.getSizeInBits() + 1);
5570       else if (VT.isVector()) {
5571         PromVT = VT.getVectorElementType();
5572         PromVT = EVT::getIntegerVT(Ctx, PromVT.getSizeInBits() + 1);
5573         PromVT = EVT::getVectorVT(Ctx, PromVT, VT.getVectorElementCount());
5574       } else
5575         llvm_unreachable("Wrong VT for DIVFIX?");
5576       LHS = DAG.getExtOrTrunc(Signed, LHS, DL, PromVT);
5577       RHS = DAG.getExtOrTrunc(Signed, RHS, DL, PromVT);
5578       EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout());
5579       // For saturating operations, we need to shift up the LHS to get the
5580       // proper saturation width, and then shift down again afterwards.
5581       if (Saturating)
5582         LHS = DAG.getNode(ISD::SHL, DL, PromVT, LHS,
5583                           DAG.getConstant(1, DL, ShiftTy));
5584       SDValue Res = DAG.getNode(Opcode, DL, PromVT, LHS, RHS, Scale);
5585       if (Saturating)
5586         Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, PromVT, Res,
5587                           DAG.getConstant(1, DL, ShiftTy));
5588       return DAG.getZExtOrTrunc(Res, DL, VT);
5589     }
5590   }
5591 
5592   return DAG.getNode(Opcode, DL, VT, LHS, RHS, Scale);
5593 }
5594 
5595 // getUnderlyingArgRegs - Find underlying registers used for a truncated,
5596 // bitcasted, or split argument. Returns a list of <Register, size in bits>
5597 static void
5598 getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, TypeSize>> &Regs,
5599                      const SDValue &N) {
5600   switch (N.getOpcode()) {
5601   case ISD::CopyFromReg: {
5602     SDValue Op = N.getOperand(1);
5603     Regs.emplace_back(cast<RegisterSDNode>(Op)->getReg(),
5604                       Op.getValueType().getSizeInBits());
5605     return;
5606   }
5607   case ISD::BITCAST:
5608   case ISD::AssertZext:
5609   case ISD::AssertSext:
5610   case ISD::TRUNCATE:
5611     getUnderlyingArgRegs(Regs, N.getOperand(0));
5612     return;
5613   case ISD::BUILD_PAIR:
5614   case ISD::BUILD_VECTOR:
5615   case ISD::CONCAT_VECTORS:
5616     for (SDValue Op : N->op_values())
5617       getUnderlyingArgRegs(Regs, Op);
5618     return;
5619   default:
5620     return;
5621   }
5622 }
5623 
5624 /// If the DbgValueInst is a dbg_value of a function argument, create the
5625 /// corresponding DBG_VALUE machine instruction for it now.  At the end of
5626 /// instruction selection, they will be inserted to the entry BB.
5627 /// We don't currently support this for variadic dbg_values, as they shouldn't
5628 /// appear for function arguments or in the prologue.
5629 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
5630     const Value *V, DILocalVariable *Variable, DIExpression *Expr,
5631     DILocation *DL, FuncArgumentDbgValueKind Kind, const SDValue &N) {
5632   const Argument *Arg = dyn_cast<Argument>(V);
5633   if (!Arg)
5634     return false;
5635 
5636   MachineFunction &MF = DAG.getMachineFunction();
5637   const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5638 
5639   // Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind
5640   // we've been asked to pursue.
5641   auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr,
5642                               bool Indirect) {
5643     if (Reg.isVirtual() && MF.useDebugInstrRef()) {
5644       // For VRegs, in instruction referencing mode, create a DBG_INSTR_REF
5645       // pointing at the VReg, which will be patched up later.
5646       auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF);
5647       SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
5648           /* Reg */ Reg, /* isDef */ false, /* isImp */ false,
5649           /* isKill */ false, /* isDead */ false,
5650           /* isUndef */ false, /* isEarlyClobber */ false,
5651           /* SubReg */ 0, /* isDebug */ true)});
5652 
5653       auto *NewDIExpr = FragExpr;
5654       // We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
5655       // the DIExpression.
5656       if (Indirect)
5657         NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore);
5658       SmallVector<uint64_t, 2> Ops({dwarf::DW_OP_LLVM_arg, 0});
5659       NewDIExpr = DIExpression::prependOpcodes(NewDIExpr, Ops);
5660       return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr);
5661     } else {
5662       // Create a completely standard DBG_VALUE.
5663       auto &Inst = TII->get(TargetOpcode::DBG_VALUE);
5664       return BuildMI(MF, DL, Inst, Indirect, Reg, Variable, FragExpr);
5665     }
5666   };
5667 
5668   if (Kind == FuncArgumentDbgValueKind::Value) {
5669     // ArgDbgValues are hoisted to the beginning of the entry block. So we
5670     // should only emit as ArgDbgValue if the dbg.value intrinsic is found in
5671     // the entry block.
5672     bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front();
5673     if (!IsInEntryBlock)
5674       return false;
5675 
5676     // ArgDbgValues are hoisted to the beginning of the entry block.  So we
5677     // should only emit as ArgDbgValue if the dbg.value intrinsic describes a
5678     // variable that also is a param.
5679     //
5680     // Although, if we are at the top of the entry block already, we can still
5681     // emit using ArgDbgValue. This might catch some situations when the
5682     // dbg.value refers to an argument that isn't used in the entry block, so
5683     // any CopyToReg node would be optimized out and the only way to express
5684     // this DBG_VALUE is by using the physical reg (or FI) as done in this
5685     // method.  ArgDbgValues are hoisted to the beginning of the entry block. So
5686     // we should only emit as ArgDbgValue if the Variable is an argument to the
5687     // current function, and the dbg.value intrinsic is found in the entry
5688     // block.
5689     bool VariableIsFunctionInputArg = Variable->isParameter() &&
5690         !DL->getInlinedAt();
5691     bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder;
5692     if (!IsInPrologue && !VariableIsFunctionInputArg)
5693       return false;
5694 
5695     // Here we assume that a function argument on IR level only can be used to
5696     // describe one input parameter on source level. If we for example have
5697     // source code like this
5698     //
5699     //    struct A { long x, y; };
5700     //    void foo(struct A a, long b) {
5701     //      ...
5702     //      b = a.x;
5703     //      ...
5704     //    }
5705     //
5706     // and IR like this
5707     //
5708     //  define void @foo(i32 %a1, i32 %a2, i32 %b)  {
5709     //  entry:
5710     //    call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment
5711     //    call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment
5712     //    call void @llvm.dbg.value(metadata i32 %b, "b",
5713     //    ...
5714     //    call void @llvm.dbg.value(metadata i32 %a1, "b"
5715     //    ...
5716     //
5717     // then the last dbg.value is describing a parameter "b" using a value that
5718     // is an argument. But since we already has used %a1 to describe a parameter
5719     // we should not handle that last dbg.value here (that would result in an
5720     // incorrect hoisting of the DBG_VALUE to the function entry).
5721     // Notice that we allow one dbg.value per IR level argument, to accommodate
5722     // for the situation with fragments above.
5723     if (VariableIsFunctionInputArg) {
5724       unsigned ArgNo = Arg->getArgNo();
5725       if (ArgNo >= FuncInfo.DescribedArgs.size())
5726         FuncInfo.DescribedArgs.resize(ArgNo + 1, false);
5727       else if (!IsInPrologue && FuncInfo.DescribedArgs.test(ArgNo))
5728         return false;
5729       FuncInfo.DescribedArgs.set(ArgNo);
5730     }
5731   }
5732 
5733   bool IsIndirect = false;
5734   std::optional<MachineOperand> Op;
5735   // Some arguments' frame index is recorded during argument lowering.
5736   int FI = FuncInfo.getArgumentFrameIndex(Arg);
5737   if (FI != std::numeric_limits<int>::max())
5738     Op = MachineOperand::CreateFI(FI);
5739 
5740   SmallVector<std::pair<unsigned, TypeSize>, 8> ArgRegsAndSizes;
5741   if (!Op && N.getNode()) {
5742     getUnderlyingArgRegs(ArgRegsAndSizes, N);
5743     Register Reg;
5744     if (ArgRegsAndSizes.size() == 1)
5745       Reg = ArgRegsAndSizes.front().first;
5746 
5747     if (Reg && Reg.isVirtual()) {
5748       MachineRegisterInfo &RegInfo = MF.getRegInfo();
5749       Register PR = RegInfo.getLiveInPhysReg(Reg);
5750       if (PR)
5751         Reg = PR;
5752     }
5753     if (Reg) {
5754       Op = MachineOperand::CreateReg(Reg, false);
5755       IsIndirect = Kind != FuncArgumentDbgValueKind::Value;
5756     }
5757   }
5758 
5759   if (!Op && N.getNode()) {
5760     // Check if frame index is available.
5761     SDValue LCandidate = peekThroughBitcasts(N);
5762     if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(LCandidate.getNode()))
5763       if (FrameIndexSDNode *FINode =
5764           dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
5765         Op = MachineOperand::CreateFI(FINode->getIndex());
5766   }
5767 
5768   if (!Op) {
5769     // Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg
5770     auto splitMultiRegDbgValue = [&](ArrayRef<std::pair<unsigned, TypeSize>>
5771                                          SplitRegs) {
5772       unsigned Offset = 0;
5773       for (const auto &RegAndSize : SplitRegs) {
5774         // If the expression is already a fragment, the current register
5775         // offset+size might extend beyond the fragment. In this case, only
5776         // the register bits that are inside the fragment are relevant.
5777         int RegFragmentSizeInBits = RegAndSize.second;
5778         if (auto ExprFragmentInfo = Expr->getFragmentInfo()) {
5779           uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;
5780           // The register is entirely outside the expression fragment,
5781           // so is irrelevant for debug info.
5782           if (Offset >= ExprFragmentSizeInBits)
5783             break;
5784           // The register is partially outside the expression fragment, only
5785           // the low bits within the fragment are relevant for debug info.
5786           if (Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) {
5787             RegFragmentSizeInBits = ExprFragmentSizeInBits - Offset;
5788           }
5789         }
5790 
5791         auto FragmentExpr = DIExpression::createFragmentExpression(
5792             Expr, Offset, RegFragmentSizeInBits);
5793         Offset += RegAndSize.second;
5794         // If a valid fragment expression cannot be created, the variable's
5795         // correct value cannot be determined and so it is set as Undef.
5796         if (!FragmentExpr) {
5797           SDDbgValue *SDV = DAG.getConstantDbgValue(
5798               Variable, Expr, UndefValue::get(V->getType()), DL, SDNodeOrder);
5799           DAG.AddDbgValue(SDV, false);
5800           continue;
5801         }
5802         MachineInstr *NewMI =
5803             MakeVRegDbgValue(RegAndSize.first, *FragmentExpr,
5804                              Kind != FuncArgumentDbgValueKind::Value);
5805         FuncInfo.ArgDbgValues.push_back(NewMI);
5806       }
5807     };
5808 
5809     // Check if ValueMap has reg number.
5810     DenseMap<const Value *, Register>::const_iterator
5811       VMI = FuncInfo.ValueMap.find(V);
5812     if (VMI != FuncInfo.ValueMap.end()) {
5813       const auto &TLI = DAG.getTargetLoweringInfo();
5814       RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
5815                        V->getType(), std::nullopt);
5816       if (RFV.occupiesMultipleRegs()) {
5817         splitMultiRegDbgValue(RFV.getRegsAndSizes());
5818         return true;
5819       }
5820 
5821       Op = MachineOperand::CreateReg(VMI->second, false);
5822       IsIndirect = Kind != FuncArgumentDbgValueKind::Value;
5823     } else if (ArgRegsAndSizes.size() > 1) {
5824       // This was split due to the calling convention, and no virtual register
5825       // mapping exists for the value.
5826       splitMultiRegDbgValue(ArgRegsAndSizes);
5827       return true;
5828     }
5829   }
5830 
5831   if (!Op)
5832     return false;
5833 
5834   assert(Variable->isValidLocationForIntrinsic(DL) &&
5835          "Expected inlined-at fields to agree");
5836   MachineInstr *NewMI = nullptr;
5837 
5838   if (Op->isReg())
5839     NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect);
5840   else
5841     NewMI = BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), true, *Op,
5842                     Variable, Expr);
5843 
5844   // Otherwise, use ArgDbgValues.
5845   FuncInfo.ArgDbgValues.push_back(NewMI);
5846   return true;
5847 }
5848 
5849 /// Return the appropriate SDDbgValue based on N.
5850 SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
5851                                              DILocalVariable *Variable,
5852                                              DIExpression *Expr,
5853                                              const DebugLoc &dl,
5854                                              unsigned DbgSDNodeOrder) {
5855   if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) {
5856     // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
5857     // stack slot locations.
5858     //
5859     // Consider "int x = 0; int *px = &x;". There are two kinds of interesting
5860     // debug values here after optimization:
5861     //
5862     //   dbg.value(i32* %px, !"int *px", !DIExpression()), and
5863     //   dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
5864     //
5865     // Both describe the direct values of their associated variables.
5866     return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(),
5867                                      /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5868   }
5869   return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(),
5870                          /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5871 }
5872 
5873 static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) {
5874   switch (Intrinsic) {
5875   case Intrinsic::smul_fix:
5876     return ISD::SMULFIX;
5877   case Intrinsic::umul_fix:
5878     return ISD::UMULFIX;
5879   case Intrinsic::smul_fix_sat:
5880     return ISD::SMULFIXSAT;
5881   case Intrinsic::umul_fix_sat:
5882     return ISD::UMULFIXSAT;
5883   case Intrinsic::sdiv_fix:
5884     return ISD::SDIVFIX;
5885   case Intrinsic::udiv_fix:
5886     return ISD::UDIVFIX;
5887   case Intrinsic::sdiv_fix_sat:
5888     return ISD::SDIVFIXSAT;
5889   case Intrinsic::udiv_fix_sat:
5890     return ISD::UDIVFIXSAT;
5891   default:
5892     llvm_unreachable("Unhandled fixed point intrinsic");
5893   }
5894 }
5895 
5896 void SelectionDAGBuilder::lowerCallToExternalSymbol(const CallInst &I,
5897                                            const char *FunctionName) {
5898   assert(FunctionName && "FunctionName must not be nullptr");
5899   SDValue Callee = DAG.getExternalSymbol(
5900       FunctionName,
5901       DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5902   LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall());
5903 }
5904 
5905 /// Given a @llvm.call.preallocated.setup, return the corresponding
5906 /// preallocated call.
5907 static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) {
5908   assert(cast<CallBase>(PreallocatedSetup)
5909                  ->getCalledFunction()
5910                  ->getIntrinsicID() == Intrinsic::call_preallocated_setup &&
5911          "expected call_preallocated_setup Value");
5912   for (const auto *U : PreallocatedSetup->users()) {
5913     auto *UseCall = cast<CallBase>(U);
5914     const Function *Fn = UseCall->getCalledFunction();
5915     if (!Fn || Fn->getIntrinsicID() != Intrinsic::call_preallocated_arg) {
5916       return UseCall;
5917     }
5918   }
5919   llvm_unreachable("expected corresponding call to preallocated setup/arg");
5920 }
5921 
5922 /// If DI is a debug value with an EntryValue expression, lower it using the
5923 /// corresponding physical register of the associated Argument value
5924 /// (guaranteed to exist by the verifier).
5925 bool SelectionDAGBuilder::visitEntryValueDbgValue(const DbgValueInst &DI) {
5926   DILocalVariable *Variable = DI.getVariable();
5927   DIExpression *Expr = DI.getExpression();
5928   if (!Expr->isEntryValue() || !hasSingleElement(DI.getValues()))
5929     return false;
5930 
5931   // These properties are guaranteed by the verifier.
5932   Argument *Arg = cast<Argument>(DI.getValue(0));
5933   assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync));
5934 
5935   auto ArgIt = FuncInfo.ValueMap.find(Arg);
5936   if (ArgIt == FuncInfo.ValueMap.end()) {
5937     LLVM_DEBUG(
5938         dbgs() << "Dropping dbg.value: expression is entry_value but "
5939                   "couldn't find an associated register for the Argument\n");
5940     return true;
5941   }
5942   Register ArgVReg = ArgIt->getSecond();
5943 
5944   for (auto [PhysReg, VirtReg] : FuncInfo.RegInfo->liveins())
5945     if (ArgVReg == VirtReg || ArgVReg == PhysReg) {
5946       SDDbgValue *SDV =
5947           DAG.getVRegDbgValue(Variable, Expr, PhysReg, false /*IsIndidrect*/,
5948                               DI.getDebugLoc(), SDNodeOrder);
5949       DAG.AddDbgValue(SDV, false /*treat as dbg.declare byval parameter*/);
5950       return true;
5951     }
5952   LLVM_DEBUG(dbgs() << "Dropping dbg.value: expression is entry_value but "
5953                        "couldn't find a physical register\n");
5954   return true;
5955 }
5956 
5957 /// Lower the call to the specified intrinsic function.
5958 void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
5959                                              unsigned Intrinsic) {
5960   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5961   SDLoc sdl = getCurSDLoc();
5962   DebugLoc dl = getCurDebugLoc();
5963   SDValue Res;
5964 
5965   SDNodeFlags Flags;
5966   if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
5967     Flags.copyFMF(*FPOp);
5968 
5969   switch (Intrinsic) {
5970   default:
5971     // By default, turn this into a target intrinsic node.
5972     visitTargetIntrinsic(I, Intrinsic);
5973     return;
5974   case Intrinsic::vscale: {
5975     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5976     setValue(&I, DAG.getVScale(sdl, VT, APInt(VT.getSizeInBits(), 1)));
5977     return;
5978   }
5979   case Intrinsic::vastart:  visitVAStart(I); return;
5980   case Intrinsic::vaend:    visitVAEnd(I); return;
5981   case Intrinsic::vacopy:   visitVACopy(I); return;
5982   case Intrinsic::returnaddress:
5983     setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
5984                              TLI.getValueType(DAG.getDataLayout(), I.getType()),
5985                              getValue(I.getArgOperand(0))));
5986     return;
5987   case Intrinsic::addressofreturnaddress:
5988     setValue(&I,
5989              DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
5990                          TLI.getValueType(DAG.getDataLayout(), I.getType())));
5991     return;
5992   case Intrinsic::sponentry:
5993     setValue(&I,
5994              DAG.getNode(ISD::SPONENTRY, sdl,
5995                          TLI.getValueType(DAG.getDataLayout(), I.getType())));
5996     return;
5997   case Intrinsic::frameaddress:
5998     setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
5999                              TLI.getFrameIndexTy(DAG.getDataLayout()),
6000                              getValue(I.getArgOperand(0))));
6001     return;
6002   case Intrinsic::read_volatile_register:
6003   case Intrinsic::read_register: {
6004     Value *Reg = I.getArgOperand(0);
6005     SDValue Chain = getRoot();
6006     SDValue RegName =
6007         DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6008     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6009     Res = DAG.getNode(ISD::READ_REGISTER, sdl,
6010       DAG.getVTList(VT, MVT::Other), Chain, RegName);
6011     setValue(&I, Res);
6012     DAG.setRoot(Res.getValue(1));
6013     return;
6014   }
6015   case Intrinsic::write_register: {
6016     Value *Reg = I.getArgOperand(0);
6017     Value *RegValue = I.getArgOperand(1);
6018     SDValue Chain = getRoot();
6019     SDValue RegName =
6020         DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6021     DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
6022                             RegName, getValue(RegValue)));
6023     return;
6024   }
6025   case Intrinsic::memcpy: {
6026     const auto &MCI = cast<MemCpyInst>(I);
6027     SDValue Op1 = getValue(I.getArgOperand(0));
6028     SDValue Op2 = getValue(I.getArgOperand(1));
6029     SDValue Op3 = getValue(I.getArgOperand(2));
6030     // @llvm.memcpy defines 0 and 1 to both mean no alignment.
6031     Align DstAlign = MCI.getDestAlign().valueOrOne();
6032     Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6033     Align Alignment = std::min(DstAlign, SrcAlign);
6034     bool isVol = MCI.isVolatile();
6035     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6036     // FIXME: Support passing different dest/src alignments to the memcpy DAG
6037     // node.
6038     SDValue Root = isVol ? getRoot() : getMemoryRoot();
6039     SDValue MC = DAG.getMemcpy(
6040         Root, sdl, Op1, Op2, Op3, Alignment, isVol,
6041         /* AlwaysInline */ false, isTC, MachinePointerInfo(I.getArgOperand(0)),
6042         MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata(), AA);
6043     updateDAGForMaybeTailCall(MC);
6044     return;
6045   }
6046   case Intrinsic::memcpy_inline: {
6047     const auto &MCI = cast<MemCpyInlineInst>(I);
6048     SDValue Dst = getValue(I.getArgOperand(0));
6049     SDValue Src = getValue(I.getArgOperand(1));
6050     SDValue Size = getValue(I.getArgOperand(2));
6051     assert(isa<ConstantSDNode>(Size) && "memcpy_inline needs constant size");
6052     // @llvm.memcpy.inline defines 0 and 1 to both mean no alignment.
6053     Align DstAlign = MCI.getDestAlign().valueOrOne();
6054     Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6055     Align Alignment = std::min(DstAlign, SrcAlign);
6056     bool isVol = MCI.isVolatile();
6057     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6058     // FIXME: Support passing different dest/src alignments to the memcpy DAG
6059     // node.
6060     SDValue MC = DAG.getMemcpy(
6061         getRoot(), sdl, Dst, Src, Size, Alignment, isVol,
6062         /* AlwaysInline */ true, isTC, MachinePointerInfo(I.getArgOperand(0)),
6063         MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata(), AA);
6064     updateDAGForMaybeTailCall(MC);
6065     return;
6066   }
6067   case Intrinsic::memset: {
6068     const auto &MSI = cast<MemSetInst>(I);
6069     SDValue Op1 = getValue(I.getArgOperand(0));
6070     SDValue Op2 = getValue(I.getArgOperand(1));
6071     SDValue Op3 = getValue(I.getArgOperand(2));
6072     // @llvm.memset defines 0 and 1 to both mean no alignment.
6073     Align Alignment = MSI.getDestAlign().valueOrOne();
6074     bool isVol = MSI.isVolatile();
6075     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6076     SDValue Root = isVol ? getRoot() : getMemoryRoot();
6077     SDValue MS = DAG.getMemset(
6078         Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false,
6079         isTC, MachinePointerInfo(I.getArgOperand(0)), I.getAAMetadata());
6080     updateDAGForMaybeTailCall(MS);
6081     return;
6082   }
6083   case Intrinsic::memset_inline: {
6084     const auto &MSII = cast<MemSetInlineInst>(I);
6085     SDValue Dst = getValue(I.getArgOperand(0));
6086     SDValue Value = getValue(I.getArgOperand(1));
6087     SDValue Size = getValue(I.getArgOperand(2));
6088     assert(isa<ConstantSDNode>(Size) && "memset_inline needs constant size");
6089     // @llvm.memset defines 0 and 1 to both mean no alignment.
6090     Align DstAlign = MSII.getDestAlign().valueOrOne();
6091     bool isVol = MSII.isVolatile();
6092     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6093     SDValue Root = isVol ? getRoot() : getMemoryRoot();
6094     SDValue MC = DAG.getMemset(Root, sdl, Dst, Value, Size, DstAlign, isVol,
6095                                /* AlwaysInline */ true, isTC,
6096                                MachinePointerInfo(I.getArgOperand(0)),
6097                                I.getAAMetadata());
6098     updateDAGForMaybeTailCall(MC);
6099     return;
6100   }
6101   case Intrinsic::memmove: {
6102     const auto &MMI = cast<MemMoveInst>(I);
6103     SDValue Op1 = getValue(I.getArgOperand(0));
6104     SDValue Op2 = getValue(I.getArgOperand(1));
6105     SDValue Op3 = getValue(I.getArgOperand(2));
6106     // @llvm.memmove defines 0 and 1 to both mean no alignment.
6107     Align DstAlign = MMI.getDestAlign().valueOrOne();
6108     Align SrcAlign = MMI.getSourceAlign().valueOrOne();
6109     Align Alignment = std::min(DstAlign, SrcAlign);
6110     bool isVol = MMI.isVolatile();
6111     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6112     // FIXME: Support passing different dest/src alignments to the memmove DAG
6113     // node.
6114     SDValue Root = isVol ? getRoot() : getMemoryRoot();
6115     SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol,
6116                                 isTC, MachinePointerInfo(I.getArgOperand(0)),
6117                                 MachinePointerInfo(I.getArgOperand(1)),
6118                                 I.getAAMetadata(), AA);
6119     updateDAGForMaybeTailCall(MM);
6120     return;
6121   }
6122   case Intrinsic::memcpy_element_unordered_atomic: {
6123     const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I);
6124     SDValue Dst = getValue(MI.getRawDest());
6125     SDValue Src = getValue(MI.getRawSource());
6126     SDValue Length = getValue(MI.getLength());
6127 
6128     Type *LengthTy = MI.getLength()->getType();
6129     unsigned ElemSz = MI.getElementSizeInBytes();
6130     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6131     SDValue MC =
6132         DAG.getAtomicMemcpy(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz,
6133                             isTC, MachinePointerInfo(MI.getRawDest()),
6134                             MachinePointerInfo(MI.getRawSource()));
6135     updateDAGForMaybeTailCall(MC);
6136     return;
6137   }
6138   case Intrinsic::memmove_element_unordered_atomic: {
6139     auto &MI = cast<AtomicMemMoveInst>(I);
6140     SDValue Dst = getValue(MI.getRawDest());
6141     SDValue Src = getValue(MI.getRawSource());
6142     SDValue Length = getValue(MI.getLength());
6143 
6144     Type *LengthTy = MI.getLength()->getType();
6145     unsigned ElemSz = MI.getElementSizeInBytes();
6146     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6147     SDValue MC =
6148         DAG.getAtomicMemmove(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz,
6149                              isTC, MachinePointerInfo(MI.getRawDest()),
6150                              MachinePointerInfo(MI.getRawSource()));
6151     updateDAGForMaybeTailCall(MC);
6152     return;
6153   }
6154   case Intrinsic::memset_element_unordered_atomic: {
6155     auto &MI = cast<AtomicMemSetInst>(I);
6156     SDValue Dst = getValue(MI.getRawDest());
6157     SDValue Val = getValue(MI.getValue());
6158     SDValue Length = getValue(MI.getLength());
6159 
6160     Type *LengthTy = MI.getLength()->getType();
6161     unsigned ElemSz = MI.getElementSizeInBytes();
6162     bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
6163     SDValue MC =
6164         DAG.getAtomicMemset(getRoot(), sdl, Dst, Val, Length, LengthTy, ElemSz,
6165                             isTC, MachinePointerInfo(MI.getRawDest()));
6166     updateDAGForMaybeTailCall(MC);
6167     return;
6168   }
6169   case Intrinsic::call_preallocated_setup: {
6170     const CallBase *PreallocatedCall = FindPreallocatedCall(&I);
6171     SDValue SrcValue = DAG.getSrcValue(PreallocatedCall);
6172     SDValue Res = DAG.getNode(ISD::PREALLOCATED_SETUP, sdl, MVT::Other,
6173                               getRoot(), SrcValue);
6174     setValue(&I, Res);
6175     DAG.setRoot(Res);
6176     return;
6177   }
6178   case Intrinsic::call_preallocated_arg: {
6179     const CallBase *PreallocatedCall = FindPreallocatedCall(I.getOperand(0));
6180     SDValue SrcValue = DAG.getSrcValue(PreallocatedCall);
6181     SDValue Ops[3];
6182     Ops[0] = getRoot();
6183     Ops[1] = SrcValue;
6184     Ops[2] = DAG.getTargetConstant(*cast<ConstantInt>(I.getArgOperand(1)), sdl,
6185                                    MVT::i32); // arg index
6186     SDValue Res = DAG.getNode(
6187         ISD::PREALLOCATED_ARG, sdl,
6188         DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Ops);
6189     setValue(&I, Res);
6190     DAG.setRoot(Res.getValue(1));
6191     return;
6192   }
6193   case Intrinsic::dbg_declare: {
6194     const auto &DI = cast<DbgDeclareInst>(I);
6195     // Debug intrinsics are handled separately in assignment tracking mode.
6196     // Some intrinsics are handled right after Argument lowering.
6197     if (AssignmentTrackingEnabled ||
6198         FuncInfo.PreprocessedDbgDeclares.count(&DI))
6199       return;
6200     // Assume dbg.declare can not currently use DIArgList, i.e.
6201     // it is non-variadic.
6202     assert(!DI.hasArgList() && "Only dbg.value should currently use DIArgList");
6203     DILocalVariable *Variable = DI.getVariable();
6204     DIExpression *Expression = DI.getExpression();
6205     dropDanglingDebugInfo(Variable, Expression);
6206     assert(Variable && "Missing variable");
6207     LLVM_DEBUG(dbgs() << "SelectionDAG visiting debug intrinsic: " << DI
6208                       << "\n");
6209     // Check if address has undef value.
6210     const Value *Address = DI.getVariableLocationOp(0);
6211     if (!Address || isa<UndefValue>(Address) ||
6212         (Address->use_empty() && !isa<Argument>(Address))) {
6213       LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI
6214                         << " (bad/undef/unused-arg address)\n");
6215       return;
6216     }
6217 
6218     bool isParameter = Variable->isParameter() || isa<Argument>(Address);
6219 
6220     SDValue &N = NodeMap[Address];
6221     if (!N.getNode() && isa<Argument>(Address))
6222       // Check unused arguments map.
6223       N = UnusedArgNodeMap[Address];
6224     SDDbgValue *SDV;
6225     if (N.getNode()) {
6226       if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
6227         Address = BCI->getOperand(0);
6228       // Parameters are handled specially.
6229       auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
6230       if (isParameter && FINode) {
6231         // Byval parameter. We have a frame index at this point.
6232         SDV =
6233             DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(),
6234                                       /*IsIndirect*/ true, dl, SDNodeOrder);
6235       } else if (isa<Argument>(Address)) {
6236         // Address is an argument, so try to emit its dbg value using
6237         // virtual register info from the FuncInfo.ValueMap.
6238         EmitFuncArgumentDbgValue(Address, Variable, Expression, dl,
6239                                  FuncArgumentDbgValueKind::Declare, N);
6240         return;
6241       } else {
6242         SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
6243                               true, dl, SDNodeOrder);
6244       }
6245       DAG.AddDbgValue(SDV, isParameter);
6246     } else {
6247       // If Address is an argument then try to emit its dbg value using
6248       // virtual register info from the FuncInfo.ValueMap.
6249       if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl,
6250                                     FuncArgumentDbgValueKind::Declare, N)) {
6251         LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI
6252                           << " (could not emit func-arg dbg_value)\n");
6253       }
6254     }
6255     return;
6256   }
6257   case Intrinsic::dbg_label: {
6258     const DbgLabelInst &DI = cast<DbgLabelInst>(I);
6259     DILabel *Label = DI.getLabel();
6260     assert(Label && "Missing label");
6261 
6262     SDDbgLabel *SDV;
6263     SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder);
6264     DAG.AddDbgLabel(SDV);
6265     return;
6266   }
6267   case Intrinsic::dbg_assign: {
6268     // Debug intrinsics are handled seperately in assignment tracking mode.
6269     if (AssignmentTrackingEnabled)
6270       return;
6271     // If assignment tracking hasn't been enabled then fall through and treat
6272     // the dbg.assign as a dbg.value.
6273     [[fallthrough]];
6274   }
6275   case Intrinsic::dbg_value: {
6276     // Debug intrinsics are handled seperately in assignment tracking mode.
6277     if (AssignmentTrackingEnabled)
6278       return;
6279     const DbgValueInst &DI = cast<DbgValueInst>(I);
6280     assert(DI.getVariable() && "Missing variable");
6281 
6282     DILocalVariable *Variable = DI.getVariable();
6283     DIExpression *Expression = DI.getExpression();
6284     dropDanglingDebugInfo(Variable, Expression);
6285 
6286     if (visitEntryValueDbgValue(DI))
6287       return;
6288 
6289     if (DI.isKillLocation()) {
6290       handleKillDebugValue(Variable, Expression, DI.getDebugLoc(), SDNodeOrder);
6291       return;
6292     }
6293 
6294     SmallVector<Value *, 4> Values(DI.getValues());
6295     if (Values.empty())
6296       return;
6297 
6298     bool IsVariadic = DI.hasArgList();
6299     if (!handleDebugValue(Values, Variable, Expression, DI.getDebugLoc(),
6300                           SDNodeOrder, IsVariadic))
6301       addDanglingDebugInfo(&DI, SDNodeOrder);
6302     return;
6303   }
6304 
6305   case Intrinsic::eh_typeid_for: {
6306     // Find the type id for the given typeinfo.
6307     GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
6308     unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV);
6309     Res = DAG.getConstant(TypeID, sdl, MVT::i32);
6310     setValue(&I, Res);
6311     return;
6312   }
6313 
6314   case Intrinsic::eh_return_i32:
6315   case Intrinsic::eh_return_i64:
6316     DAG.getMachineFunction().setCallsEHReturn(true);
6317     DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
6318                             MVT::Other,
6319                             getControlRoot(),
6320                             getValue(I.getArgOperand(0)),
6321                             getValue(I.getArgOperand(1))));
6322     return;
6323   case Intrinsic::eh_unwind_init:
6324     DAG.getMachineFunction().setCallsUnwindInit(true);
6325     return;
6326   case Intrinsic::eh_dwarf_cfa:
6327     setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl,
6328                              TLI.getPointerTy(DAG.getDataLayout()),
6329                              getValue(I.getArgOperand(0))));
6330     return;
6331   case Intrinsic::eh_sjlj_callsite: {
6332     MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6333     ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(0));
6334     assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
6335 
6336     MMI.setCurrentCallSite(CI->getZExtValue());
6337     return;
6338   }
6339   case Intrinsic::eh_sjlj_functioncontext: {
6340     // Get and store the index of the function context.
6341     MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
6342     AllocaInst *FnCtx =
6343       cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
6344     int FI = FuncInfo.StaticAllocaMap[FnCtx];
6345     MFI.setFunctionContextIndex(FI);
6346     return;
6347   }
6348   case Intrinsic::eh_sjlj_setjmp: {
6349     SDValue Ops[2];
6350     Ops[0] = getRoot();
6351     Ops[1] = getValue(I.getArgOperand(0));
6352     SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
6353                              DAG.getVTList(MVT::i32, MVT::Other), Ops);
6354     setValue(&I, Op.getValue(0));
6355     DAG.setRoot(Op.getValue(1));
6356     return;
6357   }
6358   case Intrinsic::eh_sjlj_longjmp:
6359     DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
6360                             getRoot(), getValue(I.getArgOperand(0))));
6361     return;
6362   case Intrinsic::eh_sjlj_setup_dispatch:
6363     DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
6364                             getRoot()));
6365     return;
6366   case Intrinsic::masked_gather:
6367     visitMaskedGather(I);
6368     return;
6369   case Intrinsic::masked_load:
6370     visitMaskedLoad(I);
6371     return;
6372   case Intrinsic::masked_scatter:
6373     visitMaskedScatter(I);
6374     return;
6375   case Intrinsic::masked_store:
6376     visitMaskedStore(I);
6377     return;
6378   case Intrinsic::masked_expandload:
6379     visitMaskedLoad(I, true /* IsExpanding */);
6380     return;
6381   case Intrinsic::masked_compressstore:
6382     visitMaskedStore(I, true /* IsCompressing */);
6383     return;
6384   case Intrinsic::powi:
6385     setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
6386                             getValue(I.getArgOperand(1)), DAG));
6387     return;
6388   case Intrinsic::log:
6389     setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags));
6390     return;
6391   case Intrinsic::log2:
6392     setValue(&I,
6393              expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags));
6394     return;
6395   case Intrinsic::log10:
6396     setValue(&I,
6397              expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags));
6398     return;
6399   case Intrinsic::exp:
6400     setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags));
6401     return;
6402   case Intrinsic::exp2:
6403     setValue(&I,
6404              expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags));
6405     return;
6406   case Intrinsic::pow:
6407     setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
6408                            getValue(I.getArgOperand(1)), DAG, TLI, Flags));
6409     return;
6410   case Intrinsic::sqrt:
6411   case Intrinsic::fabs:
6412   case Intrinsic::sin:
6413   case Intrinsic::cos:
6414   case Intrinsic::exp10:
6415   case Intrinsic::floor:
6416   case Intrinsic::ceil:
6417   case Intrinsic::trunc:
6418   case Intrinsic::rint:
6419   case Intrinsic::nearbyint:
6420   case Intrinsic::round:
6421   case Intrinsic::roundeven:
6422   case Intrinsic::canonicalize: {
6423     unsigned Opcode;
6424     switch (Intrinsic) {
6425     default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
6426     case Intrinsic::sqrt:      Opcode = ISD::FSQRT;      break;
6427     case Intrinsic::fabs:      Opcode = ISD::FABS;       break;
6428     case Intrinsic::sin:       Opcode = ISD::FSIN;       break;
6429     case Intrinsic::cos:       Opcode = ISD::FCOS;       break;
6430     case Intrinsic::exp10:     Opcode = ISD::FEXP10;     break;
6431     case Intrinsic::floor:     Opcode = ISD::FFLOOR;     break;
6432     case Intrinsic::ceil:      Opcode = ISD::FCEIL;      break;
6433     case Intrinsic::trunc:     Opcode = ISD::FTRUNC;     break;
6434     case Intrinsic::rint:      Opcode = ISD::FRINT;      break;
6435     case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
6436     case Intrinsic::round:     Opcode = ISD::FROUND;     break;
6437     case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break;
6438     case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
6439     }
6440 
6441     setValue(&I, DAG.getNode(Opcode, sdl,
6442                              getValue(I.getArgOperand(0)).getValueType(),
6443                              getValue(I.getArgOperand(0)), Flags));
6444     return;
6445   }
6446   case Intrinsic::lround:
6447   case Intrinsic::llround:
6448   case Intrinsic::lrint:
6449   case Intrinsic::llrint: {
6450     unsigned Opcode;
6451     switch (Intrinsic) {
6452     default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
6453     case Intrinsic::lround:  Opcode = ISD::LROUND;  break;
6454     case Intrinsic::llround: Opcode = ISD::LLROUND; break;
6455     case Intrinsic::lrint:   Opcode = ISD::LRINT;   break;
6456     case Intrinsic::llrint:  Opcode = ISD::LLRINT;  break;
6457     }
6458 
6459     EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6460     setValue(&I, DAG.getNode(Opcode, sdl, RetVT,
6461                              getValue(I.getArgOperand(0))));
6462     return;
6463   }
6464   case Intrinsic::minnum:
6465     setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
6466                              getValue(I.getArgOperand(0)).getValueType(),
6467                              getValue(I.getArgOperand(0)),
6468                              getValue(I.getArgOperand(1)), Flags));
6469     return;
6470   case Intrinsic::maxnum:
6471     setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
6472                              getValue(I.getArgOperand(0)).getValueType(),
6473                              getValue(I.getArgOperand(0)),
6474                              getValue(I.getArgOperand(1)), Flags));
6475     return;
6476   case Intrinsic::minimum:
6477     setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl,
6478                              getValue(I.getArgOperand(0)).getValueType(),
6479                              getValue(I.getArgOperand(0)),
6480                              getValue(I.getArgOperand(1)), Flags));
6481     return;
6482   case Intrinsic::maximum:
6483     setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl,
6484                              getValue(I.getArgOperand(0)).getValueType(),
6485                              getValue(I.getArgOperand(0)),
6486                              getValue(I.getArgOperand(1)), Flags));
6487     return;
6488   case Intrinsic::copysign:
6489     setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
6490                              getValue(I.getArgOperand(0)).getValueType(),
6491                              getValue(I.getArgOperand(0)),
6492                              getValue(I.getArgOperand(1)), Flags));
6493     return;
6494   case Intrinsic::ldexp:
6495     setValue(&I, DAG.getNode(ISD::FLDEXP, sdl,
6496                              getValue(I.getArgOperand(0)).getValueType(),
6497                              getValue(I.getArgOperand(0)),
6498                              getValue(I.getArgOperand(1)), Flags));
6499     return;
6500   case Intrinsic::frexp: {
6501     SmallVector<EVT, 2> ValueVTs;
6502     ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
6503     SDVTList VTs = DAG.getVTList(ValueVTs);
6504     setValue(&I,
6505              DAG.getNode(ISD::FFREXP, sdl, VTs, getValue(I.getArgOperand(0))));
6506     return;
6507   }
6508   case Intrinsic::arithmetic_fence: {
6509     setValue(&I, DAG.getNode(ISD::ARITH_FENCE, sdl,
6510                              getValue(I.getArgOperand(0)).getValueType(),
6511                              getValue(I.getArgOperand(0)), Flags));
6512     return;
6513   }
6514   case Intrinsic::fma:
6515     setValue(&I, DAG.getNode(
6516                      ISD::FMA, sdl, getValue(I.getArgOperand(0)).getValueType(),
6517                      getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
6518                      getValue(I.getArgOperand(2)), Flags));
6519     return;
6520 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC)                         \
6521   case Intrinsic::INTRINSIC:
6522 #include "llvm/IR/ConstrainedOps.def"
6523     visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(I));
6524     return;
6525 #define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
6526 #include "llvm/IR/VPIntrinsics.def"
6527     visitVectorPredicationIntrinsic(cast<VPIntrinsic>(I));
6528     return;
6529   case Intrinsic::fptrunc_round: {
6530     // Get the last argument, the metadata and convert it to an integer in the
6531     // call
6532     Metadata *MD = cast<MetadataAsValue>(I.getArgOperand(1))->getMetadata();
6533     std::optional<RoundingMode> RoundMode =
6534         convertStrToRoundingMode(cast<MDString>(MD)->getString());
6535 
6536     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6537 
6538     // Propagate fast-math-flags from IR to node(s).
6539     SDNodeFlags Flags;
6540     Flags.copyFMF(*cast<FPMathOperator>(&I));
6541     SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
6542 
6543     SDValue Result;
6544     Result = DAG.getNode(
6545         ISD::FPTRUNC_ROUND, sdl, VT, getValue(I.getArgOperand(0)),
6546         DAG.getTargetConstant((int)*RoundMode, sdl,
6547                               TLI.getPointerTy(DAG.getDataLayout())));
6548     setValue(&I, Result);
6549 
6550     return;
6551   }
6552   case Intrinsic::fmuladd: {
6553     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6554     if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
6555         TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) {
6556       setValue(&I, DAG.getNode(ISD::FMA, sdl,
6557                                getValue(I.getArgOperand(0)).getValueType(),
6558                                getValue(I.getArgOperand(0)),
6559                                getValue(I.getArgOperand(1)),
6560                                getValue(I.getArgOperand(2)), Flags));
6561     } else {
6562       // TODO: Intrinsic calls should have fast-math-flags.
6563       SDValue Mul = DAG.getNode(
6564           ISD::FMUL, sdl, getValue(I.getArgOperand(0)).getValueType(),
6565           getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)), Flags);
6566       SDValue Add = DAG.getNode(ISD::FADD, sdl,
6567                                 getValue(I.getArgOperand(0)).getValueType(),
6568                                 Mul, getValue(I.getArgOperand(2)), Flags);
6569       setValue(&I, Add);
6570     }
6571     return;
6572   }
6573   case Intrinsic::convert_to_fp16:
6574     setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
6575                              DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
6576                                          getValue(I.getArgOperand(0)),
6577                                          DAG.getTargetConstant(0, sdl,
6578                                                                MVT::i32))));
6579     return;
6580   case Intrinsic::convert_from_fp16:
6581     setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
6582                              TLI.getValueType(DAG.getDataLayout(), I.getType()),
6583                              DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
6584                                          getValue(I.getArgOperand(0)))));
6585     return;
6586   case Intrinsic::fptosi_sat: {
6587     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6588     setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT,
6589                              getValue(I.getArgOperand(0)),
6590                              DAG.getValueType(VT.getScalarType())));
6591     return;
6592   }
6593   case Intrinsic::fptoui_sat: {
6594     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6595     setValue(&I, DAG.getNode(ISD::FP_TO_UINT_SAT, sdl, VT,
6596                              getValue(I.getArgOperand(0)),
6597                              DAG.getValueType(VT.getScalarType())));
6598     return;
6599   }
6600   case Intrinsic::set_rounding:
6601     Res = DAG.getNode(ISD::SET_ROUNDING, sdl, MVT::Other,
6602                       {getRoot(), getValue(I.getArgOperand(0))});
6603     setValue(&I, Res);
6604     DAG.setRoot(Res.getValue(0));
6605     return;
6606   case Intrinsic::is_fpclass: {
6607     const DataLayout DLayout = DAG.getDataLayout();
6608     EVT DestVT = TLI.getValueType(DLayout, I.getType());
6609     EVT ArgVT = TLI.getValueType(DLayout, I.getArgOperand(0)->getType());
6610     FPClassTest Test = static_cast<FPClassTest>(
6611         cast<ConstantInt>(I.getArgOperand(1))->getZExtValue());
6612     MachineFunction &MF = DAG.getMachineFunction();
6613     const Function &F = MF.getFunction();
6614     SDValue Op = getValue(I.getArgOperand(0));
6615     SDNodeFlags Flags;
6616     Flags.setNoFPExcept(
6617         !F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP));
6618     // If ISD::IS_FPCLASS should be expanded, do it right now, because the
6619     // expansion can use illegal types. Making expansion early allows
6620     // legalizing these types prior to selection.
6621     if (!TLI.isOperationLegalOrCustom(ISD::IS_FPCLASS, ArgVT)) {
6622       SDValue Result = TLI.expandIS_FPCLASS(DestVT, Op, Test, Flags, sdl, DAG);
6623       setValue(&I, Result);
6624       return;
6625     }
6626 
6627     SDValue Check = DAG.getTargetConstant(Test, sdl, MVT::i32);
6628     SDValue V = DAG.getNode(ISD::IS_FPCLASS, sdl, DestVT, {Op, Check}, Flags);
6629     setValue(&I, V);
6630     return;
6631   }
6632   case Intrinsic::get_fpenv: {
6633     const DataLayout DLayout = DAG.getDataLayout();
6634     EVT EnvVT = TLI.getValueType(DLayout, I.getType());
6635     Align TempAlign = DAG.getEVTAlign(EnvVT);
6636     SDValue Chain = getRoot();
6637     // Use GET_FPENV if it is legal or custom. Otherwise use memory-based node
6638     // and temporary storage in stack.
6639     if (TLI.isOperationLegalOrCustom(ISD::GET_FPENV, EnvVT)) {
6640       Res = DAG.getNode(
6641           ISD::GET_FPENV, sdl,
6642           DAG.getVTList(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6643                         MVT::Other),
6644           Chain);
6645     } else {
6646       SDValue Temp = DAG.CreateStackTemporary(EnvVT, TempAlign.value());
6647       int SPFI = cast<FrameIndexSDNode>(Temp.getNode())->getIndex();
6648       auto MPI =
6649           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
6650       MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
6651           MPI, MachineMemOperand::MOStore, MemoryLocation::UnknownSize,
6652           TempAlign);
6653       Chain = DAG.getGetFPEnv(Chain, sdl, Temp, EnvVT, MMO);
6654       Res = DAG.getLoad(EnvVT, sdl, Chain, Temp, MPI);
6655     }
6656     setValue(&I, Res);
6657     DAG.setRoot(Res.getValue(1));
6658     return;
6659   }
6660   case Intrinsic::set_fpenv: {
6661     const DataLayout DLayout = DAG.getDataLayout();
6662     SDValue Env = getValue(I.getArgOperand(0));
6663     EVT EnvVT = Env.getValueType();
6664     Align TempAlign = DAG.getEVTAlign(EnvVT);
6665     SDValue Chain = getRoot();
6666     // If SET_FPENV is custom or legal, use it. Otherwise use loading
6667     // environment from memory.
6668     if (TLI.isOperationLegalOrCustom(ISD::SET_FPENV, EnvVT)) {
6669       Chain = DAG.getNode(ISD::SET_FPENV, sdl, MVT::Other, Chain, Env);
6670     } else {
6671       // Allocate space in stack, copy environment bits into it and use this
6672       // memory in SET_FPENV_MEM.
6673       SDValue Temp = DAG.CreateStackTemporary(EnvVT, TempAlign.value());
6674       int SPFI = cast<FrameIndexSDNode>(Temp.getNode())->getIndex();
6675       auto MPI =
6676           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
6677       Chain = DAG.getStore(Chain, sdl, Env, Temp, MPI, TempAlign,
6678                            MachineMemOperand::MOStore);
6679       MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
6680           MPI, MachineMemOperand::MOLoad, MemoryLocation::UnknownSize,
6681           TempAlign);
6682       Chain = DAG.getSetFPEnv(Chain, sdl, Temp, EnvVT, MMO);
6683     }
6684     DAG.setRoot(Chain);
6685     return;
6686   }
6687   case Intrinsic::reset_fpenv:
6688     DAG.setRoot(DAG.getNode(ISD::RESET_FPENV, sdl, MVT::Other, getRoot()));
6689     return;
6690   case Intrinsic::get_fpmode:
6691     Res = DAG.getNode(
6692         ISD::GET_FPMODE, sdl,
6693         DAG.getVTList(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6694                       MVT::Other),
6695         DAG.getRoot());
6696     setValue(&I, Res);
6697     DAG.setRoot(Res.getValue(1));
6698     return;
6699   case Intrinsic::set_fpmode:
6700     Res = DAG.getNode(ISD::SET_FPMODE, sdl, MVT::Other, {DAG.getRoot()},
6701                       getValue(I.getArgOperand(0)));
6702     DAG.setRoot(Res);
6703     return;
6704   case Intrinsic::reset_fpmode: {
6705     Res = DAG.getNode(ISD::RESET_FPMODE, sdl, MVT::Other, getRoot());
6706     DAG.setRoot(Res);
6707     return;
6708   }
6709   case Intrinsic::pcmarker: {
6710     SDValue Tmp = getValue(I.getArgOperand(0));
6711     DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
6712     return;
6713   }
6714   case Intrinsic::readcyclecounter: {
6715     SDValue Op = getRoot();
6716     Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
6717                       DAG.getVTList(MVT::i64, MVT::Other), Op);
6718     setValue(&I, Res);
6719     DAG.setRoot(Res.getValue(1));
6720     return;
6721   }
6722   case Intrinsic::bitreverse:
6723     setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
6724                              getValue(I.getArgOperand(0)).getValueType(),
6725                              getValue(I.getArgOperand(0))));
6726     return;
6727   case Intrinsic::bswap:
6728     setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
6729                              getValue(I.getArgOperand(0)).getValueType(),
6730                              getValue(I.getArgOperand(0))));
6731     return;
6732   case Intrinsic::cttz: {
6733     SDValue Arg = getValue(I.getArgOperand(0));
6734     ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
6735     EVT Ty = Arg.getValueType();
6736     setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
6737                              sdl, Ty, Arg));
6738     return;
6739   }
6740   case Intrinsic::ctlz: {
6741     SDValue Arg = getValue(I.getArgOperand(0));
6742     ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
6743     EVT Ty = Arg.getValueType();
6744     setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
6745                              sdl, Ty, Arg));
6746     return;
6747   }
6748   case Intrinsic::ctpop: {
6749     SDValue Arg = getValue(I.getArgOperand(0));
6750     EVT Ty = Arg.getValueType();
6751     setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
6752     return;
6753   }
6754   case Intrinsic::fshl:
6755   case Intrinsic::fshr: {
6756     bool IsFSHL = Intrinsic == Intrinsic::fshl;
6757     SDValue X = getValue(I.getArgOperand(0));
6758     SDValue Y = getValue(I.getArgOperand(1));
6759     SDValue Z = getValue(I.getArgOperand(2));
6760     EVT VT = X.getValueType();
6761 
6762     if (X == Y) {
6763       auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
6764       setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z));
6765     } else {
6766       auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
6767       setValue(&I, DAG.getNode(FunnelOpcode, sdl, VT, X, Y, Z));
6768     }
6769     return;
6770   }
6771   case Intrinsic::sadd_sat: {
6772     SDValue Op1 = getValue(I.getArgOperand(0));
6773     SDValue Op2 = getValue(I.getArgOperand(1));
6774     setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2));
6775     return;
6776   }
6777   case Intrinsic::uadd_sat: {
6778     SDValue Op1 = getValue(I.getArgOperand(0));
6779     SDValue Op2 = getValue(I.getArgOperand(1));
6780     setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2));
6781     return;
6782   }
6783   case Intrinsic::ssub_sat: {
6784     SDValue Op1 = getValue(I.getArgOperand(0));
6785     SDValue Op2 = getValue(I.getArgOperand(1));
6786     setValue(&I, DAG.getNode(ISD::SSUBSAT, sdl, Op1.getValueType(), Op1, Op2));
6787     return;
6788   }
6789   case Intrinsic::usub_sat: {
6790     SDValue Op1 = getValue(I.getArgOperand(0));
6791     SDValue Op2 = getValue(I.getArgOperand(1));
6792     setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2));
6793     return;
6794   }
6795   case Intrinsic::sshl_sat: {
6796     SDValue Op1 = getValue(I.getArgOperand(0));
6797     SDValue Op2 = getValue(I.getArgOperand(1));
6798     setValue(&I, DAG.getNode(ISD::SSHLSAT, sdl, Op1.getValueType(), Op1, Op2));
6799     return;
6800   }
6801   case Intrinsic::ushl_sat: {
6802     SDValue Op1 = getValue(I.getArgOperand(0));
6803     SDValue Op2 = getValue(I.getArgOperand(1));
6804     setValue(&I, DAG.getNode(ISD::USHLSAT, sdl, Op1.getValueType(), Op1, Op2));
6805     return;
6806   }
6807   case Intrinsic::smul_fix:
6808   case Intrinsic::umul_fix:
6809   case Intrinsic::smul_fix_sat:
6810   case Intrinsic::umul_fix_sat: {
6811     SDValue Op1 = getValue(I.getArgOperand(0));
6812     SDValue Op2 = getValue(I.getArgOperand(1));
6813     SDValue Op3 = getValue(I.getArgOperand(2));
6814     setValue(&I, DAG.getNode(FixedPointIntrinsicToOpcode(Intrinsic), sdl,
6815                              Op1.getValueType(), Op1, Op2, Op3));
6816     return;
6817   }
6818   case Intrinsic::sdiv_fix:
6819   case Intrinsic::udiv_fix:
6820   case Intrinsic::sdiv_fix_sat:
6821   case Intrinsic::udiv_fix_sat: {
6822     SDValue Op1 = getValue(I.getArgOperand(0));
6823     SDValue Op2 = getValue(I.getArgOperand(1));
6824     SDValue Op3 = getValue(I.getArgOperand(2));
6825     setValue(&I, expandDivFix(FixedPointIntrinsicToOpcode(Intrinsic), sdl,
6826                               Op1, Op2, Op3, DAG, TLI));
6827     return;
6828   }
6829   case Intrinsic::smax: {
6830     SDValue Op1 = getValue(I.getArgOperand(0));
6831     SDValue Op2 = getValue(I.getArgOperand(1));
6832     setValue(&I, DAG.getNode(ISD::SMAX, sdl, Op1.getValueType(), Op1, Op2));
6833     return;
6834   }
6835   case Intrinsic::smin: {
6836     SDValue Op1 = getValue(I.getArgOperand(0));
6837     SDValue Op2 = getValue(I.getArgOperand(1));
6838     setValue(&I, DAG.getNode(ISD::SMIN, sdl, Op1.getValueType(), Op1, Op2));
6839     return;
6840   }
6841   case Intrinsic::umax: {
6842     SDValue Op1 = getValue(I.getArgOperand(0));
6843     SDValue Op2 = getValue(I.getArgOperand(1));
6844     setValue(&I, DAG.getNode(ISD::UMAX, sdl, Op1.getValueType(), Op1, Op2));
6845     return;
6846   }
6847   case Intrinsic::umin: {
6848     SDValue Op1 = getValue(I.getArgOperand(0));
6849     SDValue Op2 = getValue(I.getArgOperand(1));
6850     setValue(&I, DAG.getNode(ISD::UMIN, sdl, Op1.getValueType(), Op1, Op2));
6851     return;
6852   }
6853   case Intrinsic::abs: {
6854     // TODO: Preserve "int min is poison" arg in SDAG?
6855     SDValue Op1 = getValue(I.getArgOperand(0));
6856     setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1));
6857     return;
6858   }
6859   case Intrinsic::stacksave: {
6860     SDValue Op = getRoot();
6861     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6862     Res = DAG.getNode(ISD::STACKSAVE, sdl, DAG.getVTList(VT, MVT::Other), Op);
6863     setValue(&I, Res);
6864     DAG.setRoot(Res.getValue(1));
6865     return;
6866   }
6867   case Intrinsic::stackrestore:
6868     Res = getValue(I.getArgOperand(0));
6869     DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
6870     return;
6871   case Intrinsic::get_dynamic_area_offset: {
6872     SDValue Op = getRoot();
6873     EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout());
6874     EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
6875     // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
6876     // target.
6877     if (PtrTy.getFixedSizeInBits() < ResTy.getFixedSizeInBits())
6878       report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
6879                          " intrinsic!");
6880     Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
6881                       Op);
6882     DAG.setRoot(Op);
6883     setValue(&I, Res);
6884     return;
6885   }
6886   case Intrinsic::stackguard: {
6887     MachineFunction &MF = DAG.getMachineFunction();
6888     const Module &M = *MF.getFunction().getParent();
6889     SDValue Chain = getRoot();
6890     if (TLI.useLoadStackGuardNode()) {
6891       Res = getLoadStackGuard(DAG, sdl, Chain);
6892     } else {
6893       EVT PtrTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
6894       const Value *Global = TLI.getSDagStackGuard(M);
6895       Align Align = DAG.getDataLayout().getPrefTypeAlign(Global->getType());
6896       Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global),
6897                         MachinePointerInfo(Global, 0), Align,
6898                         MachineMemOperand::MOVolatile);
6899     }
6900     if (TLI.useStackGuardXorFP())
6901       Res = TLI.emitStackGuardXorFP(DAG, Res, sdl);
6902     DAG.setRoot(Chain);
6903     setValue(&I, Res);
6904     return;
6905   }
6906   case Intrinsic::stackprotector: {
6907     // Emit code into the DAG to store the stack guard onto the stack.
6908     MachineFunction &MF = DAG.getMachineFunction();
6909     MachineFrameInfo &MFI = MF.getFrameInfo();
6910     SDValue Src, Chain = getRoot();
6911 
6912     if (TLI.useLoadStackGuardNode())
6913       Src = getLoadStackGuard(DAG, sdl, Chain);
6914     else
6915       Src = getValue(I.getArgOperand(0));   // The guard's value.
6916 
6917     AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
6918 
6919     int FI = FuncInfo.StaticAllocaMap[Slot];
6920     MFI.setStackProtectorIndex(FI);
6921     EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout());
6922 
6923     SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
6924 
6925     // Store the stack protector onto the stack.
6926     Res = DAG.getStore(
6927         Chain, sdl, Src, FIN,
6928         MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
6929         MaybeAlign(), MachineMemOperand::MOVolatile);
6930     setValue(&I, Res);
6931     DAG.setRoot(Res);
6932     return;
6933   }
6934   case Intrinsic::objectsize:
6935     llvm_unreachable("llvm.objectsize.* should have been lowered already");
6936 
6937   case Intrinsic::is_constant:
6938     llvm_unreachable("llvm.is.constant.* should have been lowered already");
6939 
6940   case Intrinsic::annotation:
6941   case Intrinsic::ptr_annotation:
6942   case Intrinsic::launder_invariant_group:
6943   case Intrinsic::strip_invariant_group:
6944     // Drop the intrinsic, but forward the value
6945     setValue(&I, getValue(I.getOperand(0)));
6946     return;
6947 
6948   case Intrinsic::assume:
6949   case Intrinsic::experimental_noalias_scope_decl:
6950   case Intrinsic::var_annotation:
6951   case Intrinsic::sideeffect:
6952     // Discard annotate attributes, noalias scope declarations, assumptions, and
6953     // artificial side-effects.
6954     return;
6955 
6956   case Intrinsic::codeview_annotation: {
6957     // Emit a label associated with this metadata.
6958     MachineFunction &MF = DAG.getMachineFunction();
6959     MCSymbol *Label =
6960         MF.getMMI().getContext().createTempSymbol("annotation", true);
6961     Metadata *MD = cast<MetadataAsValue>(I.getArgOperand(0))->getMetadata();
6962     MF.addCodeViewAnnotation(Label, cast<MDNode>(MD));
6963     Res = DAG.getLabelNode(ISD::ANNOTATION_LABEL, sdl, getRoot(), Label);
6964     DAG.setRoot(Res);
6965     return;
6966   }
6967 
6968   case Intrinsic::init_trampoline: {
6969     const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
6970 
6971     SDValue Ops[6];
6972     Ops[0] = getRoot();
6973     Ops[1] = getValue(I.getArgOperand(0));
6974     Ops[2] = getValue(I.getArgOperand(1));
6975     Ops[3] = getValue(I.getArgOperand(2));
6976     Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
6977     Ops[5] = DAG.getSrcValue(F);
6978 
6979     Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
6980 
6981     DAG.setRoot(Res);
6982     return;
6983   }
6984   case Intrinsic::adjust_trampoline:
6985     setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
6986                              TLI.getPointerTy(DAG.getDataLayout()),
6987                              getValue(I.getArgOperand(0))));
6988     return;
6989   case Intrinsic::gcroot: {
6990     assert(DAG.getMachineFunction().getFunction().hasGC() &&
6991            "only valid in functions with gc specified, enforced by Verifier");
6992     assert(GFI && "implied by previous");
6993     const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
6994     const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
6995 
6996     FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
6997     GFI->addStackRoot(FI->getIndex(), TypeMap);
6998     return;
6999   }
7000   case Intrinsic::gcread:
7001   case Intrinsic::gcwrite:
7002     llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
7003   case Intrinsic::get_rounding:
7004     Res = DAG.getNode(ISD::GET_ROUNDING, sdl, {MVT::i32, MVT::Other}, getRoot());
7005     setValue(&I, Res);
7006     DAG.setRoot(Res.getValue(1));
7007     return;
7008 
7009   case Intrinsic::expect:
7010     // Just replace __builtin_expect(exp, c) with EXP.
7011     setValue(&I, getValue(I.getArgOperand(0)));
7012     return;
7013 
7014   case Intrinsic::ubsantrap:
7015   case Intrinsic::debugtrap:
7016   case Intrinsic::trap: {
7017     StringRef TrapFuncName =
7018         I.getAttributes().getFnAttr("trap-func-name").getValueAsString();
7019     if (TrapFuncName.empty()) {
7020       switch (Intrinsic) {
7021       case Intrinsic::trap:
7022         DAG.setRoot(DAG.getNode(ISD::TRAP, sdl, MVT::Other, getRoot()));
7023         break;
7024       case Intrinsic::debugtrap:
7025         DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, sdl, MVT::Other, getRoot()));
7026         break;
7027       case Intrinsic::ubsantrap:
7028         DAG.setRoot(DAG.getNode(
7029             ISD::UBSANTRAP, sdl, MVT::Other, getRoot(),
7030             DAG.getTargetConstant(
7031                 cast<ConstantInt>(I.getArgOperand(0))->getZExtValue(), sdl,
7032                 MVT::i32)));
7033         break;
7034       default: llvm_unreachable("unknown trap intrinsic");
7035       }
7036       return;
7037     }
7038     TargetLowering::ArgListTy Args;
7039     if (Intrinsic == Intrinsic::ubsantrap) {
7040       Args.push_back(TargetLoweringBase::ArgListEntry());
7041       Args[0].Val = I.getArgOperand(0);
7042       Args[0].Node = getValue(Args[0].Val);
7043       Args[0].Ty = Args[0].Val->getType();
7044     }
7045 
7046     TargetLowering::CallLoweringInfo CLI(DAG);
7047     CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee(
7048         CallingConv::C, I.getType(),
7049         DAG.getExternalSymbol(TrapFuncName.data(),
7050                               TLI.getPointerTy(DAG.getDataLayout())),
7051         std::move(Args));
7052 
7053     std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
7054     DAG.setRoot(Result.second);
7055     return;
7056   }
7057 
7058   case Intrinsic::uadd_with_overflow:
7059   case Intrinsic::sadd_with_overflow:
7060   case Intrinsic::usub_with_overflow:
7061   case Intrinsic::ssub_with_overflow:
7062   case Intrinsic::umul_with_overflow:
7063   case Intrinsic::smul_with_overflow: {
7064     ISD::NodeType Op;
7065     switch (Intrinsic) {
7066     default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
7067     case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
7068     case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
7069     case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
7070     case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
7071     case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
7072     case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
7073     }
7074     SDValue Op1 = getValue(I.getArgOperand(0));
7075     SDValue Op2 = getValue(I.getArgOperand(1));
7076 
7077     EVT ResultVT = Op1.getValueType();
7078     EVT OverflowVT = MVT::i1;
7079     if (ResultVT.isVector())
7080       OverflowVT = EVT::getVectorVT(
7081           *Context, OverflowVT, ResultVT.getVectorElementCount());
7082 
7083     SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT);
7084     setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
7085     return;
7086   }
7087   case Intrinsic::prefetch: {
7088     SDValue Ops[5];
7089     unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
7090     auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore;
7091     Ops[0] = DAG.getRoot();
7092     Ops[1] = getValue(I.getArgOperand(0));
7093     Ops[2] = DAG.getTargetConstant(*cast<ConstantInt>(I.getArgOperand(1)), sdl,
7094                                    MVT::i32);
7095     Ops[3] = DAG.getTargetConstant(*cast<ConstantInt>(I.getArgOperand(2)), sdl,
7096                                    MVT::i32);
7097     Ops[4] = DAG.getTargetConstant(*cast<ConstantInt>(I.getArgOperand(3)), sdl,
7098                                    MVT::i32);
7099     SDValue Result = DAG.getMemIntrinsicNode(
7100         ISD::PREFETCH, sdl, DAG.getVTList(MVT::Other), Ops,
7101         EVT::getIntegerVT(*Context, 8), MachinePointerInfo(I.getArgOperand(0)),
7102         /* align */ std::nullopt, Flags);
7103 
7104     // Chain the prefetch in parallell with any pending loads, to stay out of
7105     // the way of later optimizations.
7106     PendingLoads.push_back(Result);
7107     Result = getRoot();
7108     DAG.setRoot(Result);
7109     return;
7110   }
7111   case Intrinsic::lifetime_start:
7112   case Intrinsic::lifetime_end: {
7113     bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
7114     // Stack coloring is not enabled in O0, discard region information.
7115     if (TM.getOptLevel() == CodeGenOptLevel::None)
7116       return;
7117 
7118     const int64_t ObjectSize =
7119         cast<ConstantInt>(I.getArgOperand(0))->getSExtValue();
7120     Value *const ObjectPtr = I.getArgOperand(1);
7121     SmallVector<const Value *, 4> Allocas;
7122     getUnderlyingObjects(ObjectPtr, Allocas);
7123 
7124     for (const Value *Alloca : Allocas) {
7125       const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(Alloca);
7126 
7127       // Could not find an Alloca.
7128       if (!LifetimeObject)
7129         continue;
7130 
7131       // First check that the Alloca is static, otherwise it won't have a
7132       // valid frame index.
7133       auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
7134       if (SI == FuncInfo.StaticAllocaMap.end())
7135         return;
7136 
7137       const int FrameIndex = SI->second;
7138       int64_t Offset;
7139       if (GetPointerBaseWithConstantOffset(
7140               ObjectPtr, Offset, DAG.getDataLayout()) != LifetimeObject)
7141         Offset = -1; // Cannot determine offset from alloca to lifetime object.
7142       Res = DAG.getLifetimeNode(IsStart, sdl, getRoot(), FrameIndex, ObjectSize,
7143                                 Offset);
7144       DAG.setRoot(Res);
7145     }
7146     return;
7147   }
7148   case Intrinsic::pseudoprobe: {
7149     auto Guid = cast<ConstantInt>(I.getArgOperand(0))->getZExtValue();
7150     auto Index = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
7151     auto Attr = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
7152     Res = DAG.getPseudoProbeNode(sdl, getRoot(), Guid, Index, Attr);
7153     DAG.setRoot(Res);
7154     return;
7155   }
7156   case Intrinsic::invariant_start:
7157     // Discard region information.
7158     setValue(&I,
7159              DAG.getUNDEF(TLI.getValueType(DAG.getDataLayout(), I.getType())));
7160     return;
7161   case Intrinsic::invariant_end:
7162     // Discard region information.
7163     return;
7164   case Intrinsic::clear_cache:
7165     /// FunctionName may be null.
7166     if (const char *FunctionName = TLI.getClearCacheBuiltinName())
7167       lowerCallToExternalSymbol(I, FunctionName);
7168     return;
7169   case Intrinsic::donothing:
7170   case Intrinsic::seh_try_begin:
7171   case Intrinsic::seh_scope_begin:
7172   case Intrinsic::seh_try_end:
7173   case Intrinsic::seh_scope_end:
7174     // ignore
7175     return;
7176   case Intrinsic::experimental_stackmap:
7177     visitStackmap(I);
7178     return;
7179   case Intrinsic::experimental_patchpoint_void:
7180   case Intrinsic::experimental_patchpoint_i64:
7181     visitPatchpoint(I);
7182     return;
7183   case Intrinsic::experimental_gc_statepoint:
7184     LowerStatepoint(cast<GCStatepointInst>(I));
7185     return;
7186   case Intrinsic::experimental_gc_result:
7187     visitGCResult(cast<GCResultInst>(I));
7188     return;
7189   case Intrinsic::experimental_gc_relocate:
7190     visitGCRelocate(cast<GCRelocateInst>(I));
7191     return;
7192   case Intrinsic::instrprof_cover:
7193     llvm_unreachable("instrprof failed to lower a cover");
7194   case Intrinsic::instrprof_increment:
7195     llvm_unreachable("instrprof failed to lower an increment");
7196   case Intrinsic::instrprof_timestamp:
7197     llvm_unreachable("instrprof failed to lower a timestamp");
7198   case Intrinsic::instrprof_value_profile:
7199     llvm_unreachable("instrprof failed to lower a value profiling call");
7200   case Intrinsic::localescape: {
7201     MachineFunction &MF = DAG.getMachineFunction();
7202     const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
7203 
7204     // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
7205     // is the same on all targets.
7206     for (unsigned Idx = 0, E = I.arg_size(); Idx < E; ++Idx) {
7207       Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
7208       if (isa<ConstantPointerNull>(Arg))
7209         continue; // Skip null pointers. They represent a hole in index space.
7210       AllocaInst *Slot = cast<AllocaInst>(Arg);
7211       assert(FuncInfo.StaticAllocaMap.count(Slot) &&
7212              "can only escape static allocas");
7213       int FI = FuncInfo.StaticAllocaMap[Slot];
7214       MCSymbol *FrameAllocSym =
7215           MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
7216               GlobalValue::dropLLVMManglingEscape(MF.getName()), Idx);
7217       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
7218               TII->get(TargetOpcode::LOCAL_ESCAPE))
7219           .addSym(FrameAllocSym)
7220           .addFrameIndex(FI);
7221     }
7222 
7223     return;
7224   }
7225 
7226   case Intrinsic::localrecover: {
7227     // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
7228     MachineFunction &MF = DAG.getMachineFunction();
7229 
7230     // Get the symbol that defines the frame offset.
7231     auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
7232     auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
7233     unsigned IdxVal =
7234         unsigned(Idx->getLimitedValue(std::numeric_limits<int>::max()));
7235     MCSymbol *FrameAllocSym =
7236         MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
7237             GlobalValue::dropLLVMManglingEscape(Fn->getName()), IdxVal);
7238 
7239     Value *FP = I.getArgOperand(1);
7240     SDValue FPVal = getValue(FP);
7241     EVT PtrVT = FPVal.getValueType();
7242 
7243     // Create a MCSymbol for the label to avoid any target lowering
7244     // that would make this PC relative.
7245     SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
7246     SDValue OffsetVal =
7247         DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
7248 
7249     // Add the offset to the FP.
7250     SDValue Add = DAG.getMemBasePlusOffset(FPVal, OffsetVal, sdl);
7251     setValue(&I, Add);
7252 
7253     return;
7254   }
7255 
7256   case Intrinsic::eh_exceptionpointer:
7257   case Intrinsic::eh_exceptioncode: {
7258     // Get the exception pointer vreg, copy from it, and resize it to fit.
7259     const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
7260     MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
7261     const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
7262     unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
7263     SDValue N = DAG.getCopyFromReg(DAG.getEntryNode(), sdl, VReg, PtrVT);
7264     if (Intrinsic == Intrinsic::eh_exceptioncode)
7265       N = DAG.getZExtOrTrunc(N, sdl, MVT::i32);
7266     setValue(&I, N);
7267     return;
7268   }
7269   case Intrinsic::xray_customevent: {
7270     // Here we want to make sure that the intrinsic behaves as if it has a
7271     // specific calling convention.
7272     const auto &Triple = DAG.getTarget().getTargetTriple();
7273     if (!Triple.isAArch64(64) && Triple.getArch() != Triple::x86_64)
7274       return;
7275 
7276     SmallVector<SDValue, 8> Ops;
7277 
7278     // We want to say that we always want the arguments in registers.
7279     SDValue LogEntryVal = getValue(I.getArgOperand(0));
7280     SDValue StrSizeVal = getValue(I.getArgOperand(1));
7281     SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7282     SDValue Chain = getRoot();
7283     Ops.push_back(LogEntryVal);
7284     Ops.push_back(StrSizeVal);
7285     Ops.push_back(Chain);
7286 
7287     // We need to enforce the calling convention for the callsite, so that
7288     // argument ordering is enforced correctly, and that register allocation can
7289     // see that some registers may be assumed clobbered and have to preserve
7290     // them across calls to the intrinsic.
7291     MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHABLE_EVENT_CALL,
7292                                            sdl, NodeTys, Ops);
7293     SDValue patchableNode = SDValue(MN, 0);
7294     DAG.setRoot(patchableNode);
7295     setValue(&I, patchableNode);
7296     return;
7297   }
7298   case Intrinsic::xray_typedevent: {
7299     // Here we want to make sure that the intrinsic behaves as if it has a
7300     // specific calling convention.
7301     const auto &Triple = DAG.getTarget().getTargetTriple();
7302     if (!Triple.isAArch64(64) && Triple.getArch() != Triple::x86_64)
7303       return;
7304 
7305     SmallVector<SDValue, 8> Ops;
7306 
7307     // We want to say that we always want the arguments in registers.
7308     // It's unclear to me how manipulating the selection DAG here forces callers
7309     // to provide arguments in registers instead of on the stack.
7310     SDValue LogTypeId = getValue(I.getArgOperand(0));
7311     SDValue LogEntryVal = getValue(I.getArgOperand(1));
7312     SDValue StrSizeVal = getValue(I.getArgOperand(2));
7313     SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7314     SDValue Chain = getRoot();
7315     Ops.push_back(LogTypeId);
7316     Ops.push_back(LogEntryVal);
7317     Ops.push_back(StrSizeVal);
7318     Ops.push_back(Chain);
7319 
7320     // We need to enforce the calling convention for the callsite, so that
7321     // argument ordering is enforced correctly, and that register allocation can
7322     // see that some registers may be assumed clobbered and have to preserve
7323     // them across calls to the intrinsic.
7324     MachineSDNode *MN = DAG.getMachineNode(
7325         TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, sdl, NodeTys, Ops);
7326     SDValue patchableNode = SDValue(MN, 0);
7327     DAG.setRoot(patchableNode);
7328     setValue(&I, patchableNode);
7329     return;
7330   }
7331   case Intrinsic::experimental_deoptimize:
7332     LowerDeoptimizeCall(&I);
7333     return;
7334   case Intrinsic::experimental_stepvector:
7335     visitStepVector(I);
7336     return;
7337   case Intrinsic::vector_reduce_fadd:
7338   case Intrinsic::vector_reduce_fmul:
7339   case Intrinsic::vector_reduce_add:
7340   case Intrinsic::vector_reduce_mul:
7341   case Intrinsic::vector_reduce_and:
7342   case Intrinsic::vector_reduce_or:
7343   case Intrinsic::vector_reduce_xor:
7344   case Intrinsic::vector_reduce_smax:
7345   case Intrinsic::vector_reduce_smin:
7346   case Intrinsic::vector_reduce_umax:
7347   case Intrinsic::vector_reduce_umin:
7348   case Intrinsic::vector_reduce_fmax:
7349   case Intrinsic::vector_reduce_fmin:
7350   case Intrinsic::vector_reduce_fmaximum:
7351   case Intrinsic::vector_reduce_fminimum:
7352     visitVectorReduce(I, Intrinsic);
7353     return;
7354 
7355   case Intrinsic::icall_branch_funnel: {
7356     SmallVector<SDValue, 16> Ops;
7357     Ops.push_back(getValue(I.getArgOperand(0)));
7358 
7359     int64_t Offset;
7360     auto *Base = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset(
7361         I.getArgOperand(1), Offset, DAG.getDataLayout()));
7362     if (!Base)
7363       report_fatal_error(
7364           "llvm.icall.branch.funnel operand must be a GlobalValue");
7365     Ops.push_back(DAG.getTargetGlobalAddress(Base, sdl, MVT::i64, 0));
7366 
7367     struct BranchFunnelTarget {
7368       int64_t Offset;
7369       SDValue Target;
7370     };
7371     SmallVector<BranchFunnelTarget, 8> Targets;
7372 
7373     for (unsigned Op = 1, N = I.arg_size(); Op != N; Op += 2) {
7374       auto *ElemBase = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset(
7375           I.getArgOperand(Op), Offset, DAG.getDataLayout()));
7376       if (ElemBase != Base)
7377         report_fatal_error("all llvm.icall.branch.funnel operands must refer "
7378                            "to the same GlobalValue");
7379 
7380       SDValue Val = getValue(I.getArgOperand(Op + 1));
7381       auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
7382       if (!GA)
7383         report_fatal_error(
7384             "llvm.icall.branch.funnel operand must be a GlobalValue");
7385       Targets.push_back({Offset, DAG.getTargetGlobalAddress(
7386                                      GA->getGlobal(), sdl, Val.getValueType(),
7387                                      GA->getOffset())});
7388     }
7389     llvm::sort(Targets,
7390                [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) {
7391                  return T1.Offset < T2.Offset;
7392                });
7393 
7394     for (auto &T : Targets) {
7395       Ops.push_back(DAG.getTargetConstant(T.Offset, sdl, MVT::i32));
7396       Ops.push_back(T.Target);
7397     }
7398 
7399     Ops.push_back(DAG.getRoot()); // Chain
7400     SDValue N(DAG.getMachineNode(TargetOpcode::ICALL_BRANCH_FUNNEL, sdl,
7401                                  MVT::Other, Ops),
7402               0);
7403     DAG.setRoot(N);
7404     setValue(&I, N);
7405     HasTailCall = true;
7406     return;
7407   }
7408 
7409   case Intrinsic::wasm_landingpad_index:
7410     // Information this intrinsic contained has been transferred to
7411     // MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely
7412     // delete it now.
7413     return;
7414 
7415   case Intrinsic::aarch64_settag:
7416   case Intrinsic::aarch64_settag_zero: {
7417     const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
7418     bool ZeroMemory = Intrinsic == Intrinsic::aarch64_settag_zero;
7419     SDValue Val = TSI.EmitTargetCodeForSetTag(
7420         DAG, sdl, getRoot(), getValue(I.getArgOperand(0)),
7421         getValue(I.getArgOperand(1)), MachinePointerInfo(I.getArgOperand(0)),
7422         ZeroMemory);
7423     DAG.setRoot(Val);
7424     setValue(&I, Val);
7425     return;
7426   }
7427   case Intrinsic::ptrmask: {
7428     SDValue Ptr = getValue(I.getOperand(0));
7429     SDValue Const = getValue(I.getOperand(1));
7430 
7431     EVT PtrVT = Ptr.getValueType();
7432     setValue(&I, DAG.getNode(ISD::AND, sdl, PtrVT, Ptr,
7433                              DAG.getZExtOrTrunc(Const, sdl, PtrVT)));
7434     return;
7435   }
7436   case Intrinsic::threadlocal_address: {
7437     setValue(&I, getValue(I.getOperand(0)));
7438     return;
7439   }
7440   case Intrinsic::get_active_lane_mask: {
7441     EVT CCVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
7442     SDValue Index = getValue(I.getOperand(0));
7443     EVT ElementVT = Index.getValueType();
7444 
7445     if (!TLI.shouldExpandGetActiveLaneMask(CCVT, ElementVT)) {
7446       visitTargetIntrinsic(I, Intrinsic);
7447       return;
7448     }
7449 
7450     SDValue TripCount = getValue(I.getOperand(1));
7451     EVT VecTy = EVT::getVectorVT(*DAG.getContext(), ElementVT,
7452                                  CCVT.getVectorElementCount());
7453 
7454     SDValue VectorIndex = DAG.getSplat(VecTy, sdl, Index);
7455     SDValue VectorTripCount = DAG.getSplat(VecTy, sdl, TripCount);
7456     SDValue VectorStep = DAG.getStepVector(sdl, VecTy);
7457     SDValue VectorInduction = DAG.getNode(
7458         ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep);
7459     SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction,
7460                                  VectorTripCount, ISD::CondCode::SETULT);
7461     setValue(&I, SetCC);
7462     return;
7463   }
7464   case Intrinsic::experimental_get_vector_length: {
7465     assert(cast<ConstantInt>(I.getOperand(1))->getSExtValue() > 0 &&
7466            "Expected positive VF");
7467     unsigned VF = cast<ConstantInt>(I.getOperand(1))->getZExtValue();
7468     bool IsScalable = cast<ConstantInt>(I.getOperand(2))->isOne();
7469 
7470     SDValue Count = getValue(I.getOperand(0));
7471     EVT CountVT = Count.getValueType();
7472 
7473     if (!TLI.shouldExpandGetVectorLength(CountVT, VF, IsScalable)) {
7474       visitTargetIntrinsic(I, Intrinsic);
7475       return;
7476     }
7477 
7478     // Expand to a umin between the trip count and the maximum elements the type
7479     // can hold.
7480     EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
7481 
7482     // Extend the trip count to at least the result VT.
7483     if (CountVT.bitsLT(VT)) {
7484       Count = DAG.getNode(ISD::ZERO_EXTEND, sdl, VT, Count);
7485       CountVT = VT;
7486     }
7487 
7488     SDValue MaxEVL = DAG.getElementCount(sdl, CountVT,
7489                                          ElementCount::get(VF, IsScalable));
7490 
7491     SDValue UMin = DAG.getNode(ISD::UMIN, sdl, CountVT, Count, MaxEVL);
7492     // Clip to the result type if needed.
7493     SDValue Trunc = DAG.getNode(ISD::TRUNCATE, sdl, VT, UMin);
7494 
7495     setValue(&I, Trunc);
7496     return;
7497   }
7498   case Intrinsic::vector_insert: {
7499     SDValue Vec = getValue(I.getOperand(0));
7500     SDValue SubVec = getValue(I.getOperand(1));
7501     SDValue Index = getValue(I.getOperand(2));
7502 
7503     // The intrinsic's index type is i64, but the SDNode requires an index type
7504     // suitable for the target. Convert the index as required.
7505     MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
7506     if (Index.getValueType() != VectorIdxTy)
7507       Index = DAG.getVectorIdxConstant(
7508           cast<ConstantSDNode>(Index)->getZExtValue(), sdl);
7509 
7510     EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
7511     setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec,
7512                              Index));
7513     return;
7514   }
7515   case Intrinsic::vector_extract: {
7516     SDValue Vec = getValue(I.getOperand(0));
7517     SDValue Index = getValue(I.getOperand(1));
7518     EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
7519 
7520     // The intrinsic's index type is i64, but the SDNode requires an index type
7521     // suitable for the target. Convert the index as required.
7522     MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
7523     if (Index.getValueType() != VectorIdxTy)
7524       Index = DAG.getVectorIdxConstant(
7525           cast<ConstantSDNode>(Index)->getZExtValue(), sdl);
7526 
7527     setValue(&I,
7528              DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index));
7529     return;
7530   }
7531   case Intrinsic::experimental_vector_reverse:
7532     visitVectorReverse(I);
7533     return;
7534   case Intrinsic::experimental_vector_splice:
7535     visitVectorSplice(I);
7536     return;
7537   case Intrinsic::callbr_landingpad:
7538     visitCallBrLandingPad(I);
7539     return;
7540   case Intrinsic::experimental_vector_interleave2:
7541     visitVectorInterleave(I);
7542     return;
7543   case Intrinsic::experimental_vector_deinterleave2:
7544     visitVectorDeinterleave(I);
7545     return;
7546   }
7547 }
7548 
7549 void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
7550     const ConstrainedFPIntrinsic &FPI) {
7551   SDLoc sdl = getCurSDLoc();
7552 
7553   // We do not need to serialize constrained FP intrinsics against
7554   // each other or against (nonvolatile) loads, so they can be
7555   // chained like loads.
7556   SDValue Chain = DAG.getRoot();
7557   SmallVector<SDValue, 4> Opers;
7558   Opers.push_back(Chain);
7559   if (FPI.isUnaryOp()) {
7560     Opers.push_back(getValue(FPI.getArgOperand(0)));
7561   } else if (FPI.isTernaryOp()) {
7562     Opers.push_back(getValue(FPI.getArgOperand(0)));
7563     Opers.push_back(getValue(FPI.getArgOperand(1)));
7564     Opers.push_back(getValue(FPI.getArgOperand(2)));
7565   } else {
7566     Opers.push_back(getValue(FPI.getArgOperand(0)));
7567     Opers.push_back(getValue(FPI.getArgOperand(1)));
7568   }
7569 
7570   auto pushOutChain = [this](SDValue Result, fp::ExceptionBehavior EB) {
7571     assert(Result.getNode()->getNumValues() == 2);
7572 
7573     // Push node to the appropriate list so that future instructions can be
7574     // chained up correctly.
7575     SDValue OutChain = Result.getValue(1);
7576     switch (EB) {
7577     case fp::ExceptionBehavior::ebIgnore:
7578       // The only reason why ebIgnore nodes still need to be chained is that
7579       // they might depend on the current rounding mode, and therefore must
7580       // not be moved across instruction that may change that mode.
7581       [[fallthrough]];
7582     case fp::ExceptionBehavior::ebMayTrap:
7583       // These must not be moved across calls or instructions that may change
7584       // floating-point exception masks.
7585       PendingConstrainedFP.push_back(OutChain);
7586       break;
7587     case fp::ExceptionBehavior::ebStrict:
7588       // These must not be moved across calls or instructions that may change
7589       // floating-point exception masks or read floating-point exception flags.
7590       // In addition, they cannot be optimized out even if unused.
7591       PendingConstrainedFPStrict.push_back(OutChain);
7592       break;
7593     }
7594   };
7595 
7596   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7597   EVT VT = TLI.getValueType(DAG.getDataLayout(), FPI.getType());
7598   SDVTList VTs = DAG.getVTList(VT, MVT::Other);
7599   fp::ExceptionBehavior EB = *FPI.getExceptionBehavior();
7600 
7601   SDNodeFlags Flags;
7602   if (EB == fp::ExceptionBehavior::ebIgnore)
7603     Flags.setNoFPExcept(true);
7604 
7605   if (auto *FPOp = dyn_cast<FPMathOperator>(&FPI))
7606     Flags.copyFMF(*FPOp);
7607 
7608   unsigned Opcode;
7609   switch (FPI.getIntrinsicID()) {
7610   default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
7611 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \
7612   case Intrinsic::INTRINSIC:                                                   \
7613     Opcode = ISD::STRICT_##DAGN;                                               \
7614     break;
7615 #include "llvm/IR/ConstrainedOps.def"
7616   case Intrinsic::experimental_constrained_fmuladd: {
7617     Opcode = ISD::STRICT_FMA;
7618     // Break fmuladd into fmul and fadd.
7619     if (TM.Options.AllowFPOpFusion == FPOpFusion::Strict ||
7620         !TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) {
7621       Opers.pop_back();
7622       SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, sdl, VTs, Opers, Flags);
7623       pushOutChain(Mul, EB);
7624       Opcode = ISD::STRICT_FADD;
7625       Opers.clear();
7626       Opers.push_back(Mul.getValue(1));
7627       Opers.push_back(Mul.getValue(0));
7628       Opers.push_back(getValue(FPI.getArgOperand(2)));
7629     }
7630     break;
7631   }
7632   }
7633 
7634   // A few strict DAG nodes carry additional operands that are not
7635   // set up by the default code above.
7636   switch (Opcode) {
7637   default: break;
7638   case ISD::STRICT_FP_ROUND:
7639     Opers.push_back(
7640         DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
7641     break;
7642   case ISD::STRICT_FSETCC:
7643   case ISD::STRICT_FSETCCS: {
7644     auto *FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(&FPI);
7645     ISD::CondCode Condition = getFCmpCondCode(FPCmp->getPredicate());
7646     if (TM.Options.NoNaNsFPMath)
7647       Condition = getFCmpCodeWithoutNaN(Condition);
7648     Opers.push_back(DAG.getCondCode(Condition));
7649     break;
7650   }
7651   }
7652 
7653   SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers, Flags);
7654   pushOutChain(Result, EB);
7655 
7656   SDValue FPResult = Result.getValue(0);
7657   setValue(&FPI, FPResult);
7658 }
7659 
7660 static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) {
7661   std::optional<unsigned> ResOPC;
7662   switch (VPIntrin.getIntrinsicID()) {
7663   case Intrinsic::vp_ctlz: {
7664     bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
7665     ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ;
7666     break;
7667   }
7668   case Intrinsic::vp_cttz: {
7669     bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
7670     ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ;
7671     break;
7672   }
7673 #define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD)                                    \
7674   case Intrinsic::VPID:                                                        \
7675     ResOPC = ISD::VPSD;                                                        \
7676     break;
7677 #include "llvm/IR/VPIntrinsics.def"
7678   }
7679 
7680   if (!ResOPC)
7681     llvm_unreachable(
7682         "Inconsistency: no SDNode available for this VPIntrinsic!");
7683 
7684   if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD ||
7685       *ResOPC == ISD::VP_REDUCE_SEQ_FMUL) {
7686     if (VPIntrin.getFastMathFlags().allowReassoc())
7687       return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD
7688                                                 : ISD::VP_REDUCE_FMUL;
7689   }
7690 
7691   return *ResOPC;
7692 }
7693 
7694 void SelectionDAGBuilder::visitVPLoad(
7695     const VPIntrinsic &VPIntrin, EVT VT,
7696     const SmallVectorImpl<SDValue> &OpValues) {
7697   SDLoc DL = getCurSDLoc();
7698   Value *PtrOperand = VPIntrin.getArgOperand(0);
7699   MaybeAlign Alignment = VPIntrin.getPointerAlignment();
7700   AAMDNodes AAInfo = VPIntrin.getAAMetadata();
7701   const MDNode *Ranges = getRangeMetadata(VPIntrin);
7702   SDValue LD;
7703   // Do not serialize variable-length loads of constant memory with
7704   // anything.
7705   if (!Alignment)
7706     Alignment = DAG.getEVTAlign(VT);
7707   MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo);
7708   bool AddToChain = !AA || !AA->pointsToConstantMemory(ML);
7709   SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
7710   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7711       MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad,
7712       MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges);
7713   LD = DAG.getLoadVP(VT, DL, InChain, OpValues[0], OpValues[1], OpValues[2],
7714                      MMO, false /*IsExpanding */);
7715   if (AddToChain)
7716     PendingLoads.push_back(LD.getValue(1));
7717   setValue(&VPIntrin, LD);
7718 }
7719 
7720 void SelectionDAGBuilder::visitVPGather(
7721     const VPIntrinsic &VPIntrin, EVT VT,
7722     const SmallVectorImpl<SDValue> &OpValues) {
7723   SDLoc DL = getCurSDLoc();
7724   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7725   Value *PtrOperand = VPIntrin.getArgOperand(0);
7726   MaybeAlign Alignment = VPIntrin.getPointerAlignment();
7727   AAMDNodes AAInfo = VPIntrin.getAAMetadata();
7728   const MDNode *Ranges = getRangeMetadata(VPIntrin);
7729   SDValue LD;
7730   if (!Alignment)
7731     Alignment = DAG.getEVTAlign(VT.getScalarType());
7732   unsigned AS =
7733     PtrOperand->getType()->getScalarType()->getPointerAddressSpace();
7734   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7735      MachinePointerInfo(AS), MachineMemOperand::MOLoad,
7736      MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges);
7737   SDValue Base, Index, Scale;
7738   ISD::MemIndexType IndexType;
7739   bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale,
7740                                     this, VPIntrin.getParent(),
7741                                     VT.getScalarStoreSize());
7742   if (!UniformBase) {
7743     Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout()));
7744     Index = getValue(PtrOperand);
7745     IndexType = ISD::SIGNED_SCALED;
7746     Scale = DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout()));
7747   }
7748   EVT IdxVT = Index.getValueType();
7749   EVT EltTy = IdxVT.getVectorElementType();
7750   if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) {
7751     EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy);
7752     Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index);
7753   }
7754   LD = DAG.getGatherVP(
7755       DAG.getVTList(VT, MVT::Other), VT, DL,
7756       {DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO,
7757       IndexType);
7758   PendingLoads.push_back(LD.getValue(1));
7759   setValue(&VPIntrin, LD);
7760 }
7761 
7762 void SelectionDAGBuilder::visitVPStore(
7763     const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
7764   SDLoc DL = getCurSDLoc();
7765   Value *PtrOperand = VPIntrin.getArgOperand(1);
7766   EVT VT = OpValues[0].getValueType();
7767   MaybeAlign Alignment = VPIntrin.getPointerAlignment();
7768   AAMDNodes AAInfo = VPIntrin.getAAMetadata();
7769   SDValue ST;
7770   if (!Alignment)
7771     Alignment = DAG.getEVTAlign(VT);
7772   SDValue Ptr = OpValues[1];
7773   SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7774   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7775       MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore,
7776       MemoryLocation::UnknownSize, *Alignment, AAInfo);
7777   ST = DAG.getStoreVP(getMemoryRoot(), DL, OpValues[0], Ptr, Offset,
7778                       OpValues[2], OpValues[3], VT, MMO, ISD::UNINDEXED,
7779                       /* IsTruncating */ false, /*IsCompressing*/ false);
7780   DAG.setRoot(ST);
7781   setValue(&VPIntrin, ST);
7782 }
7783 
7784 void SelectionDAGBuilder::visitVPScatter(
7785     const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
7786   SDLoc DL = getCurSDLoc();
7787   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7788   Value *PtrOperand = VPIntrin.getArgOperand(1);
7789   EVT VT = OpValues[0].getValueType();
7790   MaybeAlign Alignment = VPIntrin.getPointerAlignment();
7791   AAMDNodes AAInfo = VPIntrin.getAAMetadata();
7792   SDValue ST;
7793   if (!Alignment)
7794     Alignment = DAG.getEVTAlign(VT.getScalarType());
7795   unsigned AS =
7796       PtrOperand->getType()->getScalarType()->getPointerAddressSpace();
7797   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7798       MachinePointerInfo(AS), MachineMemOperand::MOStore,
7799       MemoryLocation::UnknownSize, *Alignment, AAInfo);
7800   SDValue Base, Index, Scale;
7801   ISD::MemIndexType IndexType;
7802   bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale,
7803                                     this, VPIntrin.getParent(),
7804                                     VT.getScalarStoreSize());
7805   if (!UniformBase) {
7806     Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout()));
7807     Index = getValue(PtrOperand);
7808     IndexType = ISD::SIGNED_SCALED;
7809     Scale =
7810       DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout()));
7811   }
7812   EVT IdxVT = Index.getValueType();
7813   EVT EltTy = IdxVT.getVectorElementType();
7814   if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) {
7815     EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy);
7816     Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index);
7817   }
7818   ST = DAG.getScatterVP(DAG.getVTList(MVT::Other), VT, DL,
7819                         {getMemoryRoot(), OpValues[0], Base, Index, Scale,
7820                          OpValues[2], OpValues[3]},
7821                         MMO, IndexType);
7822   DAG.setRoot(ST);
7823   setValue(&VPIntrin, ST);
7824 }
7825 
7826 void SelectionDAGBuilder::visitVPStridedLoad(
7827     const VPIntrinsic &VPIntrin, EVT VT,
7828     const SmallVectorImpl<SDValue> &OpValues) {
7829   SDLoc DL = getCurSDLoc();
7830   Value *PtrOperand = VPIntrin.getArgOperand(0);
7831   MaybeAlign Alignment = VPIntrin.getPointerAlignment();
7832   if (!Alignment)
7833     Alignment = DAG.getEVTAlign(VT.getScalarType());
7834   AAMDNodes AAInfo = VPIntrin.getAAMetadata();
7835   const MDNode *Ranges = getRangeMetadata(VPIntrin);
7836   MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo);
7837   bool AddToChain = !AA || !AA->pointsToConstantMemory(ML);
7838   SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
7839   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7840       MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad,
7841       MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges);
7842 
7843   SDValue LD = DAG.getStridedLoadVP(VT, DL, InChain, OpValues[0], OpValues[1],
7844                                     OpValues[2], OpValues[3], MMO,
7845                                     false /*IsExpanding*/);
7846 
7847   if (AddToChain)
7848     PendingLoads.push_back(LD.getValue(1));
7849   setValue(&VPIntrin, LD);
7850 }
7851 
7852 void SelectionDAGBuilder::visitVPStridedStore(
7853     const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
7854   SDLoc DL = getCurSDLoc();
7855   Value *PtrOperand = VPIntrin.getArgOperand(1);
7856   EVT VT = OpValues[0].getValueType();
7857   MaybeAlign Alignment = VPIntrin.getPointerAlignment();
7858   if (!Alignment)
7859     Alignment = DAG.getEVTAlign(VT.getScalarType());
7860   AAMDNodes AAInfo = VPIntrin.getAAMetadata();
7861   MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7862       MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore,
7863       MemoryLocation::UnknownSize, *Alignment, AAInfo);
7864 
7865   SDValue ST = DAG.getStridedStoreVP(
7866       getMemoryRoot(), DL, OpValues[0], OpValues[1],
7867       DAG.getUNDEF(OpValues[1].getValueType()), OpValues[2], OpValues[3],
7868       OpValues[4], VT, MMO, ISD::UNINDEXED, /*IsTruncating*/ false,
7869       /*IsCompressing*/ false);
7870 
7871   DAG.setRoot(ST);
7872   setValue(&VPIntrin, ST);
7873 }
7874 
7875 void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) {
7876   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7877   SDLoc DL = getCurSDLoc();
7878 
7879   ISD::CondCode Condition;
7880   CmpInst::Predicate CondCode = VPIntrin.getPredicate();
7881   bool IsFP = VPIntrin.getOperand(0)->getType()->isFPOrFPVectorTy();
7882   if (IsFP) {
7883     // FIXME: Regular fcmps are FPMathOperators which may have fast-math (nnan)
7884     // flags, but calls that don't return floating-point types can't be
7885     // FPMathOperators, like vp.fcmp. This affects constrained fcmp too.
7886     Condition = getFCmpCondCode(CondCode);
7887     if (TM.Options.NoNaNsFPMath)
7888       Condition = getFCmpCodeWithoutNaN(Condition);
7889   } else {
7890     Condition = getICmpCondCode(CondCode);
7891   }
7892 
7893   SDValue Op1 = getValue(VPIntrin.getOperand(0));
7894   SDValue Op2 = getValue(VPIntrin.getOperand(1));
7895   // #2 is the condition code
7896   SDValue MaskOp = getValue(VPIntrin.getOperand(3));
7897   SDValue EVL = getValue(VPIntrin.getOperand(4));
7898   MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy();
7899   assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) &&
7900          "Unexpected target EVL type");
7901   EVL = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, EVL);
7902 
7903   EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
7904                                                         VPIntrin.getType());
7905   setValue(&VPIntrin,
7906            DAG.getSetCCVP(DL, DestVT, Op1, Op2, Condition, MaskOp, EVL));
7907 }
7908 
7909 void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
7910     const VPIntrinsic &VPIntrin) {
7911   SDLoc DL = getCurSDLoc();
7912   unsigned Opcode = getISDForVPIntrinsic(VPIntrin);
7913 
7914   auto IID = VPIntrin.getIntrinsicID();
7915 
7916   if (const auto *CmpI = dyn_cast<VPCmpIntrinsic>(&VPIntrin))
7917     return visitVPCmp(*CmpI);
7918 
7919   SmallVector<EVT, 4> ValueVTs;
7920   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7921   ComputeValueVTs(TLI, DAG.getDataLayout(), VPIntrin.getType(), ValueVTs);
7922   SDVTList VTs = DAG.getVTList(ValueVTs);
7923 
7924   auto EVLParamPos = VPIntrinsic::getVectorLengthParamPos(IID);
7925 
7926   MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy();
7927   assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) &&
7928          "Unexpected target EVL type");
7929 
7930   // Request operands.
7931   SmallVector<SDValue, 7> OpValues;
7932   for (unsigned I = 0; I < VPIntrin.arg_size(); ++I) {
7933     auto Op = getValue(VPIntrin.getArgOperand(I));
7934     if (I == EVLParamPos)
7935       Op = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, Op);
7936     OpValues.push_back(Op);
7937   }
7938 
7939   switch (Opcode) {
7940   default: {
7941     SDNodeFlags SDFlags;
7942     if (auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
7943       SDFlags.copyFMF(*FPMO);
7944     SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues, SDFlags);
7945     setValue(&VPIntrin, Result);
7946     break;
7947   }
7948   case ISD::VP_LOAD:
7949     visitVPLoad(VPIntrin, ValueVTs[0], OpValues);
7950     break;
7951   case ISD::VP_GATHER:
7952     visitVPGather(VPIntrin, ValueVTs[0], OpValues);
7953     break;
7954   case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
7955     visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues);
7956     break;
7957   case ISD::VP_STORE:
7958     visitVPStore(VPIntrin, OpValues);
7959     break;
7960   case ISD::VP_SCATTER:
7961     visitVPScatter(VPIntrin, OpValues);
7962     break;
7963   case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
7964     visitVPStridedStore(VPIntrin, OpValues);
7965     break;
7966   case ISD::VP_FMULADD: {
7967     assert(OpValues.size() == 5 && "Unexpected number of operands");
7968     SDNodeFlags SDFlags;
7969     if (auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
7970       SDFlags.copyFMF(*FPMO);
7971     if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
7972         TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), ValueVTs[0])) {
7973       setValue(&VPIntrin, DAG.getNode(ISD::VP_FMA, DL, VTs, OpValues, SDFlags));
7974     } else {
7975       SDValue Mul = DAG.getNode(
7976           ISD::VP_FMUL, DL, VTs,
7977           {OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, SDFlags);
7978       SDValue Add =
7979           DAG.getNode(ISD::VP_FADD, DL, VTs,
7980                       {Mul, OpValues[2], OpValues[3], OpValues[4]}, SDFlags);
7981       setValue(&VPIntrin, Add);
7982     }
7983     break;
7984   }
7985   case ISD::VP_IS_FPCLASS: {
7986     const DataLayout DLayout = DAG.getDataLayout();
7987     EVT DestVT = TLI.getValueType(DLayout, VPIntrin.getType());
7988     auto Constant = cast<ConstantSDNode>(OpValues[1])->getZExtValue();
7989     SDValue Check = DAG.getTargetConstant(Constant, DL, MVT::i32);
7990     SDValue V = DAG.getNode(ISD::VP_IS_FPCLASS, DL, DestVT,
7991                             {OpValues[0], Check, OpValues[2], OpValues[3]});
7992     setValue(&VPIntrin, V);
7993     return;
7994   }
7995   case ISD::VP_INTTOPTR: {
7996     SDValue N = OpValues[0];
7997     EVT DestVT = TLI.getValueType(DAG.getDataLayout(), VPIntrin.getType());
7998     EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), VPIntrin.getType());
7999     N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1],
8000                                OpValues[2]);
8001     N = DAG.getVPZExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1],
8002                              OpValues[2]);
8003     setValue(&VPIntrin, N);
8004     break;
8005   }
8006   case ISD::VP_PTRTOINT: {
8007     SDValue N = OpValues[0];
8008     EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
8009                                                           VPIntrin.getType());
8010     EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(),
8011                                        VPIntrin.getOperand(0)->getType());
8012     N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1],
8013                                OpValues[2]);
8014     N = DAG.getVPZExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1],
8015                              OpValues[2]);
8016     setValue(&VPIntrin, N);
8017     break;
8018   }
8019   case ISD::VP_ABS:
8020   case ISD::VP_CTLZ:
8021   case ISD::VP_CTLZ_ZERO_UNDEF:
8022   case ISD::VP_CTTZ:
8023   case ISD::VP_CTTZ_ZERO_UNDEF: {
8024     SDValue Result =
8025         DAG.getNode(Opcode, DL, VTs, {OpValues[0], OpValues[2], OpValues[3]});
8026     setValue(&VPIntrin, Result);
8027     break;
8028   }
8029   }
8030 }
8031 
8032 SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain,
8033                                           const BasicBlock *EHPadBB,
8034                                           MCSymbol *&BeginLabel) {
8035   MachineFunction &MF = DAG.getMachineFunction();
8036   MachineModuleInfo &MMI = MF.getMMI();
8037 
8038   // Insert a label before the invoke call to mark the try range.  This can be
8039   // used to detect deletion of the invoke via the MachineModuleInfo.
8040   BeginLabel = MMI.getContext().createTempSymbol();
8041 
8042   // For SjLj, keep track of which landing pads go with which invokes
8043   // so as to maintain the ordering of pads in the LSDA.
8044   unsigned CallSiteIndex = MMI.getCurrentCallSite();
8045   if (CallSiteIndex) {
8046     MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
8047     LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
8048 
8049     // Now that the call site is handled, stop tracking it.
8050     MMI.setCurrentCallSite(0);
8051   }
8052 
8053   return DAG.getEHLabel(getCurSDLoc(), Chain, BeginLabel);
8054 }
8055 
8056 SDValue SelectionDAGBuilder::lowerEndEH(SDValue Chain, const InvokeInst *II,
8057                                         const BasicBlock *EHPadBB,
8058                                         MCSymbol *BeginLabel) {
8059   assert(BeginLabel && "BeginLabel should've been set");
8060 
8061   MachineFunction &MF = DAG.getMachineFunction();
8062   MachineModuleInfo &MMI = MF.getMMI();
8063 
8064   // Insert a label at the end of the invoke call to mark the try range.  This
8065   // can be used to detect deletion of the invoke via the MachineModuleInfo.
8066   MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
8067   Chain = DAG.getEHLabel(getCurSDLoc(), Chain, EndLabel);
8068 
8069   // Inform MachineModuleInfo of range.
8070   auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
8071   // There is a platform (e.g. wasm) that uses funclet style IR but does not
8072   // actually use outlined funclets and their LSDA info style.
8073   if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) {
8074     assert(II && "II should've been set");
8075     WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
8076     EHInfo->addIPToStateRange(II, BeginLabel, EndLabel);
8077   } else if (!isScopedEHPersonality(Pers)) {
8078     assert(EHPadBB);
8079     MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
8080   }
8081 
8082   return Chain;
8083 }
8084 
8085 std::pair<SDValue, SDValue>
8086 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
8087                                     const BasicBlock *EHPadBB) {
8088   MCSymbol *BeginLabel = nullptr;
8089 
8090   if (EHPadBB) {
8091     // Both PendingLoads and PendingExports must be flushed here;
8092     // this call might not return.
8093     (void)getRoot();
8094     DAG.setRoot(lowerStartEH(getControlRoot(), EHPadBB, BeginLabel));
8095     CLI.setChain(getRoot());
8096   }
8097 
8098   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8099   std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
8100 
8101   assert((CLI.IsTailCall || Result.second.getNode()) &&
8102          "Non-null chain expected with non-tail call!");
8103   assert((Result.second.getNode() || !Result.first.getNode()) &&
8104          "Null value expected with tail call!");
8105 
8106   if (!Result.second.getNode()) {
8107     // As a special case, a null chain means that a tail call has been emitted
8108     // and the DAG root is already updated.
8109     HasTailCall = true;
8110 
8111     // Since there's no actual continuation from this block, nothing can be
8112     // relying on us setting vregs for them.
8113     PendingExports.clear();
8114   } else {
8115     DAG.setRoot(Result.second);
8116   }
8117 
8118   if (EHPadBB) {
8119     DAG.setRoot(lowerEndEH(getRoot(), cast_or_null<InvokeInst>(CLI.CB), EHPadBB,
8120                            BeginLabel));
8121   }
8122 
8123   return Result;
8124 }
8125 
8126 void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee,
8127                                       bool isTailCall,
8128                                       bool isMustTailCall,
8129                                       const BasicBlock *EHPadBB) {
8130   auto &DL = DAG.getDataLayout();
8131   FunctionType *FTy = CB.getFunctionType();
8132   Type *RetTy = CB.getType();
8133 
8134   TargetLowering::ArgListTy Args;
8135   Args.reserve(CB.arg_size());
8136 
8137   const Value *SwiftErrorVal = nullptr;
8138   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8139 
8140   if (isTailCall) {
8141     // Avoid emitting tail calls in functions with the disable-tail-calls
8142     // attribute.
8143     auto *Caller = CB.getParent()->getParent();
8144     if (Caller->getFnAttribute("disable-tail-calls").getValueAsString() ==
8145         "true" && !isMustTailCall)
8146       isTailCall = false;
8147 
8148     // We can't tail call inside a function with a swifterror argument. Lowering
8149     // does not support this yet. It would have to move into the swifterror
8150     // register before the call.
8151     if (TLI.supportSwiftError() &&
8152         Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
8153       isTailCall = false;
8154   }
8155 
8156   for (auto I = CB.arg_begin(), E = CB.arg_end(); I != E; ++I) {
8157     TargetLowering::ArgListEntry Entry;
8158     const Value *V = *I;
8159 
8160     // Skip empty types
8161     if (V->getType()->isEmptyTy())
8162       continue;
8163 
8164     SDValue ArgNode = getValue(V);
8165     Entry.Node = ArgNode; Entry.Ty = V->getType();
8166 
8167     Entry.setAttributes(&CB, I - CB.arg_begin());
8168 
8169     // Use swifterror virtual register as input to the call.
8170     if (Entry.IsSwiftError && TLI.supportSwiftError()) {
8171       SwiftErrorVal = V;
8172       // We find the virtual register for the actual swifterror argument.
8173       // Instead of using the Value, we use the virtual register instead.
8174       Entry.Node =
8175           DAG.getRegister(SwiftError.getOrCreateVRegUseAt(&CB, FuncInfo.MBB, V),
8176                           EVT(TLI.getPointerTy(DL)));
8177     }
8178 
8179     Args.push_back(Entry);
8180 
8181     // If we have an explicit sret argument that is an Instruction, (i.e., it
8182     // might point to function-local memory), we can't meaningfully tail-call.
8183     if (Entry.IsSRet && isa<Instruction>(V))
8184       isTailCall = false;
8185   }
8186 
8187   // If call site has a cfguardtarget operand bundle, create and add an
8188   // additional ArgListEntry.
8189   if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_cfguardtarget)) {
8190     TargetLowering::ArgListEntry Entry;
8191     Value *V = Bundle->Inputs[0];
8192     SDValue ArgNode = getValue(V);
8193     Entry.Node = ArgNode;
8194     Entry.Ty = V->getType();
8195     Entry.IsCFGuardTarget = true;
8196     Args.push_back(Entry);
8197   }
8198 
8199   // Check if target-independent constraints permit a tail call here.
8200   // Target-dependent constraints are checked within TLI->LowerCallTo.
8201   if (isTailCall && !isInTailCallPosition(CB, DAG.getTarget()))
8202     isTailCall = false;
8203 
8204   // Disable tail calls if there is an swifterror argument. Targets have not
8205   // been updated to support tail calls.
8206   if (TLI.supportSwiftError() && SwiftErrorVal)
8207     isTailCall = false;
8208 
8209   ConstantInt *CFIType = nullptr;
8210   if (CB.isIndirectCall()) {
8211     if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_kcfi)) {
8212       if (!TLI.supportKCFIBundles())
8213         report_fatal_error(
8214             "Target doesn't support calls with kcfi operand bundles.");
8215       CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
8216       assert(CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
8217     }
8218   }
8219 
8220   TargetLowering::CallLoweringInfo CLI(DAG);
8221   CLI.setDebugLoc(getCurSDLoc())
8222       .setChain(getRoot())
8223       .setCallee(RetTy, FTy, Callee, std::move(Args), CB)
8224       .setTailCall(isTailCall)
8225       .setConvergent(CB.isConvergent())
8226       .setIsPreallocated(
8227           CB.countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0)
8228       .setCFIType(CFIType);
8229   std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
8230 
8231   if (Result.first.getNode()) {
8232     Result.first = lowerRangeToAssertZExt(DAG, CB, Result.first);
8233     setValue(&CB, Result.first);
8234   }
8235 
8236   // The last element of CLI.InVals has the SDValue for swifterror return.
8237   // Here we copy it to a virtual register and update SwiftErrorMap for
8238   // book-keeping.
8239   if (SwiftErrorVal && TLI.supportSwiftError()) {
8240     // Get the last element of InVals.
8241     SDValue Src = CLI.InVals.back();
8242     Register VReg =
8243         SwiftError.getOrCreateVRegDefAt(&CB, FuncInfo.MBB, SwiftErrorVal);
8244     SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src);
8245     DAG.setRoot(CopyNode);
8246   }
8247 }
8248 
8249 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
8250                              SelectionDAGBuilder &Builder) {
8251   // Check to see if this load can be trivially constant folded, e.g. if the
8252   // input is from a string literal.
8253   if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
8254     // Cast pointer to the type we really want to load.
8255     Type *LoadTy =
8256         Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits());
8257     if (LoadVT.isVector())
8258       LoadTy = FixedVectorType::get(LoadTy, LoadVT.getVectorNumElements());
8259 
8260     LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
8261                                          PointerType::getUnqual(LoadTy));
8262 
8263     if (const Constant *LoadCst =
8264             ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
8265                                          LoadTy, Builder.DAG.getDataLayout()))
8266       return Builder.getValue(LoadCst);
8267   }
8268 
8269   // Otherwise, we have to emit the load.  If the pointer is to unfoldable but
8270   // still constant memory, the input chain can be the entry node.
8271   SDValue Root;
8272   bool ConstantMemory = false;
8273 
8274   // Do not serialize (non-volatile) loads of constant memory with anything.
8275   if (Builder.AA && Builder.AA->pointsToConstantMemory(PtrVal)) {
8276     Root = Builder.DAG.getEntryNode();
8277     ConstantMemory = true;
8278   } else {
8279     // Do not serialize non-volatile loads against each other.
8280     Root = Builder.DAG.getRoot();
8281   }
8282 
8283   SDValue Ptr = Builder.getValue(PtrVal);
8284   SDValue LoadVal =
8285       Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr,
8286                           MachinePointerInfo(PtrVal), Align(1));
8287 
8288   if (!ConstantMemory)
8289     Builder.PendingLoads.push_back(LoadVal.getValue(1));
8290   return LoadVal;
8291 }
8292 
8293 /// Record the value for an instruction that produces an integer result,
8294 /// converting the type where necessary.
8295 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
8296                                                   SDValue Value,
8297                                                   bool IsSigned) {
8298   EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
8299                                                     I.getType(), true);
8300   Value = DAG.getExtOrTrunc(IsSigned, Value, getCurSDLoc(), VT);
8301   setValue(&I, Value);
8302 }
8303 
8304 /// See if we can lower a memcmp/bcmp call into an optimized form. If so, return
8305 /// true and lower it. Otherwise return false, and it will be lowered like a
8306 /// normal call.
8307 /// The caller already checked that \p I calls the appropriate LibFunc with a
8308 /// correct prototype.
8309 bool SelectionDAGBuilder::visitMemCmpBCmpCall(const CallInst &I) {
8310   const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
8311   const Value *Size = I.getArgOperand(2);
8312   const ConstantSDNode *CSize = dyn_cast<ConstantSDNode>(getValue(Size));
8313   if (CSize && CSize->getZExtValue() == 0) {
8314     EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
8315                                                           I.getType(), true);
8316     setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
8317     return true;
8318   }
8319 
8320   const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8321   std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp(
8322       DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS),
8323       getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS));
8324   if (Res.first.getNode()) {
8325     processIntegerCallValue(I, Res.first, true);
8326     PendingLoads.push_back(Res.second);
8327     return true;
8328   }
8329 
8330   // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS)  != 0
8331   // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS)  != 0
8332   if (!CSize || !isOnlyUsedInZeroEqualityComparison(&I))
8333     return false;
8334 
8335   // If the target has a fast compare for the given size, it will return a
8336   // preferred load type for that size. Require that the load VT is legal and
8337   // that the target supports unaligned loads of that type. Otherwise, return
8338   // INVALID.
8339   auto hasFastLoadsAndCompare = [&](unsigned NumBits) {
8340     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8341     MVT LVT = TLI.hasFastEqualityCompare(NumBits);
8342     if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) {
8343       // TODO: Handle 5 byte compare as 4-byte + 1 byte.
8344       // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
8345       // TODO: Check alignment of src and dest ptrs.
8346       unsigned DstAS = LHS->getType()->getPointerAddressSpace();
8347       unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
8348       if (!TLI.isTypeLegal(LVT) ||
8349           !TLI.allowsMisalignedMemoryAccesses(LVT, SrcAS) ||
8350           !TLI.allowsMisalignedMemoryAccesses(LVT, DstAS))
8351         LVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
8352     }
8353 
8354     return LVT;
8355   };
8356 
8357   // This turns into unaligned loads. We only do this if the target natively
8358   // supports the MVT we'll be loading or if it is small enough (<= 4) that
8359   // we'll only produce a small number of byte loads.
8360   MVT LoadVT;
8361   unsigned NumBitsToCompare = CSize->getZExtValue() * 8;
8362   switch (NumBitsToCompare) {
8363   default:
8364     return false;
8365   case 16:
8366     LoadVT = MVT::i16;
8367     break;
8368   case 32:
8369     LoadVT = MVT::i32;
8370     break;
8371   case 64:
8372   case 128:
8373   case 256:
8374     LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
8375     break;
8376   }
8377 
8378   if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE)
8379     return false;
8380 
8381   SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this);
8382   SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this);
8383 
8384   // Bitcast to a wide integer type if the loads are vectors.
8385   if (LoadVT.isVector()) {
8386     EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits());
8387     LoadL = DAG.getBitcast(CmpVT, LoadL);
8388     LoadR = DAG.getBitcast(CmpVT, LoadR);
8389   }
8390 
8391   SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE);
8392   processIntegerCallValue(I, Cmp, false);
8393   return true;
8394 }
8395 
8396 /// See if we can lower a memchr call into an optimized form. If so, return
8397 /// true and lower it. Otherwise return false, and it will be lowered like a
8398 /// normal call.
8399 /// The caller already checked that \p I calls the appropriate LibFunc with a
8400 /// correct prototype.
8401 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
8402   const Value *Src = I.getArgOperand(0);
8403   const Value *Char = I.getArgOperand(1);
8404   const Value *Length = I.getArgOperand(2);
8405 
8406   const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8407   std::pair<SDValue, SDValue> Res =
8408     TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
8409                                 getValue(Src), getValue(Char), getValue(Length),
8410                                 MachinePointerInfo(Src));
8411   if (Res.first.getNode()) {
8412     setValue(&I, Res.first);
8413     PendingLoads.push_back(Res.second);
8414     return true;
8415   }
8416 
8417   return false;
8418 }
8419 
8420 /// See if we can lower a mempcpy call into an optimized form. If so, return
8421 /// true and lower it. Otherwise return false, and it will be lowered like a
8422 /// normal call.
8423 /// The caller already checked that \p I calls the appropriate LibFunc with a
8424 /// correct prototype.
8425 bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
8426   SDValue Dst = getValue(I.getArgOperand(0));
8427   SDValue Src = getValue(I.getArgOperand(1));
8428   SDValue Size = getValue(I.getArgOperand(2));
8429 
8430   Align DstAlign = DAG.InferPtrAlign(Dst).valueOrOne();
8431   Align SrcAlign = DAG.InferPtrAlign(Src).valueOrOne();
8432   // DAG::getMemcpy needs Alignment to be defined.
8433   Align Alignment = std::min(DstAlign, SrcAlign);
8434 
8435   SDLoc sdl = getCurSDLoc();
8436 
8437   // In the mempcpy context we need to pass in a false value for isTailCall
8438   // because the return pointer needs to be adjusted by the size of
8439   // the copied memory.
8440   SDValue Root = getMemoryRoot();
8441   SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Alignment, false, false,
8442                              /*isTailCall=*/false,
8443                              MachinePointerInfo(I.getArgOperand(0)),
8444                              MachinePointerInfo(I.getArgOperand(1)),
8445                              I.getAAMetadata());
8446   assert(MC.getNode() != nullptr &&
8447          "** memcpy should not be lowered as TailCall in mempcpy context **");
8448   DAG.setRoot(MC);
8449 
8450   // Check if Size needs to be truncated or extended.
8451   Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType());
8452 
8453   // Adjust return pointer to point just past the last dst byte.
8454   SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(),
8455                                     Dst, Size);
8456   setValue(&I, DstPlusSize);
8457   return true;
8458 }
8459 
8460 /// See if we can lower a strcpy call into an optimized form.  If so, return
8461 /// true and lower it, otherwise return false and it will be lowered like a
8462 /// normal call.
8463 /// The caller already checked that \p I calls the appropriate LibFunc with a
8464 /// correct prototype.
8465 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
8466   const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
8467 
8468   const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8469   std::pair<SDValue, SDValue> Res =
8470     TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
8471                                 getValue(Arg0), getValue(Arg1),
8472                                 MachinePointerInfo(Arg0),
8473                                 MachinePointerInfo(Arg1), isStpcpy);
8474   if (Res.first.getNode()) {
8475     setValue(&I, Res.first);
8476     DAG.setRoot(Res.second);
8477     return true;
8478   }
8479 
8480   return false;
8481 }
8482 
8483 /// See if we can lower a strcmp call into an optimized form.  If so, return
8484 /// true and lower it, otherwise return false and it will be lowered like a
8485 /// normal call.
8486 /// The caller already checked that \p I calls the appropriate LibFunc with a
8487 /// correct prototype.
8488 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
8489   const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
8490 
8491   const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8492   std::pair<SDValue, SDValue> Res =
8493     TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
8494                                 getValue(Arg0), getValue(Arg1),
8495                                 MachinePointerInfo(Arg0),
8496                                 MachinePointerInfo(Arg1));
8497   if (Res.first.getNode()) {
8498     processIntegerCallValue(I, Res.first, true);
8499     PendingLoads.push_back(Res.second);
8500     return true;
8501   }
8502 
8503   return false;
8504 }
8505 
8506 /// See if we can lower a strlen call into an optimized form.  If so, return
8507 /// true and lower it, otherwise return false and it will be lowered like a
8508 /// normal call.
8509 /// The caller already checked that \p I calls the appropriate LibFunc with a
8510 /// correct prototype.
8511 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
8512   const Value *Arg0 = I.getArgOperand(0);
8513 
8514   const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8515   std::pair<SDValue, SDValue> Res =
8516     TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
8517                                 getValue(Arg0), MachinePointerInfo(Arg0));
8518   if (Res.first.getNode()) {
8519     processIntegerCallValue(I, Res.first, false);
8520     PendingLoads.push_back(Res.second);
8521     return true;
8522   }
8523 
8524   return false;
8525 }
8526 
8527 /// See if we can lower a strnlen call into an optimized form.  If so, return
8528 /// true and lower it, otherwise return false and it will be lowered like a
8529 /// normal call.
8530 /// The caller already checked that \p I calls the appropriate LibFunc with a
8531 /// correct prototype.
8532 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
8533   const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
8534 
8535   const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8536   std::pair<SDValue, SDValue> Res =
8537     TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
8538                                  getValue(Arg0), getValue(Arg1),
8539                                  MachinePointerInfo(Arg0));
8540   if (Res.first.getNode()) {
8541     processIntegerCallValue(I, Res.first, false);
8542     PendingLoads.push_back(Res.second);
8543     return true;
8544   }
8545 
8546   return false;
8547 }
8548 
8549 /// See if we can lower a unary floating-point operation into an SDNode with
8550 /// the specified Opcode.  If so, return true and lower it, otherwise return
8551 /// false and it will be lowered like a normal call.
8552 /// The caller already checked that \p I calls the appropriate LibFunc with a
8553 /// correct prototype.
8554 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
8555                                               unsigned Opcode) {
8556   // We already checked this call's prototype; verify it doesn't modify errno.
8557   if (!I.onlyReadsMemory())
8558     return false;
8559 
8560   SDNodeFlags Flags;
8561   Flags.copyFMF(cast<FPMathOperator>(I));
8562 
8563   SDValue Tmp = getValue(I.getArgOperand(0));
8564   setValue(&I,
8565            DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp, Flags));
8566   return true;
8567 }
8568 
8569 /// See if we can lower a binary floating-point operation into an SDNode with
8570 /// the specified Opcode. If so, return true and lower it. Otherwise return
8571 /// false, and it will be lowered like a normal call.
8572 /// The caller already checked that \p I calls the appropriate LibFunc with a
8573 /// correct prototype.
8574 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
8575                                                unsigned Opcode) {
8576   // We already checked this call's prototype; verify it doesn't modify errno.
8577   if (!I.onlyReadsMemory())
8578     return false;
8579 
8580   SDNodeFlags Flags;
8581   Flags.copyFMF(cast<FPMathOperator>(I));
8582 
8583   SDValue Tmp0 = getValue(I.getArgOperand(0));
8584   SDValue Tmp1 = getValue(I.getArgOperand(1));
8585   EVT VT = Tmp0.getValueType();
8586   setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1, Flags));
8587   return true;
8588 }
8589 
8590 void SelectionDAGBuilder::visitCall(const CallInst &I) {
8591   // Handle inline assembly differently.
8592   if (I.isInlineAsm()) {
8593     visitInlineAsm(I);
8594     return;
8595   }
8596 
8597   diagnoseDontCall(I);
8598 
8599   if (Function *F = I.getCalledFunction()) {
8600     if (F->isDeclaration()) {
8601       // Is this an LLVM intrinsic or a target-specific intrinsic?
8602       unsigned IID = F->getIntrinsicID();
8603       if (!IID)
8604         if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo())
8605           IID = II->getIntrinsicID(F);
8606 
8607       if (IID) {
8608         visitIntrinsicCall(I, IID);
8609         return;
8610       }
8611     }
8612 
8613     // Check for well-known libc/libm calls.  If the function is internal, it
8614     // can't be a library call.  Don't do the check if marked as nobuiltin for
8615     // some reason or the call site requires strict floating point semantics.
8616     LibFunc Func;
8617     if (!I.isNoBuiltin() && !I.isStrictFP() && !F->hasLocalLinkage() &&
8618         F->hasName() && LibInfo->getLibFunc(*F, Func) &&
8619         LibInfo->hasOptimizedCodeGen(Func)) {
8620       switch (Func) {
8621       default: break;
8622       case LibFunc_bcmp:
8623         if (visitMemCmpBCmpCall(I))
8624           return;
8625         break;
8626       case LibFunc_copysign:
8627       case LibFunc_copysignf:
8628       case LibFunc_copysignl:
8629         // We already checked this call's prototype; verify it doesn't modify
8630         // errno.
8631         if (I.onlyReadsMemory()) {
8632           SDValue LHS = getValue(I.getArgOperand(0));
8633           SDValue RHS = getValue(I.getArgOperand(1));
8634           setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
8635                                    LHS.getValueType(), LHS, RHS));
8636           return;
8637         }
8638         break;
8639       case LibFunc_fabs:
8640       case LibFunc_fabsf:
8641       case LibFunc_fabsl:
8642         if (visitUnaryFloatCall(I, ISD::FABS))
8643           return;
8644         break;
8645       case LibFunc_fmin:
8646       case LibFunc_fminf:
8647       case LibFunc_fminl:
8648         if (visitBinaryFloatCall(I, ISD::FMINNUM))
8649           return;
8650         break;
8651       case LibFunc_fmax:
8652       case LibFunc_fmaxf:
8653       case LibFunc_fmaxl:
8654         if (visitBinaryFloatCall(I, ISD::FMAXNUM))
8655           return;
8656         break;
8657       case LibFunc_sin:
8658       case LibFunc_sinf:
8659       case LibFunc_sinl:
8660         if (visitUnaryFloatCall(I, ISD::FSIN))
8661           return;
8662         break;
8663       case LibFunc_cos:
8664       case LibFunc_cosf:
8665       case LibFunc_cosl:
8666         if (visitUnaryFloatCall(I, ISD::FCOS))
8667           return;
8668         break;
8669       case LibFunc_sqrt:
8670       case LibFunc_sqrtf:
8671       case LibFunc_sqrtl:
8672       case LibFunc_sqrt_finite:
8673       case LibFunc_sqrtf_finite:
8674       case LibFunc_sqrtl_finite:
8675         if (visitUnaryFloatCall(I, ISD::FSQRT))
8676           return;
8677         break;
8678       case LibFunc_floor:
8679       case LibFunc_floorf:
8680       case LibFunc_floorl:
8681         if (visitUnaryFloatCall(I, ISD::FFLOOR))
8682           return;
8683         break;
8684       case LibFunc_nearbyint:
8685       case LibFunc_nearbyintf:
8686       case LibFunc_nearbyintl:
8687         if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
8688           return;
8689         break;
8690       case LibFunc_ceil:
8691       case LibFunc_ceilf:
8692       case LibFunc_ceill:
8693         if (visitUnaryFloatCall(I, ISD::FCEIL))
8694           return;
8695         break;
8696       case LibFunc_rint:
8697       case LibFunc_rintf:
8698       case LibFunc_rintl:
8699         if (visitUnaryFloatCall(I, ISD::FRINT))
8700           return;
8701         break;
8702       case LibFunc_round:
8703       case LibFunc_roundf:
8704       case LibFunc_roundl:
8705         if (visitUnaryFloatCall(I, ISD::FROUND))
8706           return;
8707         break;
8708       case LibFunc_trunc:
8709       case LibFunc_truncf:
8710       case LibFunc_truncl:
8711         if (visitUnaryFloatCall(I, ISD::FTRUNC))
8712           return;
8713         break;
8714       case LibFunc_log2:
8715       case LibFunc_log2f:
8716       case LibFunc_log2l:
8717         if (visitUnaryFloatCall(I, ISD::FLOG2))
8718           return;
8719         break;
8720       case LibFunc_exp2:
8721       case LibFunc_exp2f:
8722       case LibFunc_exp2l:
8723         if (visitUnaryFloatCall(I, ISD::FEXP2))
8724           return;
8725         break;
8726       case LibFunc_exp10:
8727       case LibFunc_exp10f:
8728       case LibFunc_exp10l:
8729         if (visitUnaryFloatCall(I, ISD::FEXP10))
8730           return;
8731         break;
8732       case LibFunc_ldexp:
8733       case LibFunc_ldexpf:
8734       case LibFunc_ldexpl:
8735         if (visitBinaryFloatCall(I, ISD::FLDEXP))
8736           return;
8737         break;
8738       case LibFunc_memcmp:
8739         if (visitMemCmpBCmpCall(I))
8740           return;
8741         break;
8742       case LibFunc_mempcpy:
8743         if (visitMemPCpyCall(I))
8744           return;
8745         break;
8746       case LibFunc_memchr:
8747         if (visitMemChrCall(I))
8748           return;
8749         break;
8750       case LibFunc_strcpy:
8751         if (visitStrCpyCall(I, false))
8752           return;
8753         break;
8754       case LibFunc_stpcpy:
8755         if (visitStrCpyCall(I, true))
8756           return;
8757         break;
8758       case LibFunc_strcmp:
8759         if (visitStrCmpCall(I))
8760           return;
8761         break;
8762       case LibFunc_strlen:
8763         if (visitStrLenCall(I))
8764           return;
8765         break;
8766       case LibFunc_strnlen:
8767         if (visitStrNLenCall(I))
8768           return;
8769         break;
8770       }
8771     }
8772   }
8773 
8774   // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
8775   // have to do anything here to lower funclet bundles.
8776   // CFGuardTarget bundles are lowered in LowerCallTo.
8777   assert(!I.hasOperandBundlesOtherThan(
8778              {LLVMContext::OB_deopt, LLVMContext::OB_funclet,
8779               LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated,
8780               LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi}) &&
8781          "Cannot lower calls with arbitrary operand bundles!");
8782 
8783   SDValue Callee = getValue(I.getCalledOperand());
8784 
8785   if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
8786     LowerCallSiteWithDeoptBundle(&I, Callee, nullptr);
8787   else
8788     // Check if we can potentially perform a tail call. More detailed checking
8789     // is be done within LowerCallTo, after more information about the call is
8790     // known.
8791     LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall());
8792 }
8793 
8794 namespace {
8795 
8796 /// AsmOperandInfo - This contains information for each constraint that we are
8797 /// lowering.
8798 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
8799 public:
8800   /// CallOperand - If this is the result output operand or a clobber
8801   /// this is null, otherwise it is the incoming operand to the CallInst.
8802   /// This gets modified as the asm is processed.
8803   SDValue CallOperand;
8804 
8805   /// AssignedRegs - If this is a register or register class operand, this
8806   /// contains the set of register corresponding to the operand.
8807   RegsForValue AssignedRegs;
8808 
8809   explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
8810     : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) {
8811   }
8812 
8813   /// Whether or not this operand accesses memory
8814   bool hasMemory(const TargetLowering &TLI) const {
8815     // Indirect operand accesses access memory.
8816     if (isIndirect)
8817       return true;
8818 
8819     for (const auto &Code : Codes)
8820       if (TLI.getConstraintType(Code) == TargetLowering::C_Memory)
8821         return true;
8822 
8823     return false;
8824   }
8825 };
8826 
8827 
8828 } // end anonymous namespace
8829 
8830 /// Make sure that the output operand \p OpInfo and its corresponding input
8831 /// operand \p MatchingOpInfo have compatible constraint types (otherwise error
8832 /// out).
8833 static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
8834                                SDISelAsmOperandInfo &MatchingOpInfo,
8835                                SelectionDAG &DAG) {
8836   if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
8837     return;
8838 
8839   const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
8840   const auto &TLI = DAG.getTargetLoweringInfo();
8841 
8842   std::pair<unsigned, const TargetRegisterClass *> MatchRC =
8843       TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
8844                                        OpInfo.ConstraintVT);
8845   std::pair<unsigned, const TargetRegisterClass *> InputRC =
8846       TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
8847                                        MatchingOpInfo.ConstraintVT);
8848   if ((OpInfo.ConstraintVT.isInteger() !=
8849        MatchingOpInfo.ConstraintVT.isInteger()) ||
8850       (MatchRC.second != InputRC.second)) {
8851     // FIXME: error out in a more elegant fashion
8852     report_fatal_error("Unsupported asm: input constraint"
8853                        " with a matching output constraint of"
8854                        " incompatible type!");
8855   }
8856   MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
8857 }
8858 
8859 /// Get a direct memory input to behave well as an indirect operand.
8860 /// This may introduce stores, hence the need for a \p Chain.
8861 /// \return The (possibly updated) chain.
8862 static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
8863                                         SDISelAsmOperandInfo &OpInfo,
8864                                         SelectionDAG &DAG) {
8865   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8866 
8867   // If we don't have an indirect input, put it in the constpool if we can,
8868   // otherwise spill it to a stack slot.
8869   // TODO: This isn't quite right. We need to handle these according to
8870   // the addressing mode that the constraint wants. Also, this may take
8871   // an additional register for the computation and we don't want that
8872   // either.
8873 
8874   // If the operand is a float, integer, or vector constant, spill to a
8875   // constant pool entry to get its address.
8876   const Value *OpVal = OpInfo.CallOperandVal;
8877   if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
8878       isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
8879     OpInfo.CallOperand = DAG.getConstantPool(
8880         cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
8881     return Chain;
8882   }
8883 
8884   // Otherwise, create a stack slot and emit a store to it before the asm.
8885   Type *Ty = OpVal->getType();
8886   auto &DL = DAG.getDataLayout();
8887   uint64_t TySize = DL.getTypeAllocSize(Ty);
8888   MachineFunction &MF = DAG.getMachineFunction();
8889   int SSFI = MF.getFrameInfo().CreateStackObject(
8890       TySize, DL.getPrefTypeAlign(Ty), false);
8891   SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL));
8892   Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
8893                             MachinePointerInfo::getFixedStack(MF, SSFI),
8894                             TLI.getMemValueType(DL, Ty));
8895   OpInfo.CallOperand = StackSlot;
8896 
8897   return Chain;
8898 }
8899 
8900 /// GetRegistersForValue - Assign registers (virtual or physical) for the
8901 /// specified operand.  We prefer to assign virtual registers, to allow the
8902 /// register allocator to handle the assignment process.  However, if the asm
8903 /// uses features that we can't model on machineinstrs, we have SDISel do the
8904 /// allocation.  This produces generally horrible, but correct, code.
8905 ///
8906 ///   OpInfo describes the operand
8907 ///   RefOpInfo describes the matching operand if any, the operand otherwise
8908 static std::optional<unsigned>
8909 getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL,
8910                      SDISelAsmOperandInfo &OpInfo,
8911                      SDISelAsmOperandInfo &RefOpInfo) {
8912   LLVMContext &Context = *DAG.getContext();
8913   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8914 
8915   MachineFunction &MF = DAG.getMachineFunction();
8916   SmallVector<unsigned, 4> Regs;
8917   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8918 
8919   // No work to do for memory/address operands.
8920   if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
8921       OpInfo.ConstraintType == TargetLowering::C_Address)
8922     return std::nullopt;
8923 
8924   // If this is a constraint for a single physreg, or a constraint for a
8925   // register class, find it.
8926   unsigned AssignedReg;
8927   const TargetRegisterClass *RC;
8928   std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
8929       &TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
8930   // RC is unset only on failure. Return immediately.
8931   if (!RC)
8932     return std::nullopt;
8933 
8934   // Get the actual register value type.  This is important, because the user
8935   // may have asked for (e.g.) the AX register in i32 type.  We need to
8936   // remember that AX is actually i16 to get the right extension.
8937   const MVT RegVT = *TRI.legalclasstypes_begin(*RC);
8938 
8939   if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) {
8940     // If this is an FP operand in an integer register (or visa versa), or more
8941     // generally if the operand value disagrees with the register class we plan
8942     // to stick it in, fix the operand type.
8943     //
8944     // If this is an input value, the bitcast to the new type is done now.
8945     // Bitcast for output value is done at the end of visitInlineAsm().
8946     if ((OpInfo.Type == InlineAsm::isOutput ||
8947          OpInfo.Type == InlineAsm::isInput) &&
8948         !TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) {
8949       // Try to convert to the first EVT that the reg class contains.  If the
8950       // types are identical size, use a bitcast to convert (e.g. two differing
8951       // vector types).  Note: output bitcast is done at the end of
8952       // visitInlineAsm().
8953       if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
8954         // Exclude indirect inputs while they are unsupported because the code
8955         // to perform the load is missing and thus OpInfo.CallOperand still
8956         // refers to the input address rather than the pointed-to value.
8957         if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect)
8958           OpInfo.CallOperand =
8959               DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand);
8960         OpInfo.ConstraintVT = RegVT;
8961         // If the operand is an FP value and we want it in integer registers,
8962         // use the corresponding integer type. This turns an f64 value into
8963         // i64, which can be passed with two i32 values on a 32-bit machine.
8964       } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
8965         MVT VT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
8966         if (OpInfo.Type == InlineAsm::isInput)
8967           OpInfo.CallOperand =
8968               DAG.getNode(ISD::BITCAST, DL, VT, OpInfo.CallOperand);
8969         OpInfo.ConstraintVT = VT;
8970       }
8971     }
8972   }
8973 
8974   // No need to allocate a matching input constraint since the constraint it's
8975   // matching to has already been allocated.
8976   if (OpInfo.isMatchingInputConstraint())
8977     return std::nullopt;
8978 
8979   EVT ValueVT = OpInfo.ConstraintVT;
8980   if (OpInfo.ConstraintVT == MVT::Other)
8981     ValueVT = RegVT;
8982 
8983   // Initialize NumRegs.
8984   unsigned NumRegs = 1;
8985   if (OpInfo.ConstraintVT != MVT::Other)
8986     NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT, RegVT);
8987 
8988   // If this is a constraint for a specific physical register, like {r17},
8989   // assign it now.
8990 
8991   // If this associated to a specific register, initialize iterator to correct
8992   // place. If virtual, make sure we have enough registers
8993 
8994   // Initialize iterator if necessary
8995   TargetRegisterClass::iterator I = RC->begin();
8996   MachineRegisterInfo &RegInfo = MF.getRegInfo();
8997 
8998   // Do not check for single registers.
8999   if (AssignedReg) {
9000     I = std::find(I, RC->end(), AssignedReg);
9001     if (I == RC->end()) {
9002       // RC does not contain the selected register, which indicates a
9003       // mismatch between the register and the required type/bitwidth.
9004       return {AssignedReg};
9005     }
9006   }
9007 
9008   for (; NumRegs; --NumRegs, ++I) {
9009     assert(I != RC->end() && "Ran out of registers to allocate!");
9010     Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
9011     Regs.push_back(R);
9012   }
9013 
9014   OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
9015   return std::nullopt;
9016 }
9017 
9018 static unsigned
9019 findMatchingInlineAsmOperand(unsigned OperandNo,
9020                              const std::vector<SDValue> &AsmNodeOperands) {
9021   // Scan until we find the definition we already emitted of this operand.
9022   unsigned CurOp = InlineAsm::Op_FirstOperand;
9023   for (; OperandNo; --OperandNo) {
9024     // Advance to the next operand.
9025     unsigned OpFlag =
9026         cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
9027     const InlineAsm::Flag F(OpFlag);
9028     assert(
9029         (F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isMemKind()) &&
9030         "Skipped past definitions?");
9031     CurOp += F.getNumOperandRegisters() + 1;
9032   }
9033   return CurOp;
9034 }
9035 
9036 namespace {
9037 
9038 class ExtraFlags {
9039   unsigned Flags = 0;
9040 
9041 public:
9042   explicit ExtraFlags(const CallBase &Call) {
9043     const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand());
9044     if (IA->hasSideEffects())
9045       Flags |= InlineAsm::Extra_HasSideEffects;
9046     if (IA->isAlignStack())
9047       Flags |= InlineAsm::Extra_IsAlignStack;
9048     if (Call.isConvergent())
9049       Flags |= InlineAsm::Extra_IsConvergent;
9050     Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
9051   }
9052 
9053   void update(const TargetLowering::AsmOperandInfo &OpInfo) {
9054     // Ideally, we would only check against memory constraints.  However, the
9055     // meaning of an Other constraint can be target-specific and we can't easily
9056     // reason about it.  Therefore, be conservative and set MayLoad/MayStore
9057     // for Other constraints as well.
9058     if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
9059         OpInfo.ConstraintType == TargetLowering::C_Other) {
9060       if (OpInfo.Type == InlineAsm::isInput)
9061         Flags |= InlineAsm::Extra_MayLoad;
9062       else if (OpInfo.Type == InlineAsm::isOutput)
9063         Flags |= InlineAsm::Extra_MayStore;
9064       else if (OpInfo.Type == InlineAsm::isClobber)
9065         Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
9066     }
9067   }
9068 
9069   unsigned get() const { return Flags; }
9070 };
9071 
9072 } // end anonymous namespace
9073 
9074 static bool isFunction(SDValue Op) {
9075   if (Op && Op.getOpcode() == ISD::GlobalAddress) {
9076     if (auto *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
9077       auto Fn = dyn_cast_or_null<Function>(GA->getGlobal());
9078 
9079       // In normal "call dllimport func" instruction (non-inlineasm) it force
9080       // indirect access by specifing call opcode. And usually specially print
9081       // asm with indirect symbol (i.g: "*") according to opcode. Inline asm can
9082       // not do in this way now. (In fact, this is similar with "Data Access"
9083       // action). So here we ignore dllimport function.
9084       if (Fn && !Fn->hasDLLImportStorageClass())
9085         return true;
9086     }
9087   }
9088   return false;
9089 }
9090 
9091 /// visitInlineAsm - Handle a call to an InlineAsm object.
9092 void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
9093                                          const BasicBlock *EHPadBB) {
9094   const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand());
9095 
9096   /// ConstraintOperands - Information about all of the constraints.
9097   SmallVector<SDISelAsmOperandInfo, 16> ConstraintOperands;
9098 
9099   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9100   TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
9101       DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), Call);
9102 
9103   // First Pass: Calculate HasSideEffects and ExtraFlags (AlignStack,
9104   // AsmDialect, MayLoad, MayStore).
9105   bool HasSideEffect = IA->hasSideEffects();
9106   ExtraFlags ExtraInfo(Call);
9107 
9108   for (auto &T : TargetConstraints) {
9109     ConstraintOperands.push_back(SDISelAsmOperandInfo(T));
9110     SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
9111 
9112     if (OpInfo.CallOperandVal)
9113       OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
9114 
9115     if (!HasSideEffect)
9116       HasSideEffect = OpInfo.hasMemory(TLI);
9117 
9118     // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
9119     // FIXME: Could we compute this on OpInfo rather than T?
9120 
9121     // Compute the constraint code and ConstraintType to use.
9122     TLI.ComputeConstraintToUse(T, SDValue());
9123 
9124     if (T.ConstraintType == TargetLowering::C_Immediate &&
9125         OpInfo.CallOperand && !isa<ConstantSDNode>(OpInfo.CallOperand))
9126       // We've delayed emitting a diagnostic like the "n" constraint because
9127       // inlining could cause an integer showing up.
9128       return emitInlineAsmError(Call, "constraint '" + Twine(T.ConstraintCode) +
9129                                           "' expects an integer constant "
9130                                           "expression");
9131 
9132     ExtraInfo.update(T);
9133   }
9134 
9135   // We won't need to flush pending loads if this asm doesn't touch
9136   // memory and is nonvolatile.
9137   SDValue Glue, Chain = (HasSideEffect) ? getRoot() : DAG.getRoot();
9138 
9139   bool EmitEHLabels = isa<InvokeInst>(Call);
9140   if (EmitEHLabels) {
9141     assert(EHPadBB && "InvokeInst must have an EHPadBB");
9142   }
9143   bool IsCallBr = isa<CallBrInst>(Call);
9144 
9145   if (IsCallBr || EmitEHLabels) {
9146     // If this is a callbr or invoke we need to flush pending exports since
9147     // inlineasm_br and invoke are terminators.
9148     // We need to do this before nodes are glued to the inlineasm_br node.
9149     Chain = getControlRoot();
9150   }
9151 
9152   MCSymbol *BeginLabel = nullptr;
9153   if (EmitEHLabels) {
9154     Chain = lowerStartEH(Chain, EHPadBB, BeginLabel);
9155   }
9156 
9157   int OpNo = -1;
9158   SmallVector<StringRef> AsmStrs;
9159   IA->collectAsmStrs(AsmStrs);
9160 
9161   // Second pass over the constraints: compute which constraint option to use.
9162   for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9163     if (OpInfo.hasArg() || OpInfo.Type == InlineAsm::isOutput)
9164       OpNo++;
9165 
9166     // If this is an output operand with a matching input operand, look up the
9167     // matching input. If their types mismatch, e.g. one is an integer, the
9168     // other is floating point, or their sizes are different, flag it as an
9169     // error.
9170     if (OpInfo.hasMatchingInput()) {
9171       SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
9172       patchMatchingInput(OpInfo, Input, DAG);
9173     }
9174 
9175     // Compute the constraint code and ConstraintType to use.
9176     TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
9177 
9178     if ((OpInfo.ConstraintType == TargetLowering::C_Memory &&
9179          OpInfo.Type == InlineAsm::isClobber) ||
9180         OpInfo.ConstraintType == TargetLowering::C_Address)
9181       continue;
9182 
9183     // In Linux PIC model, there are 4 cases about value/label addressing:
9184     //
9185     // 1: Function call or Label jmp inside the module.
9186     // 2: Data access (such as global variable, static variable) inside module.
9187     // 3: Function call or Label jmp outside the module.
9188     // 4: Data access (such as global variable) outside the module.
9189     //
9190     // Due to current llvm inline asm architecture designed to not "recognize"
9191     // the asm code, there are quite troubles for us to treat mem addressing
9192     // differently for same value/adress used in different instuctions.
9193     // For example, in pic model, call a func may in plt way or direclty
9194     // pc-related, but lea/mov a function adress may use got.
9195     //
9196     // Here we try to "recognize" function call for the case 1 and case 3 in
9197     // inline asm. And try to adjust the constraint for them.
9198     //
9199     // TODO: Due to current inline asm didn't encourage to jmp to the outsider
9200     // label, so here we don't handle jmp function label now, but we need to
9201     // enhance it (especilly in PIC model) if we meet meaningful requirements.
9202     if (OpInfo.isIndirect && isFunction(OpInfo.CallOperand) &&
9203         TLI.isInlineAsmTargetBranch(AsmStrs, OpNo) &&
9204         TM.getCodeModel() != CodeModel::Large) {
9205       OpInfo.isIndirect = false;
9206       OpInfo.ConstraintType = TargetLowering::C_Address;
9207     }
9208 
9209     // If this is a memory input, and if the operand is not indirect, do what we
9210     // need to provide an address for the memory input.
9211     if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
9212         !OpInfo.isIndirect) {
9213       assert((OpInfo.isMultipleAlternative ||
9214               (OpInfo.Type == InlineAsm::isInput)) &&
9215              "Can only indirectify direct input operands!");
9216 
9217       // Memory operands really want the address of the value.
9218       Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG);
9219 
9220       // There is no longer a Value* corresponding to this operand.
9221       OpInfo.CallOperandVal = nullptr;
9222 
9223       // It is now an indirect operand.
9224       OpInfo.isIndirect = true;
9225     }
9226 
9227   }
9228 
9229   // AsmNodeOperands - The operands for the ISD::INLINEASM node.
9230   std::vector<SDValue> AsmNodeOperands;
9231   AsmNodeOperands.push_back(SDValue());  // reserve space for input chain
9232   AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
9233       IA->getAsmString().c_str(), TLI.getProgramPointerTy(DAG.getDataLayout())));
9234 
9235   // If we have a !srcloc metadata node associated with it, we want to attach
9236   // this to the ultimately generated inline asm machineinstr.  To do this, we
9237   // pass in the third operand as this (potentially null) inline asm MDNode.
9238   const MDNode *SrcLoc = Call.getMetadata("srcloc");
9239   AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
9240 
9241   // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
9242   // bits as operand 3.
9243   AsmNodeOperands.push_back(DAG.getTargetConstant(
9244       ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
9245 
9246   // Third pass: Loop over operands to prepare DAG-level operands.. As part of
9247   // this, assign virtual and physical registers for inputs and otput.
9248   for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9249     // Assign Registers.
9250     SDISelAsmOperandInfo &RefOpInfo =
9251         OpInfo.isMatchingInputConstraint()
9252             ? ConstraintOperands[OpInfo.getMatchedOperand()]
9253             : OpInfo;
9254     const auto RegError =
9255         getRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo);
9256     if (RegError) {
9257       const MachineFunction &MF = DAG.getMachineFunction();
9258       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
9259       const char *RegName = TRI.getName(*RegError);
9260       emitInlineAsmError(Call, "register '" + Twine(RegName) +
9261                                    "' allocated for constraint '" +
9262                                    Twine(OpInfo.ConstraintCode) +
9263                                    "' does not match required type");
9264       return;
9265     }
9266 
9267     auto DetectWriteToReservedRegister = [&]() {
9268       const MachineFunction &MF = DAG.getMachineFunction();
9269       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
9270       for (unsigned Reg : OpInfo.AssignedRegs.Regs) {
9271         if (Register::isPhysicalRegister(Reg) &&
9272             TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
9273           const char *RegName = TRI.getName(Reg);
9274           emitInlineAsmError(Call, "write to reserved register '" +
9275                                        Twine(RegName) + "'");
9276           return true;
9277         }
9278       }
9279       return false;
9280     };
9281     assert((OpInfo.ConstraintType != TargetLowering::C_Address ||
9282             (OpInfo.Type == InlineAsm::isInput &&
9283              !OpInfo.isMatchingInputConstraint())) &&
9284            "Only address as input operand is allowed.");
9285 
9286     switch (OpInfo.Type) {
9287     case InlineAsm::isOutput:
9288       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
9289         const InlineAsm::ConstraintCode ConstraintID =
9290             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
9291         assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
9292                "Failed to convert memory constraint code to constraint id.");
9293 
9294         // Add information to the INLINEASM node to know about this output.
9295         InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
9296         OpFlags.setMemConstraint(ConstraintID);
9297         AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
9298                                                         MVT::i32));
9299         AsmNodeOperands.push_back(OpInfo.CallOperand);
9300       } else {
9301         // Otherwise, this outputs to a register (directly for C_Register /
9302         // C_RegisterClass, and a target-defined fashion for
9303         // C_Immediate/C_Other). Find a register that we can use.
9304         if (OpInfo.AssignedRegs.Regs.empty()) {
9305           emitInlineAsmError(
9306               Call, "couldn't allocate output register for constraint '" +
9307                         Twine(OpInfo.ConstraintCode) + "'");
9308           return;
9309         }
9310 
9311         if (DetectWriteToReservedRegister())
9312           return;
9313 
9314         // Add information to the INLINEASM node to know that this register is
9315         // set.
9316         OpInfo.AssignedRegs.AddInlineAsmOperands(
9317             OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
9318                                   : InlineAsm::Kind::RegDef,
9319             false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
9320       }
9321       break;
9322 
9323     case InlineAsm::isInput:
9324     case InlineAsm::isLabel: {
9325       SDValue InOperandVal = OpInfo.CallOperand;
9326 
9327       if (OpInfo.isMatchingInputConstraint()) {
9328         // If this is required to match an output register we have already set,
9329         // just use its register.
9330         auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
9331                                                   AsmNodeOperands);
9332         InlineAsm::Flag Flag(
9333             cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue());
9334         if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) {
9335           if (OpInfo.isIndirect) {
9336             // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
9337             emitInlineAsmError(Call, "inline asm not supported yet: "
9338                                      "don't know how to handle tied "
9339                                      "indirect register inputs");
9340             return;
9341           }
9342 
9343           SmallVector<unsigned, 4> Regs;
9344           MachineFunction &MF = DAG.getMachineFunction();
9345           MachineRegisterInfo &MRI = MF.getRegInfo();
9346           const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
9347           auto *R = cast<RegisterSDNode>(AsmNodeOperands[CurOp+1]);
9348           Register TiedReg = R->getReg();
9349           MVT RegVT = R->getSimpleValueType(0);
9350           const TargetRegisterClass *RC =
9351               TiedReg.isVirtual()     ? MRI.getRegClass(TiedReg)
9352               : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT)
9353                                       : TRI.getMinimalPhysRegClass(TiedReg);
9354           for (unsigned i = 0, e = Flag.getNumOperandRegisters(); i != e; ++i)
9355             Regs.push_back(MRI.createVirtualRegister(RC));
9356 
9357           RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
9358 
9359           SDLoc dl = getCurSDLoc();
9360           // Use the produced MatchedRegs object to
9361           MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, &Call);
9362           MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, true,
9363                                            OpInfo.getMatchedOperand(), dl, DAG,
9364                                            AsmNodeOperands);
9365           break;
9366         }
9367 
9368         assert(Flag.isMemKind() && "Unknown matching constraint!");
9369         assert(Flag.getNumOperandRegisters() == 1 &&
9370                "Unexpected number of operands");
9371         // Add information to the INLINEASM node to know about this input.
9372         // See InlineAsm.h isUseOperandTiedToDef.
9373         Flag.clearMemConstraint();
9374         Flag.setMatchingOp(OpInfo.getMatchedOperand());
9375         AsmNodeOperands.push_back(DAG.getTargetConstant(
9376             Flag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
9377         AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
9378         break;
9379       }
9380 
9381       // Treat indirect 'X' constraint as memory.
9382       if (OpInfo.ConstraintType == TargetLowering::C_Other &&
9383           OpInfo.isIndirect)
9384         OpInfo.ConstraintType = TargetLowering::C_Memory;
9385 
9386       if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
9387           OpInfo.ConstraintType == TargetLowering::C_Other) {
9388         std::vector<SDValue> Ops;
9389         TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
9390                                           Ops, DAG);
9391         if (Ops.empty()) {
9392           if (OpInfo.ConstraintType == TargetLowering::C_Immediate)
9393             if (isa<ConstantSDNode>(InOperandVal)) {
9394               emitInlineAsmError(Call, "value out of range for constraint '" +
9395                                            Twine(OpInfo.ConstraintCode) + "'");
9396               return;
9397             }
9398 
9399           emitInlineAsmError(Call,
9400                              "invalid operand for inline asm constraint '" +
9401                                  Twine(OpInfo.ConstraintCode) + "'");
9402           return;
9403         }
9404 
9405         // Add information to the INLINEASM node to know about this input.
9406         InlineAsm::Flag ResOpType(InlineAsm::Kind::Imm, Ops.size());
9407         AsmNodeOperands.push_back(DAG.getTargetConstant(
9408             ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
9409         llvm::append_range(AsmNodeOperands, Ops);
9410         break;
9411       }
9412 
9413       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
9414         assert((OpInfo.isIndirect ||
9415                 OpInfo.ConstraintType != TargetLowering::C_Memory) &&
9416                "Operand must be indirect to be a mem!");
9417         assert(InOperandVal.getValueType() ==
9418                    TLI.getPointerTy(DAG.getDataLayout()) &&
9419                "Memory operands expect pointer values");
9420 
9421         const InlineAsm::ConstraintCode ConstraintID =
9422             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
9423         assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
9424                "Failed to convert memory constraint code to constraint id.");
9425 
9426         // Add information to the INLINEASM node to know about this input.
9427         InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
9428         ResOpType.setMemConstraint(ConstraintID);
9429         AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
9430                                                         getCurSDLoc(),
9431                                                         MVT::i32));
9432         AsmNodeOperands.push_back(InOperandVal);
9433         break;
9434       }
9435 
9436       if (OpInfo.ConstraintType == TargetLowering::C_Address) {
9437         const InlineAsm::ConstraintCode ConstraintID =
9438             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
9439         assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
9440                "Failed to convert memory constraint code to constraint id.");
9441 
9442         InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
9443 
9444         SDValue AsmOp = InOperandVal;
9445         if (isFunction(InOperandVal)) {
9446           auto *GA = cast<GlobalAddressSDNode>(InOperandVal);
9447           ResOpType = InlineAsm::Flag(InlineAsm::Kind::Func, 1);
9448           AsmOp = DAG.getTargetGlobalAddress(GA->getGlobal(), getCurSDLoc(),
9449                                              InOperandVal.getValueType(),
9450                                              GA->getOffset());
9451         }
9452 
9453         // Add information to the INLINEASM node to know about this input.
9454         ResOpType.setMemConstraint(ConstraintID);
9455 
9456         AsmNodeOperands.push_back(
9457             DAG.getTargetConstant(ResOpType, getCurSDLoc(), MVT::i32));
9458 
9459         AsmNodeOperands.push_back(AsmOp);
9460         break;
9461       }
9462 
9463       assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
9464               OpInfo.ConstraintType == TargetLowering::C_Register) &&
9465              "Unknown constraint type!");
9466 
9467       // TODO: Support this.
9468       if (OpInfo.isIndirect) {
9469         emitInlineAsmError(
9470             Call, "Don't know how to handle indirect register inputs yet "
9471                   "for constraint '" +
9472                       Twine(OpInfo.ConstraintCode) + "'");
9473         return;
9474       }
9475 
9476       // Copy the input into the appropriate registers.
9477       if (OpInfo.AssignedRegs.Regs.empty()) {
9478         emitInlineAsmError(Call,
9479                            "couldn't allocate input reg for constraint '" +
9480                                Twine(OpInfo.ConstraintCode) + "'");
9481         return;
9482       }
9483 
9484       if (DetectWriteToReservedRegister())
9485         return;
9486 
9487       SDLoc dl = getCurSDLoc();
9488 
9489       OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue,
9490                                         &Call);
9491 
9492       OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, false,
9493                                                0, dl, DAG, AsmNodeOperands);
9494       break;
9495     }
9496     case InlineAsm::isClobber:
9497       // Add the clobbered value to the operand list, so that the register
9498       // allocator is aware that the physreg got clobbered.
9499       if (!OpInfo.AssignedRegs.Regs.empty())
9500         OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::Clobber,
9501                                                  false, 0, getCurSDLoc(), DAG,
9502                                                  AsmNodeOperands);
9503       break;
9504     }
9505   }
9506 
9507   // Finish up input operands.  Set the input chain and add the flag last.
9508   AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
9509   if (Glue.getNode()) AsmNodeOperands.push_back(Glue);
9510 
9511   unsigned ISDOpc = IsCallBr ? ISD::INLINEASM_BR : ISD::INLINEASM;
9512   Chain = DAG.getNode(ISDOpc, getCurSDLoc(),
9513                       DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
9514   Glue = Chain.getValue(1);
9515 
9516   // Do additional work to generate outputs.
9517 
9518   SmallVector<EVT, 1> ResultVTs;
9519   SmallVector<SDValue, 1> ResultValues;
9520   SmallVector<SDValue, 8> OutChains;
9521 
9522   llvm::Type *CallResultType = Call.getType();
9523   ArrayRef<Type *> ResultTypes;
9524   if (StructType *StructResult = dyn_cast<StructType>(CallResultType))
9525     ResultTypes = StructResult->elements();
9526   else if (!CallResultType->isVoidTy())
9527     ResultTypes = ArrayRef(CallResultType);
9528 
9529   auto CurResultType = ResultTypes.begin();
9530   auto handleRegAssign = [&](SDValue V) {
9531     assert(CurResultType != ResultTypes.end() && "Unexpected value");
9532     assert((*CurResultType)->isSized() && "Unexpected unsized type");
9533     EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), *CurResultType);
9534     ++CurResultType;
9535     // If the type of the inline asm call site return value is different but has
9536     // same size as the type of the asm output bitcast it.  One example of this
9537     // is for vectors with different width / number of elements.  This can
9538     // happen for register classes that can contain multiple different value
9539     // types.  The preg or vreg allocated may not have the same VT as was
9540     // expected.
9541     //
9542     // This can also happen for a return value that disagrees with the register
9543     // class it is put in, eg. a double in a general-purpose register on a
9544     // 32-bit machine.
9545     if (ResultVT != V.getValueType() &&
9546         ResultVT.getSizeInBits() == V.getValueSizeInBits())
9547       V = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, V);
9548     else if (ResultVT != V.getValueType() && ResultVT.isInteger() &&
9549              V.getValueType().isInteger()) {
9550       // If a result value was tied to an input value, the computed result
9551       // may have a wider width than the expected result.  Extract the
9552       // relevant portion.
9553       V = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, V);
9554     }
9555     assert(ResultVT == V.getValueType() && "Asm result value mismatch!");
9556     ResultVTs.push_back(ResultVT);
9557     ResultValues.push_back(V);
9558   };
9559 
9560   // Deal with output operands.
9561   for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9562     if (OpInfo.Type == InlineAsm::isOutput) {
9563       SDValue Val;
9564       // Skip trivial output operands.
9565       if (OpInfo.AssignedRegs.Regs.empty())
9566         continue;
9567 
9568       switch (OpInfo.ConstraintType) {
9569       case TargetLowering::C_Register:
9570       case TargetLowering::C_RegisterClass:
9571         Val = OpInfo.AssignedRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
9572                                                   Chain, &Glue, &Call);
9573         break;
9574       case TargetLowering::C_Immediate:
9575       case TargetLowering::C_Other:
9576         Val = TLI.LowerAsmOutputForConstraint(Chain, Glue, getCurSDLoc(),
9577                                               OpInfo, DAG);
9578         break;
9579       case TargetLowering::C_Memory:
9580         break; // Already handled.
9581       case TargetLowering::C_Address:
9582         break; // Silence warning.
9583       case TargetLowering::C_Unknown:
9584         assert(false && "Unexpected unknown constraint");
9585       }
9586 
9587       // Indirect output manifest as stores. Record output chains.
9588       if (OpInfo.isIndirect) {
9589         const Value *Ptr = OpInfo.CallOperandVal;
9590         assert(Ptr && "Expected value CallOperandVal for indirect asm operand");
9591         SDValue Store = DAG.getStore(Chain, getCurSDLoc(), Val, getValue(Ptr),
9592                                      MachinePointerInfo(Ptr));
9593         OutChains.push_back(Store);
9594       } else {
9595         // generate CopyFromRegs to associated registers.
9596         assert(!Call.getType()->isVoidTy() && "Bad inline asm!");
9597         if (Val.getOpcode() == ISD::MERGE_VALUES) {
9598           for (const SDValue &V : Val->op_values())
9599             handleRegAssign(V);
9600         } else
9601           handleRegAssign(Val);
9602       }
9603     }
9604   }
9605 
9606   // Set results.
9607   if (!ResultValues.empty()) {
9608     assert(CurResultType == ResultTypes.end() &&
9609            "Mismatch in number of ResultTypes");
9610     assert(ResultValues.size() == ResultTypes.size() &&
9611            "Mismatch in number of output operands in asm result");
9612 
9613     SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
9614                             DAG.getVTList(ResultVTs), ResultValues);
9615     setValue(&Call, V);
9616   }
9617 
9618   // Collect store chains.
9619   if (!OutChains.empty())
9620     Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
9621 
9622   if (EmitEHLabels) {
9623     Chain = lowerEndEH(Chain, cast<InvokeInst>(&Call), EHPadBB, BeginLabel);
9624   }
9625 
9626   // Only Update Root if inline assembly has a memory effect.
9627   if (ResultValues.empty() || HasSideEffect || !OutChains.empty() || IsCallBr ||
9628       EmitEHLabels)
9629     DAG.setRoot(Chain);
9630 }
9631 
9632 void SelectionDAGBuilder::emitInlineAsmError(const CallBase &Call,
9633                                              const Twine &Message) {
9634   LLVMContext &Ctx = *DAG.getContext();
9635   Ctx.emitError(&Call, Message);
9636 
9637   // Make sure we leave the DAG in a valid state
9638   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9639   SmallVector<EVT, 1> ValueVTs;
9640   ComputeValueVTs(TLI, DAG.getDataLayout(), Call.getType(), ValueVTs);
9641 
9642   if (ValueVTs.empty())
9643     return;
9644 
9645   SmallVector<SDValue, 1> Ops;
9646   for (unsigned i = 0, e = ValueVTs.size(); i != e; ++i)
9647     Ops.push_back(DAG.getUNDEF(ValueVTs[i]));
9648 
9649   setValue(&Call, DAG.getMergeValues(Ops, getCurSDLoc()));
9650 }
9651 
9652 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
9653   DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
9654                           MVT::Other, getRoot(),
9655                           getValue(I.getArgOperand(0)),
9656                           DAG.getSrcValue(I.getArgOperand(0))));
9657 }
9658 
9659 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
9660   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9661   const DataLayout &DL = DAG.getDataLayout();
9662   SDValue V = DAG.getVAArg(
9663       TLI.getMemValueType(DAG.getDataLayout(), I.getType()), getCurSDLoc(),
9664       getRoot(), getValue(I.getOperand(0)), DAG.getSrcValue(I.getOperand(0)),
9665       DL.getABITypeAlign(I.getType()).value());
9666   DAG.setRoot(V.getValue(1));
9667 
9668   if (I.getType()->isPointerTy())
9669     V = DAG.getPtrExtOrTrunc(
9670         V, getCurSDLoc(), TLI.getValueType(DAG.getDataLayout(), I.getType()));
9671   setValue(&I, V);
9672 }
9673 
9674 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
9675   DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
9676                           MVT::Other, getRoot(),
9677                           getValue(I.getArgOperand(0)),
9678                           DAG.getSrcValue(I.getArgOperand(0))));
9679 }
9680 
9681 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
9682   DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
9683                           MVT::Other, getRoot(),
9684                           getValue(I.getArgOperand(0)),
9685                           getValue(I.getArgOperand(1)),
9686                           DAG.getSrcValue(I.getArgOperand(0)),
9687                           DAG.getSrcValue(I.getArgOperand(1))));
9688 }
9689 
9690 SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
9691                                                     const Instruction &I,
9692                                                     SDValue Op) {
9693   const MDNode *Range = getRangeMetadata(I);
9694   if (!Range)
9695     return Op;
9696 
9697   ConstantRange CR = getConstantRangeFromMetadata(*Range);
9698   if (CR.isFullSet() || CR.isEmptySet() || CR.isUpperWrapped())
9699     return Op;
9700 
9701   APInt Lo = CR.getUnsignedMin();
9702   if (!Lo.isMinValue())
9703     return Op;
9704 
9705   APInt Hi = CR.getUnsignedMax();
9706   unsigned Bits = std::max(Hi.getActiveBits(),
9707                            static_cast<unsigned>(IntegerType::MIN_INT_BITS));
9708 
9709   EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
9710 
9711   SDLoc SL = getCurSDLoc();
9712 
9713   SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
9714                              DAG.getValueType(SmallVT));
9715   unsigned NumVals = Op.getNode()->getNumValues();
9716   if (NumVals == 1)
9717     return ZExt;
9718 
9719   SmallVector<SDValue, 4> Ops;
9720 
9721   Ops.push_back(ZExt);
9722   for (unsigned I = 1; I != NumVals; ++I)
9723     Ops.push_back(Op.getValue(I));
9724 
9725   return DAG.getMergeValues(Ops, SL);
9726 }
9727 
9728 /// Populate a CallLowerinInfo (into \p CLI) based on the properties of
9729 /// the call being lowered.
9730 ///
9731 /// This is a helper for lowering intrinsics that follow a target calling
9732 /// convention or require stack pointer adjustment. Only a subset of the
9733 /// intrinsic's operands need to participate in the calling convention.
9734 void SelectionDAGBuilder::populateCallLoweringInfo(
9735     TargetLowering::CallLoweringInfo &CLI, const CallBase *Call,
9736     unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy,
9737     AttributeSet RetAttrs, bool IsPatchPoint) {
9738   TargetLowering::ArgListTy Args;
9739   Args.reserve(NumArgs);
9740 
9741   // Populate the argument list.
9742   // Attributes for args start at offset 1, after the return attribute.
9743   for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
9744        ArgI != ArgE; ++ArgI) {
9745     const Value *V = Call->getOperand(ArgI);
9746 
9747     assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
9748 
9749     TargetLowering::ArgListEntry Entry;
9750     Entry.Node = getValue(V);
9751     Entry.Ty = V->getType();
9752     Entry.setAttributes(Call, ArgI);
9753     Args.push_back(Entry);
9754   }
9755 
9756   CLI.setDebugLoc(getCurSDLoc())
9757       .setChain(getRoot())
9758       .setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args),
9759                  RetAttrs)
9760       .setDiscardResult(Call->use_empty())
9761       .setIsPatchPoint(IsPatchPoint)
9762       .setIsPreallocated(
9763           Call->countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0);
9764 }
9765 
9766 /// Add a stack map intrinsic call's live variable operands to a stackmap
9767 /// or patchpoint target node's operand list.
9768 ///
9769 /// Constants are converted to TargetConstants purely as an optimization to
9770 /// avoid constant materialization and register allocation.
9771 ///
9772 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
9773 /// generate addess computation nodes, and so FinalizeISel can convert the
9774 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
9775 /// address materialization and register allocation, but may also be required
9776 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
9777 /// alloca in the entry block, then the runtime may assume that the alloca's
9778 /// StackMap location can be read immediately after compilation and that the
9779 /// location is valid at any point during execution (this is similar to the
9780 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
9781 /// only available in a register, then the runtime would need to trap when
9782 /// execution reaches the StackMap in order to read the alloca's location.
9783 static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx,
9784                                 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops,
9785                                 SelectionDAGBuilder &Builder) {
9786   SelectionDAG &DAG = Builder.DAG;
9787   for (unsigned I = StartIdx; I < Call.arg_size(); I++) {
9788     SDValue Op = Builder.getValue(Call.getArgOperand(I));
9789 
9790     // Things on the stack are pointer-typed, meaning that they are already
9791     // legal and can be emitted directly to target nodes.
9792     if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
9793       Ops.push_back(DAG.getTargetFrameIndex(FI->getIndex(), Op.getValueType()));
9794     } else {
9795       // Otherwise emit a target independent node to be legalised.
9796       Ops.push_back(Builder.getValue(Call.getArgOperand(I)));
9797     }
9798   }
9799 }
9800 
9801 /// Lower llvm.experimental.stackmap.
9802 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
9803   // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
9804   //                                  [live variables...])
9805 
9806   assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
9807 
9808   SDValue Chain, InGlue, Callee;
9809   SmallVector<SDValue, 32> Ops;
9810 
9811   SDLoc DL = getCurSDLoc();
9812   Callee = getValue(CI.getCalledOperand());
9813 
9814   // The stackmap intrinsic only records the live variables (the arguments
9815   // passed to it) and emits NOPS (if requested). Unlike the patchpoint
9816   // intrinsic, this won't be lowered to a function call. This means we don't
9817   // have to worry about calling conventions and target specific lowering code.
9818   // Instead we perform the call lowering right here.
9819   //
9820   // chain, flag = CALLSEQ_START(chain, 0, 0)
9821   // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
9822   // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
9823   //
9824   Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL);
9825   InGlue = Chain.getValue(1);
9826 
9827   // Add the STACKMAP operands, starting with DAG house-keeping.
9828   Ops.push_back(Chain);
9829   Ops.push_back(InGlue);
9830 
9831   // Add the <id>, <numShadowBytes> operands.
9832   //
9833   // These do not require legalisation, and can be emitted directly to target
9834   // constant nodes.
9835   SDValue ID = getValue(CI.getArgOperand(0));
9836   assert(ID.getValueType() == MVT::i64);
9837   SDValue IDConst = DAG.getTargetConstant(
9838       cast<ConstantSDNode>(ID)->getZExtValue(), DL, ID.getValueType());
9839   Ops.push_back(IDConst);
9840 
9841   SDValue Shad = getValue(CI.getArgOperand(1));
9842   assert(Shad.getValueType() == MVT::i32);
9843   SDValue ShadConst = DAG.getTargetConstant(
9844       cast<ConstantSDNode>(Shad)->getZExtValue(), DL, Shad.getValueType());
9845   Ops.push_back(ShadConst);
9846 
9847   // Add the live variables.
9848   addStackMapLiveVars(CI, 2, DL, Ops, *this);
9849 
9850   // Create the STACKMAP node.
9851   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9852   Chain = DAG.getNode(ISD::STACKMAP, DL, NodeTys, Ops);
9853   InGlue = Chain.getValue(1);
9854 
9855   Chain = DAG.getCALLSEQ_END(Chain, 0, 0, InGlue, DL);
9856 
9857   // Stackmaps don't generate values, so nothing goes into the NodeMap.
9858 
9859   // Set the root to the target-lowered call chain.
9860   DAG.setRoot(Chain);
9861 
9862   // Inform the Frame Information that we have a stackmap in this function.
9863   FuncInfo.MF->getFrameInfo().setHasStackMap();
9864 }
9865 
9866 /// Lower llvm.experimental.patchpoint directly to its target opcode.
9867 void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB,
9868                                           const BasicBlock *EHPadBB) {
9869   // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
9870   //                                                 i32 <numBytes>,
9871   //                                                 i8* <target>,
9872   //                                                 i32 <numArgs>,
9873   //                                                 [Args...],
9874   //                                                 [live variables...])
9875 
9876   CallingConv::ID CC = CB.getCallingConv();
9877   bool IsAnyRegCC = CC == CallingConv::AnyReg;
9878   bool HasDef = !CB.getType()->isVoidTy();
9879   SDLoc dl = getCurSDLoc();
9880   SDValue Callee = getValue(CB.getArgOperand(PatchPointOpers::TargetPos));
9881 
9882   // Handle immediate and symbolic callees.
9883   if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
9884     Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
9885                                    /*isTarget=*/true);
9886   else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
9887     Callee =  DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
9888                                          SDLoc(SymbolicCallee),
9889                                          SymbolicCallee->getValueType(0));
9890 
9891   // Get the real number of arguments participating in the call <numArgs>
9892   SDValue NArgVal = getValue(CB.getArgOperand(PatchPointOpers::NArgPos));
9893   unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
9894 
9895   // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
9896   // Intrinsics include all meta-operands up to but not including CC.
9897   unsigned NumMetaOpers = PatchPointOpers::CCPos;
9898   assert(CB.arg_size() >= NumMetaOpers + NumArgs &&
9899          "Not enough arguments provided to the patchpoint intrinsic");
9900 
9901   // For AnyRegCC the arguments are lowered later on manually.
9902   unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
9903   Type *ReturnTy =
9904       IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CB.getType();
9905 
9906   TargetLowering::CallLoweringInfo CLI(DAG);
9907   populateCallLoweringInfo(CLI, &CB, NumMetaOpers, NumCallArgs, Callee,
9908                            ReturnTy, CB.getAttributes().getRetAttrs(), true);
9909   std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
9910 
9911   SDNode *CallEnd = Result.second.getNode();
9912   if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
9913     CallEnd = CallEnd->getOperand(0).getNode();
9914 
9915   /// Get a call instruction from the call sequence chain.
9916   /// Tail calls are not allowed.
9917   assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
9918          "Expected a callseq node.");
9919   SDNode *Call = CallEnd->getOperand(0).getNode();
9920   bool HasGlue = Call->getGluedNode();
9921 
9922   // Replace the target specific call node with the patchable intrinsic.
9923   SmallVector<SDValue, 8> Ops;
9924 
9925   // Push the chain.
9926   Ops.push_back(*(Call->op_begin()));
9927 
9928   // Optionally, push the glue (if any).
9929   if (HasGlue)
9930     Ops.push_back(*(Call->op_end() - 1));
9931 
9932   // Push the register mask info.
9933   if (HasGlue)
9934     Ops.push_back(*(Call->op_end() - 2));
9935   else
9936     Ops.push_back(*(Call->op_end() - 1));
9937 
9938   // Add the <id> and <numBytes> constants.
9939   SDValue IDVal = getValue(CB.getArgOperand(PatchPointOpers::IDPos));
9940   Ops.push_back(DAG.getTargetConstant(
9941                   cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
9942   SDValue NBytesVal = getValue(CB.getArgOperand(PatchPointOpers::NBytesPos));
9943   Ops.push_back(DAG.getTargetConstant(
9944                   cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
9945                   MVT::i32));
9946 
9947   // Add the callee.
9948   Ops.push_back(Callee);
9949 
9950   // Adjust <numArgs> to account for any arguments that have been passed on the
9951   // stack instead.
9952   // Call Node: Chain, Target, {Args}, RegMask, [Glue]
9953   unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
9954   NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
9955   Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
9956 
9957   // Add the calling convention
9958   Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
9959 
9960   // Add the arguments we omitted previously. The register allocator should
9961   // place these in any free register.
9962   if (IsAnyRegCC)
9963     for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
9964       Ops.push_back(getValue(CB.getArgOperand(i)));
9965 
9966   // Push the arguments from the call instruction.
9967   SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
9968   Ops.append(Call->op_begin() + 2, e);
9969 
9970   // Push live variables for the stack map.
9971   addStackMapLiveVars(CB, NumMetaOpers + NumArgs, dl, Ops, *this);
9972 
9973   SDVTList NodeTys;
9974   if (IsAnyRegCC && HasDef) {
9975     // Create the return types based on the intrinsic definition
9976     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9977     SmallVector<EVT, 3> ValueVTs;
9978     ComputeValueVTs(TLI, DAG.getDataLayout(), CB.getType(), ValueVTs);
9979     assert(ValueVTs.size() == 1 && "Expected only one return value type.");
9980 
9981     // There is always a chain and a glue type at the end
9982     ValueVTs.push_back(MVT::Other);
9983     ValueVTs.push_back(MVT::Glue);
9984     NodeTys = DAG.getVTList(ValueVTs);
9985   } else
9986     NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9987 
9988   // Replace the target specific call node with a PATCHPOINT node.
9989   SDValue PPV = DAG.getNode(ISD::PATCHPOINT, dl, NodeTys, Ops);
9990 
9991   // Update the NodeMap.
9992   if (HasDef) {
9993     if (IsAnyRegCC)
9994       setValue(&CB, SDValue(PPV.getNode(), 0));
9995     else
9996       setValue(&CB, Result.first);
9997   }
9998 
9999   // Fixup the consumers of the intrinsic. The chain and glue may be used in the
10000   // call sequence. Furthermore the location of the chain and glue can change
10001   // when the AnyReg calling convention is used and the intrinsic returns a
10002   // value.
10003   if (IsAnyRegCC && HasDef) {
10004     SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
10005     SDValue To[] = {PPV.getValue(1), PPV.getValue(2)};
10006     DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
10007   } else
10008     DAG.ReplaceAllUsesWith(Call, PPV.getNode());
10009   DAG.DeleteNode(Call);
10010 
10011   // Inform the Frame Information that we have a patchpoint in this function.
10012   FuncInfo.MF->getFrameInfo().setHasPatchPoint();
10013 }
10014 
10015 void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
10016                                             unsigned Intrinsic) {
10017   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10018   SDValue Op1 = getValue(I.getArgOperand(0));
10019   SDValue Op2;
10020   if (I.arg_size() > 1)
10021     Op2 = getValue(I.getArgOperand(1));
10022   SDLoc dl = getCurSDLoc();
10023   EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
10024   SDValue Res;
10025   SDNodeFlags SDFlags;
10026   if (auto *FPMO = dyn_cast<FPMathOperator>(&I))
10027     SDFlags.copyFMF(*FPMO);
10028 
10029   switch (Intrinsic) {
10030   case Intrinsic::vector_reduce_fadd:
10031     if (SDFlags.hasAllowReassociation())
10032       Res = DAG.getNode(ISD::FADD, dl, VT, Op1,
10033                         DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags),
10034                         SDFlags);
10035     else
10036       Res = DAG.getNode(ISD::VECREDUCE_SEQ_FADD, dl, VT, Op1, Op2, SDFlags);
10037     break;
10038   case Intrinsic::vector_reduce_fmul:
10039     if (SDFlags.hasAllowReassociation())
10040       Res = DAG.getNode(ISD::FMUL, dl, VT, Op1,
10041                         DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2, SDFlags),
10042                         SDFlags);
10043     else
10044       Res = DAG.getNode(ISD::VECREDUCE_SEQ_FMUL, dl, VT, Op1, Op2, SDFlags);
10045     break;
10046   case Intrinsic::vector_reduce_add:
10047     Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1);
10048     break;
10049   case Intrinsic::vector_reduce_mul:
10050     Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1);
10051     break;
10052   case Intrinsic::vector_reduce_and:
10053     Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1);
10054     break;
10055   case Intrinsic::vector_reduce_or:
10056     Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1);
10057     break;
10058   case Intrinsic::vector_reduce_xor:
10059     Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1);
10060     break;
10061   case Intrinsic::vector_reduce_smax:
10062     Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1);
10063     break;
10064   case Intrinsic::vector_reduce_smin:
10065     Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);
10066     break;
10067   case Intrinsic::vector_reduce_umax:
10068     Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1);
10069     break;
10070   case Intrinsic::vector_reduce_umin:
10071     Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);
10072     break;
10073   case Intrinsic::vector_reduce_fmax:
10074     Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags);
10075     break;
10076   case Intrinsic::vector_reduce_fmin:
10077     Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags);
10078     break;
10079   case Intrinsic::vector_reduce_fmaximum:
10080     Res = DAG.getNode(ISD::VECREDUCE_FMAXIMUM, dl, VT, Op1, SDFlags);
10081     break;
10082   case Intrinsic::vector_reduce_fminimum:
10083     Res = DAG.getNode(ISD::VECREDUCE_FMINIMUM, dl, VT, Op1, SDFlags);
10084     break;
10085   default:
10086     llvm_unreachable("Unhandled vector reduce intrinsic");
10087   }
10088   setValue(&I, Res);
10089 }
10090 
10091 /// Returns an AttributeList representing the attributes applied to the return
10092 /// value of the given call.
10093 static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
10094   SmallVector<Attribute::AttrKind, 2> Attrs;
10095   if (CLI.RetSExt)
10096     Attrs.push_back(Attribute::SExt);
10097   if (CLI.RetZExt)
10098     Attrs.push_back(Attribute::ZExt);
10099   if (CLI.IsInReg)
10100     Attrs.push_back(Attribute::InReg);
10101 
10102   return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex,
10103                             Attrs);
10104 }
10105 
10106 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
10107 /// implementation, which just calls LowerCall.
10108 /// FIXME: When all targets are
10109 /// migrated to using LowerCall, this hook should be integrated into SDISel.
10110 std::pair<SDValue, SDValue>
10111 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
10112   // Handle the incoming return values from the call.
10113   CLI.Ins.clear();
10114   Type *OrigRetTy = CLI.RetTy;
10115   SmallVector<EVT, 4> RetTys;
10116   SmallVector<uint64_t, 4> Offsets;
10117   auto &DL = CLI.DAG.getDataLayout();
10118   ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets, 0);
10119 
10120   if (CLI.IsPostTypeLegalization) {
10121     // If we are lowering a libcall after legalization, split the return type.
10122     SmallVector<EVT, 4> OldRetTys;
10123     SmallVector<uint64_t, 4> OldOffsets;
10124     RetTys.swap(OldRetTys);
10125     Offsets.swap(OldOffsets);
10126 
10127     for (size_t i = 0, e = OldRetTys.size(); i != e; ++i) {
10128       EVT RetVT = OldRetTys[i];
10129       uint64_t Offset = OldOffsets[i];
10130       MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT);
10131       unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT);
10132       unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8;
10133       RetTys.append(NumRegs, RegisterVT);
10134       for (unsigned j = 0; j != NumRegs; ++j)
10135         Offsets.push_back(Offset + j * RegisterVTByteSZ);
10136     }
10137   }
10138 
10139   SmallVector<ISD::OutputArg, 4> Outs;
10140   GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
10141 
10142   bool CanLowerReturn =
10143       this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
10144                            CLI.IsVarArg, Outs, CLI.RetTy->getContext());
10145 
10146   SDValue DemoteStackSlot;
10147   int DemoteStackIdx = -100;
10148   if (!CanLowerReturn) {
10149     // FIXME: equivalent assert?
10150     // assert(!CS.hasInAllocaArgument() &&
10151     //        "sret demotion is incompatible with inalloca");
10152     uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
10153     Align Alignment = DL.getPrefTypeAlign(CLI.RetTy);
10154     MachineFunction &MF = CLI.DAG.getMachineFunction();
10155     DemoteStackIdx =
10156         MF.getFrameInfo().CreateStackObject(TySize, Alignment, false);
10157     Type *StackSlotPtrType = PointerType::get(CLI.RetTy,
10158                                               DL.getAllocaAddrSpace());
10159 
10160     DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getFrameIndexTy(DL));
10161     ArgListEntry Entry;
10162     Entry.Node = DemoteStackSlot;
10163     Entry.Ty = StackSlotPtrType;
10164     Entry.IsSExt = false;
10165     Entry.IsZExt = false;
10166     Entry.IsInReg = false;
10167     Entry.IsSRet = true;
10168     Entry.IsNest = false;
10169     Entry.IsByVal = false;
10170     Entry.IsByRef = false;
10171     Entry.IsReturned = false;
10172     Entry.IsSwiftSelf = false;
10173     Entry.IsSwiftAsync = false;
10174     Entry.IsSwiftError = false;
10175     Entry.IsCFGuardTarget = false;
10176     Entry.Alignment = Alignment;
10177     CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
10178     CLI.NumFixedArgs += 1;
10179     CLI.getArgs()[0].IndirectType = CLI.RetTy;
10180     CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
10181 
10182     // sret demotion isn't compatible with tail-calls, since the sret argument
10183     // points into the callers stack frame.
10184     CLI.IsTailCall = false;
10185   } else {
10186     bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
10187         CLI.RetTy, CLI.CallConv, CLI.IsVarArg, DL);
10188     for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
10189       ISD::ArgFlagsTy Flags;
10190       if (NeedsRegBlock) {
10191         Flags.setInConsecutiveRegs();
10192         if (I == RetTys.size() - 1)
10193           Flags.setInConsecutiveRegsLast();
10194       }
10195       EVT VT = RetTys[I];
10196       MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
10197                                                      CLI.CallConv, VT);
10198       unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
10199                                                        CLI.CallConv, VT);
10200       for (unsigned i = 0; i != NumRegs; ++i) {
10201         ISD::InputArg MyFlags;
10202         MyFlags.Flags = Flags;
10203         MyFlags.VT = RegisterVT;
10204         MyFlags.ArgVT = VT;
10205         MyFlags.Used = CLI.IsReturnValueUsed;
10206         if (CLI.RetTy->isPointerTy()) {
10207           MyFlags.Flags.setPointer();
10208           MyFlags.Flags.setPointerAddrSpace(
10209               cast<PointerType>(CLI.RetTy)->getAddressSpace());
10210         }
10211         if (CLI.RetSExt)
10212           MyFlags.Flags.setSExt();
10213         if (CLI.RetZExt)
10214           MyFlags.Flags.setZExt();
10215         if (CLI.IsInReg)
10216           MyFlags.Flags.setInReg();
10217         CLI.Ins.push_back(MyFlags);
10218       }
10219     }
10220   }
10221 
10222   // We push in swifterror return as the last element of CLI.Ins.
10223   ArgListTy &Args = CLI.getArgs();
10224   if (supportSwiftError()) {
10225     for (const ArgListEntry &Arg : Args) {
10226       if (Arg.IsSwiftError) {
10227         ISD::InputArg MyFlags;
10228         MyFlags.VT = getPointerTy(DL);
10229         MyFlags.ArgVT = EVT(getPointerTy(DL));
10230         MyFlags.Flags.setSwiftError();
10231         CLI.Ins.push_back(MyFlags);
10232       }
10233     }
10234   }
10235 
10236   // Handle all of the outgoing arguments.
10237   CLI.Outs.clear();
10238   CLI.OutVals.clear();
10239   for (unsigned i = 0, e = Args.size(); i != e; ++i) {
10240     SmallVector<EVT, 4> ValueVTs;
10241     ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
10242     // FIXME: Split arguments if CLI.IsPostTypeLegalization
10243     Type *FinalType = Args[i].Ty;
10244     if (Args[i].IsByVal)
10245       FinalType = Args[i].IndirectType;
10246     bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
10247         FinalType, CLI.CallConv, CLI.IsVarArg, DL);
10248     for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
10249          ++Value) {
10250       EVT VT = ValueVTs[Value];
10251       Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
10252       SDValue Op = SDValue(Args[i].Node.getNode(),
10253                            Args[i].Node.getResNo() + Value);
10254       ISD::ArgFlagsTy Flags;
10255 
10256       // Certain targets (such as MIPS), may have a different ABI alignment
10257       // for a type depending on the context. Give the target a chance to
10258       // specify the alignment it wants.
10259       const Align OriginalAlignment(getABIAlignmentForCallingConv(ArgTy, DL));
10260       Flags.setOrigAlign(OriginalAlignment);
10261 
10262       if (Args[i].Ty->isPointerTy()) {
10263         Flags.setPointer();
10264         Flags.setPointerAddrSpace(
10265             cast<PointerType>(Args[i].Ty)->getAddressSpace());
10266       }
10267       if (Args[i].IsZExt)
10268         Flags.setZExt();
10269       if (Args[i].IsSExt)
10270         Flags.setSExt();
10271       if (Args[i].IsInReg) {
10272         // If we are using vectorcall calling convention, a structure that is
10273         // passed InReg - is surely an HVA
10274         if (CLI.CallConv == CallingConv::X86_VectorCall &&
10275             isa<StructType>(FinalType)) {
10276           // The first value of a structure is marked
10277           if (0 == Value)
10278             Flags.setHvaStart();
10279           Flags.setHva();
10280         }
10281         // Set InReg Flag
10282         Flags.setInReg();
10283       }
10284       if (Args[i].IsSRet)
10285         Flags.setSRet();
10286       if (Args[i].IsSwiftSelf)
10287         Flags.setSwiftSelf();
10288       if (Args[i].IsSwiftAsync)
10289         Flags.setSwiftAsync();
10290       if (Args[i].IsSwiftError)
10291         Flags.setSwiftError();
10292       if (Args[i].IsCFGuardTarget)
10293         Flags.setCFGuardTarget();
10294       if (Args[i].IsByVal)
10295         Flags.setByVal();
10296       if (Args[i].IsByRef)
10297         Flags.setByRef();
10298       if (Args[i].IsPreallocated) {
10299         Flags.setPreallocated();
10300         // Set the byval flag for CCAssignFn callbacks that don't know about
10301         // preallocated.  This way we can know how many bytes we should've
10302         // allocated and how many bytes a callee cleanup function will pop.  If
10303         // we port preallocated to more targets, we'll have to add custom
10304         // preallocated handling in the various CC lowering callbacks.
10305         Flags.setByVal();
10306       }
10307       if (Args[i].IsInAlloca) {
10308         Flags.setInAlloca();
10309         // Set the byval flag for CCAssignFn callbacks that don't know about
10310         // inalloca.  This way we can know how many bytes we should've allocated
10311         // and how many bytes a callee cleanup function will pop.  If we port
10312         // inalloca to more targets, we'll have to add custom inalloca handling
10313         // in the various CC lowering callbacks.
10314         Flags.setByVal();
10315       }
10316       Align MemAlign;
10317       if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) {
10318         unsigned FrameSize = DL.getTypeAllocSize(Args[i].IndirectType);
10319         Flags.setByValSize(FrameSize);
10320 
10321         // info is not there but there are cases it cannot get right.
10322         if (auto MA = Args[i].Alignment)
10323           MemAlign = *MA;
10324         else
10325           MemAlign = Align(getByValTypeAlignment(Args[i].IndirectType, DL));
10326       } else if (auto MA = Args[i].Alignment) {
10327         MemAlign = *MA;
10328       } else {
10329         MemAlign = OriginalAlignment;
10330       }
10331       Flags.setMemAlign(MemAlign);
10332       if (Args[i].IsNest)
10333         Flags.setNest();
10334       if (NeedsRegBlock)
10335         Flags.setInConsecutiveRegs();
10336 
10337       MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
10338                                                  CLI.CallConv, VT);
10339       unsigned NumParts = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
10340                                                         CLI.CallConv, VT);
10341       SmallVector<SDValue, 4> Parts(NumParts);
10342       ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
10343 
10344       if (Args[i].IsSExt)
10345         ExtendKind = ISD::SIGN_EXTEND;
10346       else if (Args[i].IsZExt)
10347         ExtendKind = ISD::ZERO_EXTEND;
10348 
10349       // Conservatively only handle 'returned' on non-vectors that can be lowered,
10350       // for now.
10351       if (Args[i].IsReturned && !Op.getValueType().isVector() &&
10352           CanLowerReturn) {
10353         assert((CLI.RetTy == Args[i].Ty ||
10354                 (CLI.RetTy->isPointerTy() && Args[i].Ty->isPointerTy() &&
10355                  CLI.RetTy->getPointerAddressSpace() ==
10356                      Args[i].Ty->getPointerAddressSpace())) &&
10357                RetTys.size() == NumValues && "unexpected use of 'returned'");
10358         // Before passing 'returned' to the target lowering code, ensure that
10359         // either the register MVT and the actual EVT are the same size or that
10360         // the return value and argument are extended in the same way; in these
10361         // cases it's safe to pass the argument register value unchanged as the
10362         // return register value (although it's at the target's option whether
10363         // to do so)
10364         // TODO: allow code generation to take advantage of partially preserved
10365         // registers rather than clobbering the entire register when the
10366         // parameter extension method is not compatible with the return
10367         // extension method
10368         if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
10369             (ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt &&
10370              CLI.RetZExt == Args[i].IsZExt))
10371           Flags.setReturned();
10372       }
10373 
10374       getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT, CLI.CB,
10375                      CLI.CallConv, ExtendKind);
10376 
10377       for (unsigned j = 0; j != NumParts; ++j) {
10378         // if it isn't first piece, alignment must be 1
10379         // For scalable vectors the scalable part is currently handled
10380         // by individual targets, so we just use the known minimum size here.
10381         ISD::OutputArg MyFlags(
10382             Flags, Parts[j].getValueType().getSimpleVT(), VT,
10383             i < CLI.NumFixedArgs, i,
10384             j * Parts[j].getValueType().getStoreSize().getKnownMinValue());
10385         if (NumParts > 1 && j == 0)
10386           MyFlags.Flags.setSplit();
10387         else if (j != 0) {
10388           MyFlags.Flags.setOrigAlign(Align(1));
10389           if (j == NumParts - 1)
10390             MyFlags.Flags.setSplitEnd();
10391         }
10392 
10393         CLI.Outs.push_back(MyFlags);
10394         CLI.OutVals.push_back(Parts[j]);
10395       }
10396 
10397       if (NeedsRegBlock && Value == NumValues - 1)
10398         CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
10399     }
10400   }
10401 
10402   SmallVector<SDValue, 4> InVals;
10403   CLI.Chain = LowerCall(CLI, InVals);
10404 
10405   // Update CLI.InVals to use outside of this function.
10406   CLI.InVals = InVals;
10407 
10408   // Verify that the target's LowerCall behaved as expected.
10409   assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
10410          "LowerCall didn't return a valid chain!");
10411   assert((!CLI.IsTailCall || InVals.empty()) &&
10412          "LowerCall emitted a return value for a tail call!");
10413   assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
10414          "LowerCall didn't emit the correct number of values!");
10415 
10416   // For a tail call, the return value is merely live-out and there aren't
10417   // any nodes in the DAG representing it. Return a special value to
10418   // indicate that a tail call has been emitted and no more Instructions
10419   // should be processed in the current block.
10420   if (CLI.IsTailCall) {
10421     CLI.DAG.setRoot(CLI.Chain);
10422     return std::make_pair(SDValue(), SDValue());
10423   }
10424 
10425 #ifndef NDEBUG
10426   for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
10427     assert(InVals[i].getNode() && "LowerCall emitted a null value!");
10428     assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
10429            "LowerCall emitted a value with the wrong type!");
10430   }
10431 #endif
10432 
10433   SmallVector<SDValue, 4> ReturnValues;
10434   if (!CanLowerReturn) {
10435     // The instruction result is the result of loading from the
10436     // hidden sret parameter.
10437     SmallVector<EVT, 1> PVTs;
10438     Type *PtrRetTy =
10439         PointerType::get(OrigRetTy->getContext(), DL.getAllocaAddrSpace());
10440 
10441     ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
10442     assert(PVTs.size() == 1 && "Pointers should fit in one register");
10443     EVT PtrVT = PVTs[0];
10444 
10445     unsigned NumValues = RetTys.size();
10446     ReturnValues.resize(NumValues);
10447     SmallVector<SDValue, 4> Chains(NumValues);
10448 
10449     // An aggregate return value cannot wrap around the address space, so
10450     // offsets to its parts don't wrap either.
10451     SDNodeFlags Flags;
10452     Flags.setNoUnsignedWrap(true);
10453 
10454     MachineFunction &MF = CLI.DAG.getMachineFunction();
10455     Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx);
10456     for (unsigned i = 0; i < NumValues; ++i) {
10457       SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
10458                                     CLI.DAG.getConstant(Offsets[i], CLI.DL,
10459                                                         PtrVT), Flags);
10460       SDValue L = CLI.DAG.getLoad(
10461           RetTys[i], CLI.DL, CLI.Chain, Add,
10462           MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
10463                                             DemoteStackIdx, Offsets[i]),
10464           HiddenSRetAlign);
10465       ReturnValues[i] = L;
10466       Chains[i] = L.getValue(1);
10467     }
10468 
10469     CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
10470   } else {
10471     // Collect the legal value parts into potentially illegal values
10472     // that correspond to the original function's return values.
10473     std::optional<ISD::NodeType> AssertOp;
10474     if (CLI.RetSExt)
10475       AssertOp = ISD::AssertSext;
10476     else if (CLI.RetZExt)
10477       AssertOp = ISD::AssertZext;
10478     unsigned CurReg = 0;
10479     for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
10480       EVT VT = RetTys[I];
10481       MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
10482                                                      CLI.CallConv, VT);
10483       unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
10484                                                        CLI.CallConv, VT);
10485 
10486       ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
10487                                               NumRegs, RegisterVT, VT, nullptr,
10488                                               CLI.CallConv, AssertOp));
10489       CurReg += NumRegs;
10490     }
10491 
10492     // For a function returning void, there is no return value. We can't create
10493     // such a node, so we just return a null return value in that case. In
10494     // that case, nothing will actually look at the value.
10495     if (ReturnValues.empty())
10496       return std::make_pair(SDValue(), CLI.Chain);
10497   }
10498 
10499   SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
10500                                 CLI.DAG.getVTList(RetTys), ReturnValues);
10501   return std::make_pair(Res, CLI.Chain);
10502 }
10503 
10504 /// Places new result values for the node in Results (their number
10505 /// and types must exactly match those of the original return values of
10506 /// the node), or leaves Results empty, which indicates that the node is not
10507 /// to be custom lowered after all.
10508 void TargetLowering::LowerOperationWrapper(SDNode *N,
10509                                            SmallVectorImpl<SDValue> &Results,
10510                                            SelectionDAG &DAG) const {
10511   SDValue Res = LowerOperation(SDValue(N, 0), DAG);
10512 
10513   if (!Res.getNode())
10514     return;
10515 
10516   // If the original node has one result, take the return value from
10517   // LowerOperation as is. It might not be result number 0.
10518   if (N->getNumValues() == 1) {
10519     Results.push_back(Res);
10520     return;
10521   }
10522 
10523   // If the original node has multiple results, then the return node should
10524   // have the same number of results.
10525   assert((N->getNumValues() == Res->getNumValues()) &&
10526       "Lowering returned the wrong number of results!");
10527 
10528   // Places new result values base on N result number.
10529   for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
10530     Results.push_back(Res.getValue(I));
10531 }
10532 
10533 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10534   llvm_unreachable("LowerOperation not implemented for this target!");
10535 }
10536 
10537 void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V,
10538                                                      unsigned Reg,
10539                                                      ISD::NodeType ExtendType) {
10540   SDValue Op = getNonRegisterValue(V);
10541   assert((Op.getOpcode() != ISD::CopyFromReg ||
10542           cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
10543          "Copy from a reg to the same reg!");
10544   assert(!Register::isPhysicalRegister(Reg) && "Is a physreg");
10545 
10546   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10547   // If this is an InlineAsm we have to match the registers required, not the
10548   // notional registers required by the type.
10549 
10550   RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(),
10551                    std::nullopt); // This is not an ABI copy.
10552   SDValue Chain = DAG.getEntryNode();
10553 
10554   if (ExtendType == ISD::ANY_EXTEND) {
10555     auto PreferredExtendIt = FuncInfo.PreferredExtendType.find(V);
10556     if (PreferredExtendIt != FuncInfo.PreferredExtendType.end())
10557       ExtendType = PreferredExtendIt->second;
10558   }
10559   RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
10560   PendingExports.push_back(Chain);
10561 }
10562 
10563 #include "llvm/CodeGen/SelectionDAGISel.h"
10564 
10565 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
10566 /// entry block, return true.  This includes arguments used by switches, since
10567 /// the switch may expand into multiple basic blocks.
10568 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
10569   // With FastISel active, we may be splitting blocks, so force creation
10570   // of virtual registers for all non-dead arguments.
10571   if (FastISel)
10572     return A->use_empty();
10573 
10574   const BasicBlock &Entry = A->getParent()->front();
10575   for (const User *U : A->users())
10576     if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
10577       return false;  // Use not in entry block.
10578 
10579   return true;
10580 }
10581 
10582 using ArgCopyElisionMapTy =
10583     DenseMap<const Argument *,
10584              std::pair<const AllocaInst *, const StoreInst *>>;
10585 
10586 /// Scan the entry block of the function in FuncInfo for arguments that look
10587 /// like copies into a local alloca. Record any copied arguments in
10588 /// ArgCopyElisionCandidates.
10589 static void
10590 findArgumentCopyElisionCandidates(const DataLayout &DL,
10591                                   FunctionLoweringInfo *FuncInfo,
10592                                   ArgCopyElisionMapTy &ArgCopyElisionCandidates) {
10593   // Record the state of every static alloca used in the entry block. Argument
10594   // allocas are all used in the entry block, so we need approximately as many
10595   // entries as we have arguments.
10596   enum StaticAllocaInfo { Unknown, Clobbered, Elidable };
10597   SmallDenseMap<const AllocaInst *, StaticAllocaInfo, 8> StaticAllocas;
10598   unsigned NumArgs = FuncInfo->Fn->arg_size();
10599   StaticAllocas.reserve(NumArgs * 2);
10600 
10601   auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * {
10602     if (!V)
10603       return nullptr;
10604     V = V->stripPointerCasts();
10605     const auto *AI = dyn_cast<AllocaInst>(V);
10606     if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(AI))
10607       return nullptr;
10608     auto Iter = StaticAllocas.insert({AI, Unknown});
10609     return &Iter.first->second;
10610   };
10611 
10612   // Look for stores of arguments to static allocas. Look through bitcasts and
10613   // GEPs to handle type coercions, as long as the alloca is fully initialized
10614   // by the store. Any non-store use of an alloca escapes it and any subsequent
10615   // unanalyzed store might write it.
10616   // FIXME: Handle structs initialized with multiple stores.
10617   for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) {
10618     // Look for stores, and handle non-store uses conservatively.
10619     const auto *SI = dyn_cast<StoreInst>(&I);
10620     if (!SI) {
10621       // We will look through cast uses, so ignore them completely.
10622       if (I.isCast())
10623         continue;
10624       // Ignore debug info and pseudo op intrinsics, they don't escape or store
10625       // to allocas.
10626       if (I.isDebugOrPseudoInst())
10627         continue;
10628       // This is an unknown instruction. Assume it escapes or writes to all
10629       // static alloca operands.
10630       for (const Use &U : I.operands()) {
10631         if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U))
10632           *Info = StaticAllocaInfo::Clobbered;
10633       }
10634       continue;
10635     }
10636 
10637     // If the stored value is a static alloca, mark it as escaped.
10638     if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
10639       *Info = StaticAllocaInfo::Clobbered;
10640 
10641     // Check if the destination is a static alloca.
10642     const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
10643     StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst);
10644     if (!Info)
10645       continue;
10646     const AllocaInst *AI = cast<AllocaInst>(Dst);
10647 
10648     // Skip allocas that have been initialized or clobbered.
10649     if (*Info != StaticAllocaInfo::Unknown)
10650       continue;
10651 
10652     // Check if the stored value is an argument, and that this store fully
10653     // initializes the alloca.
10654     // If the argument type has padding bits we can't directly forward a pointer
10655     // as the upper bits may contain garbage.
10656     // Don't elide copies from the same argument twice.
10657     const Value *Val = SI->getValueOperand()->stripPointerCasts();
10658     const auto *Arg = dyn_cast<Argument>(Val);
10659     if (!Arg || Arg->hasPassPointeeByValueCopyAttr() ||
10660         Arg->getType()->isEmptyTy() ||
10661         DL.getTypeStoreSize(Arg->getType()) !=
10662             DL.getTypeAllocSize(AI->getAllocatedType()) ||
10663         !DL.typeSizeEqualsStoreSize(Arg->getType()) ||
10664         ArgCopyElisionCandidates.count(Arg)) {
10665       *Info = StaticAllocaInfo::Clobbered;
10666       continue;
10667     }
10668 
10669     LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI
10670                       << '\n');
10671 
10672     // Mark this alloca and store for argument copy elision.
10673     *Info = StaticAllocaInfo::Elidable;
10674     ArgCopyElisionCandidates.insert({Arg, {AI, SI}});
10675 
10676     // Stop scanning if we've seen all arguments. This will happen early in -O0
10677     // builds, which is useful, because -O0 builds have large entry blocks and
10678     // many allocas.
10679     if (ArgCopyElisionCandidates.size() == NumArgs)
10680       break;
10681   }
10682 }
10683 
10684 /// Try to elide argument copies from memory into a local alloca. Succeeds if
10685 /// ArgVal is a load from a suitable fixed stack object.
10686 static void tryToElideArgumentCopy(
10687     FunctionLoweringInfo &FuncInfo, SmallVectorImpl<SDValue> &Chains,
10688     DenseMap<int, int> &ArgCopyElisionFrameIndexMap,
10689     SmallPtrSetImpl<const Instruction *> &ElidedArgCopyInstrs,
10690     ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg,
10691     ArrayRef<SDValue> ArgVals, bool &ArgHasUses) {
10692   // Check if this is a load from a fixed stack object.
10693   auto *LNode = dyn_cast<LoadSDNode>(ArgVals[0]);
10694   if (!LNode)
10695     return;
10696   auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode());
10697   if (!FINode)
10698     return;
10699 
10700   // Check that the fixed stack object is the right size and alignment.
10701   // Look at the alignment that the user wrote on the alloca instead of looking
10702   // at the stack object.
10703   auto ArgCopyIter = ArgCopyElisionCandidates.find(&Arg);
10704   assert(ArgCopyIter != ArgCopyElisionCandidates.end());
10705   const AllocaInst *AI = ArgCopyIter->second.first;
10706   int FixedIndex = FINode->getIndex();
10707   int &AllocaIndex = FuncInfo.StaticAllocaMap[AI];
10708   int OldIndex = AllocaIndex;
10709   MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
10710   if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) {
10711     LLVM_DEBUG(
10712         dbgs() << "  argument copy elision failed due to bad fixed stack "
10713                   "object size\n");
10714     return;
10715   }
10716   Align RequiredAlignment = AI->getAlign();
10717   if (MFI.getObjectAlign(FixedIndex) < RequiredAlignment) {
10718     LLVM_DEBUG(dbgs() << "  argument copy elision failed: alignment of alloca "
10719                          "greater than stack argument alignment ("
10720                       << DebugStr(RequiredAlignment) << " vs "
10721                       << DebugStr(MFI.getObjectAlign(FixedIndex)) << ")\n");
10722     return;
10723   }
10724 
10725   // Perform the elision. Delete the old stack object and replace its only use
10726   // in the variable info map. Mark the stack object as mutable.
10727   LLVM_DEBUG({
10728     dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n'
10729            << "  Replacing frame index " << OldIndex << " with " << FixedIndex
10730            << '\n';
10731   });
10732   MFI.RemoveStackObject(OldIndex);
10733   MFI.setIsImmutableObjectIndex(FixedIndex, false);
10734   AllocaIndex = FixedIndex;
10735   ArgCopyElisionFrameIndexMap.insert({OldIndex, FixedIndex});
10736   for (SDValue ArgVal : ArgVals)
10737     Chains.push_back(ArgVal.getValue(1));
10738 
10739   // Avoid emitting code for the store implementing the copy.
10740   const StoreInst *SI = ArgCopyIter->second.second;
10741   ElidedArgCopyInstrs.insert(SI);
10742 
10743   // Check for uses of the argument again so that we can avoid exporting ArgVal
10744   // if it is't used by anything other than the store.
10745   for (const Value *U : Arg.users()) {
10746     if (U != SI) {
10747       ArgHasUses = true;
10748       break;
10749     }
10750   }
10751 }
10752 
10753 void SelectionDAGISel::LowerArguments(const Function &F) {
10754   SelectionDAG &DAG = SDB->DAG;
10755   SDLoc dl = SDB->getCurSDLoc();
10756   const DataLayout &DL = DAG.getDataLayout();
10757   SmallVector<ISD::InputArg, 16> Ins;
10758 
10759   // In Naked functions we aren't going to save any registers.
10760   if (F.hasFnAttribute(Attribute::Naked))
10761     return;
10762 
10763   if (!FuncInfo->CanLowerReturn) {
10764     // Put in an sret pointer parameter before all the other parameters.
10765     SmallVector<EVT, 1> ValueVTs;
10766     ComputeValueVTs(*TLI, DAG.getDataLayout(),
10767                     PointerType::get(F.getContext(),
10768                                      DAG.getDataLayout().getAllocaAddrSpace()),
10769                     ValueVTs);
10770 
10771     // NOTE: Assuming that a pointer will never break down to more than one VT
10772     // or one register.
10773     ISD::ArgFlagsTy Flags;
10774     Flags.setSRet();
10775     MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
10776     ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
10777                          ISD::InputArg::NoArgIndex, 0);
10778     Ins.push_back(RetArg);
10779   }
10780 
10781   // Look for stores of arguments to static allocas. Mark such arguments with a
10782   // flag to ask the target to give us the memory location of that argument if
10783   // available.
10784   ArgCopyElisionMapTy ArgCopyElisionCandidates;
10785   findArgumentCopyElisionCandidates(DL, FuncInfo.get(),
10786                                     ArgCopyElisionCandidates);
10787 
10788   // Set up the incoming argument description vector.
10789   for (const Argument &Arg : F.args()) {
10790     unsigned ArgNo = Arg.getArgNo();
10791     SmallVector<EVT, 4> ValueVTs;
10792     ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs);
10793     bool isArgValueUsed = !Arg.use_empty();
10794     unsigned PartBase = 0;
10795     Type *FinalType = Arg.getType();
10796     if (Arg.hasAttribute(Attribute::ByVal))
10797       FinalType = Arg.getParamByValType();
10798     bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
10799         FinalType, F.getCallingConv(), F.isVarArg(), DL);
10800     for (unsigned Value = 0, NumValues = ValueVTs.size();
10801          Value != NumValues; ++Value) {
10802       EVT VT = ValueVTs[Value];
10803       Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
10804       ISD::ArgFlagsTy Flags;
10805 
10806 
10807       if (Arg.getType()->isPointerTy()) {
10808         Flags.setPointer();
10809         Flags.setPointerAddrSpace(
10810             cast<PointerType>(Arg.getType())->getAddressSpace());
10811       }
10812       if (Arg.hasAttribute(Attribute::ZExt))
10813         Flags.setZExt();
10814       if (Arg.hasAttribute(Attribute::SExt))
10815         Flags.setSExt();
10816       if (Arg.hasAttribute(Attribute::InReg)) {
10817         // If we are using vectorcall calling convention, a structure that is
10818         // passed InReg - is surely an HVA
10819         if (F.getCallingConv() == CallingConv::X86_VectorCall &&
10820             isa<StructType>(Arg.getType())) {
10821           // The first value of a structure is marked
10822           if (0 == Value)
10823             Flags.setHvaStart();
10824           Flags.setHva();
10825         }
10826         // Set InReg Flag
10827         Flags.setInReg();
10828       }
10829       if (Arg.hasAttribute(Attribute::StructRet))
10830         Flags.setSRet();
10831       if (Arg.hasAttribute(Attribute::SwiftSelf))
10832         Flags.setSwiftSelf();
10833       if (Arg.hasAttribute(Attribute::SwiftAsync))
10834         Flags.setSwiftAsync();
10835       if (Arg.hasAttribute(Attribute::SwiftError))
10836         Flags.setSwiftError();
10837       if (Arg.hasAttribute(Attribute::ByVal))
10838         Flags.setByVal();
10839       if (Arg.hasAttribute(Attribute::ByRef))
10840         Flags.setByRef();
10841       if (Arg.hasAttribute(Attribute::InAlloca)) {
10842         Flags.setInAlloca();
10843         // Set the byval flag for CCAssignFn callbacks that don't know about
10844         // inalloca.  This way we can know how many bytes we should've allocated
10845         // and how many bytes a callee cleanup function will pop.  If we port
10846         // inalloca to more targets, we'll have to add custom inalloca handling
10847         // in the various CC lowering callbacks.
10848         Flags.setByVal();
10849       }
10850       if (Arg.hasAttribute(Attribute::Preallocated)) {
10851         Flags.setPreallocated();
10852         // Set the byval flag for CCAssignFn callbacks that don't know about
10853         // preallocated.  This way we can know how many bytes we should've
10854         // allocated and how many bytes a callee cleanup function will pop.  If
10855         // we port preallocated to more targets, we'll have to add custom
10856         // preallocated handling in the various CC lowering callbacks.
10857         Flags.setByVal();
10858       }
10859 
10860       // Certain targets (such as MIPS), may have a different ABI alignment
10861       // for a type depending on the context. Give the target a chance to
10862       // specify the alignment it wants.
10863       const Align OriginalAlignment(
10864           TLI->getABIAlignmentForCallingConv(ArgTy, DL));
10865       Flags.setOrigAlign(OriginalAlignment);
10866 
10867       Align MemAlign;
10868       Type *ArgMemTy = nullptr;
10869       if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() ||
10870           Flags.isByRef()) {
10871         if (!ArgMemTy)
10872           ArgMemTy = Arg.getPointeeInMemoryValueType();
10873 
10874         uint64_t MemSize = DL.getTypeAllocSize(ArgMemTy);
10875 
10876         // For in-memory arguments, size and alignment should be passed from FE.
10877         // BE will guess if this info is not there but there are cases it cannot
10878         // get right.
10879         if (auto ParamAlign = Arg.getParamStackAlign())
10880           MemAlign = *ParamAlign;
10881         else if ((ParamAlign = Arg.getParamAlign()))
10882           MemAlign = *ParamAlign;
10883         else
10884           MemAlign = Align(TLI->getByValTypeAlignment(ArgMemTy, DL));
10885         if (Flags.isByRef())
10886           Flags.setByRefSize(MemSize);
10887         else
10888           Flags.setByValSize(MemSize);
10889       } else if (auto ParamAlign = Arg.getParamStackAlign()) {
10890         MemAlign = *ParamAlign;
10891       } else {
10892         MemAlign = OriginalAlignment;
10893       }
10894       Flags.setMemAlign(MemAlign);
10895 
10896       if (Arg.hasAttribute(Attribute::Nest))
10897         Flags.setNest();
10898       if (NeedsRegBlock)
10899         Flags.setInConsecutiveRegs();
10900       if (ArgCopyElisionCandidates.count(&Arg))
10901         Flags.setCopyElisionCandidate();
10902       if (Arg.hasAttribute(Attribute::Returned))
10903         Flags.setReturned();
10904 
10905       MVT RegisterVT = TLI->getRegisterTypeForCallingConv(
10906           *CurDAG->getContext(), F.getCallingConv(), VT);
10907       unsigned NumRegs = TLI->getNumRegistersForCallingConv(
10908           *CurDAG->getContext(), F.getCallingConv(), VT);
10909       for (unsigned i = 0; i != NumRegs; ++i) {
10910         // For scalable vectors, use the minimum size; individual targets
10911         // are responsible for handling scalable vector arguments and
10912         // return values.
10913         ISD::InputArg MyFlags(
10914             Flags, RegisterVT, VT, isArgValueUsed, ArgNo,
10915             PartBase + i * RegisterVT.getStoreSize().getKnownMinValue());
10916         if (NumRegs > 1 && i == 0)
10917           MyFlags.Flags.setSplit();
10918         // if it isn't first piece, alignment must be 1
10919         else if (i > 0) {
10920           MyFlags.Flags.setOrigAlign(Align(1));
10921           if (i == NumRegs - 1)
10922             MyFlags.Flags.setSplitEnd();
10923         }
10924         Ins.push_back(MyFlags);
10925       }
10926       if (NeedsRegBlock && Value == NumValues - 1)
10927         Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
10928       PartBase += VT.getStoreSize().getKnownMinValue();
10929     }
10930   }
10931 
10932   // Call the target to set up the argument values.
10933   SmallVector<SDValue, 8> InVals;
10934   SDValue NewRoot = TLI->LowerFormalArguments(
10935       DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
10936 
10937   // Verify that the target's LowerFormalArguments behaved as expected.
10938   assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
10939          "LowerFormalArguments didn't return a valid chain!");
10940   assert(InVals.size() == Ins.size() &&
10941          "LowerFormalArguments didn't emit the correct number of values!");
10942   LLVM_DEBUG({
10943     for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
10944       assert(InVals[i].getNode() &&
10945              "LowerFormalArguments emitted a null value!");
10946       assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
10947              "LowerFormalArguments emitted a value with the wrong type!");
10948     }
10949   });
10950 
10951   // Update the DAG with the new chain value resulting from argument lowering.
10952   DAG.setRoot(NewRoot);
10953 
10954   // Set up the argument values.
10955   unsigned i = 0;
10956   if (!FuncInfo->CanLowerReturn) {
10957     // Create a virtual register for the sret pointer, and put in a copy
10958     // from the sret argument into it.
10959     SmallVector<EVT, 1> ValueVTs;
10960     ComputeValueVTs(*TLI, DAG.getDataLayout(),
10961                     PointerType::get(F.getContext(),
10962                                      DAG.getDataLayout().getAllocaAddrSpace()),
10963                     ValueVTs);
10964     MVT VT = ValueVTs[0].getSimpleVT();
10965     MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
10966     std::optional<ISD::NodeType> AssertOp;
10967     SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT,
10968                                         nullptr, F.getCallingConv(), AssertOp);
10969 
10970     MachineFunction& MF = SDB->DAG.getMachineFunction();
10971     MachineRegisterInfo& RegInfo = MF.getRegInfo();
10972     Register SRetReg =
10973         RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
10974     FuncInfo->DemoteRegister = SRetReg;
10975     NewRoot =
10976         SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
10977     DAG.setRoot(NewRoot);
10978 
10979     // i indexes lowered arguments.  Bump it past the hidden sret argument.
10980     ++i;
10981   }
10982 
10983   SmallVector<SDValue, 4> Chains;
10984   DenseMap<int, int> ArgCopyElisionFrameIndexMap;
10985   for (const Argument &Arg : F.args()) {
10986     SmallVector<SDValue, 4> ArgValues;
10987     SmallVector<EVT, 4> ValueVTs;
10988     ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs);
10989     unsigned NumValues = ValueVTs.size();
10990     if (NumValues == 0)
10991       continue;
10992 
10993     bool ArgHasUses = !Arg.use_empty();
10994 
10995     // Elide the copying store if the target loaded this argument from a
10996     // suitable fixed stack object.
10997     if (Ins[i].Flags.isCopyElisionCandidate()) {
10998       unsigned NumParts = 0;
10999       for (EVT VT : ValueVTs)
11000         NumParts += TLI->getNumRegistersForCallingConv(*CurDAG->getContext(),
11001                                                        F.getCallingConv(), VT);
11002 
11003       tryToElideArgumentCopy(*FuncInfo, Chains, ArgCopyElisionFrameIndexMap,
11004                              ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg,
11005                              ArrayRef(&InVals[i], NumParts), ArgHasUses);
11006     }
11007 
11008     // If this argument is unused then remember its value. It is used to generate
11009     // debugging information.
11010     bool isSwiftErrorArg =
11011         TLI->supportSwiftError() &&
11012         Arg.hasAttribute(Attribute::SwiftError);
11013     if (!ArgHasUses && !isSwiftErrorArg) {
11014       SDB->setUnusedArgValue(&Arg, InVals[i]);
11015 
11016       // Also remember any frame index for use in FastISel.
11017       if (FrameIndexSDNode *FI =
11018           dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
11019         FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11020     }
11021 
11022     for (unsigned Val = 0; Val != NumValues; ++Val) {
11023       EVT VT = ValueVTs[Val];
11024       MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(),
11025                                                       F.getCallingConv(), VT);
11026       unsigned NumParts = TLI->getNumRegistersForCallingConv(
11027           *CurDAG->getContext(), F.getCallingConv(), VT);
11028 
11029       // Even an apparent 'unused' swifterror argument needs to be returned. So
11030       // we do generate a copy for it that can be used on return from the
11031       // function.
11032       if (ArgHasUses || isSwiftErrorArg) {
11033         std::optional<ISD::NodeType> AssertOp;
11034         if (Arg.hasAttribute(Attribute::SExt))
11035           AssertOp = ISD::AssertSext;
11036         else if (Arg.hasAttribute(Attribute::ZExt))
11037           AssertOp = ISD::AssertZext;
11038 
11039         ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
11040                                              PartVT, VT, nullptr,
11041                                              F.getCallingConv(), AssertOp));
11042       }
11043 
11044       i += NumParts;
11045     }
11046 
11047     // We don't need to do anything else for unused arguments.
11048     if (ArgValues.empty())
11049       continue;
11050 
11051     // Note down frame index.
11052     if (FrameIndexSDNode *FI =
11053         dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
11054       FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11055 
11056     SDValue Res = DAG.getMergeValues(ArrayRef(ArgValues.data(), NumValues),
11057                                      SDB->getCurSDLoc());
11058 
11059     SDB->setValue(&Arg, Res);
11060     if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
11061       // We want to associate the argument with the frame index, among
11062       // involved operands, that correspond to the lowest address. The
11063       // getCopyFromParts function, called earlier, is swapping the order of
11064       // the operands to BUILD_PAIR depending on endianness. The result of
11065       // that swapping is that the least significant bits of the argument will
11066       // be in the first operand of the BUILD_PAIR node, and the most
11067       // significant bits will be in the second operand.
11068       unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0;
11069       if (LoadSDNode *LNode =
11070           dyn_cast<LoadSDNode>(Res.getOperand(LowAddressOp).getNode()))
11071         if (FrameIndexSDNode *FI =
11072             dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
11073           FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11074     }
11075 
11076     // Analyses past this point are naive and don't expect an assertion.
11077     if (Res.getOpcode() == ISD::AssertZext)
11078       Res = Res.getOperand(0);
11079 
11080     // Update the SwiftErrorVRegDefMap.
11081     if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
11082       unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
11083       if (Register::isVirtualRegister(Reg))
11084         SwiftError->setCurrentVReg(FuncInfo->MBB, SwiftError->getFunctionArg(),
11085                                    Reg);
11086     }
11087 
11088     // If this argument is live outside of the entry block, insert a copy from
11089     // wherever we got it to the vreg that other BB's will reference it as.
11090     if (Res.getOpcode() == ISD::CopyFromReg) {
11091       // If we can, though, try to skip creating an unnecessary vreg.
11092       // FIXME: This isn't very clean... it would be nice to make this more
11093       // general.
11094       unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
11095       if (Register::isVirtualRegister(Reg)) {
11096         FuncInfo->ValueMap[&Arg] = Reg;
11097         continue;
11098       }
11099     }
11100     if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) {
11101       FuncInfo->InitializeRegForValue(&Arg);
11102       SDB->CopyToExportRegsIfNeeded(&Arg);
11103     }
11104   }
11105 
11106   if (!Chains.empty()) {
11107     Chains.push_back(NewRoot);
11108     NewRoot = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
11109   }
11110 
11111   DAG.setRoot(NewRoot);
11112 
11113   assert(i == InVals.size() && "Argument register count mismatch!");
11114 
11115   // If any argument copy elisions occurred and we have debug info, update the
11116   // stale frame indices used in the dbg.declare variable info table.
11117   if (!ArgCopyElisionFrameIndexMap.empty()) {
11118     for (MachineFunction::VariableDbgInfo &VI :
11119          MF->getInStackSlotVariableDbgInfo()) {
11120       auto I = ArgCopyElisionFrameIndexMap.find(VI.getStackSlot());
11121       if (I != ArgCopyElisionFrameIndexMap.end())
11122         VI.updateStackSlot(I->second);
11123     }
11124   }
11125 
11126   // Finally, if the target has anything special to do, allow it to do so.
11127   emitFunctionEntryCode();
11128 }
11129 
11130 /// Handle PHI nodes in successor blocks.  Emit code into the SelectionDAG to
11131 /// ensure constants are generated when needed.  Remember the virtual registers
11132 /// that need to be added to the Machine PHI nodes as input.  We cannot just
11133 /// directly add them, because expansion might result in multiple MBB's for one
11134 /// BB.  As such, the start of the BB might correspond to a different MBB than
11135 /// the end.
11136 void
11137 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
11138   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11139 
11140   SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
11141 
11142   // Check PHI nodes in successors that expect a value to be available from this
11143   // block.
11144   for (const BasicBlock *SuccBB : successors(LLVMBB->getTerminator())) {
11145     if (!isa<PHINode>(SuccBB->begin())) continue;
11146     MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
11147 
11148     // If this terminator has multiple identical successors (common for
11149     // switches), only handle each succ once.
11150     if (!SuccsHandled.insert(SuccMBB).second)
11151       continue;
11152 
11153     MachineBasicBlock::iterator MBBI = SuccMBB->begin();
11154 
11155     // At this point we know that there is a 1-1 correspondence between LLVM PHI
11156     // nodes and Machine PHI nodes, but the incoming operands have not been
11157     // emitted yet.
11158     for (const PHINode &PN : SuccBB->phis()) {
11159       // Ignore dead phi's.
11160       if (PN.use_empty())
11161         continue;
11162 
11163       // Skip empty types
11164       if (PN.getType()->isEmptyTy())
11165         continue;
11166 
11167       unsigned Reg;
11168       const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
11169 
11170       if (const auto *C = dyn_cast<Constant>(PHIOp)) {
11171         unsigned &RegOut = ConstantsOut[C];
11172         if (RegOut == 0) {
11173           RegOut = FuncInfo.CreateRegs(C);
11174           // We need to zero/sign extend ConstantInt phi operands to match
11175           // assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo.
11176           ISD::NodeType ExtendType = ISD::ANY_EXTEND;
11177           if (auto *CI = dyn_cast<ConstantInt>(C))
11178             ExtendType = TLI.signExtendConstant(CI) ? ISD::SIGN_EXTEND
11179                                                     : ISD::ZERO_EXTEND;
11180           CopyValueToVirtualRegister(C, RegOut, ExtendType);
11181         }
11182         Reg = RegOut;
11183       } else {
11184         DenseMap<const Value *, Register>::iterator I =
11185           FuncInfo.ValueMap.find(PHIOp);
11186         if (I != FuncInfo.ValueMap.end())
11187           Reg = I->second;
11188         else {
11189           assert(isa<AllocaInst>(PHIOp) &&
11190                  FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
11191                  "Didn't codegen value into a register!??");
11192           Reg = FuncInfo.CreateRegs(PHIOp);
11193           CopyValueToVirtualRegister(PHIOp, Reg);
11194         }
11195       }
11196 
11197       // Remember that this register needs to added to the machine PHI node as
11198       // the input for this MBB.
11199       SmallVector<EVT, 4> ValueVTs;
11200       ComputeValueVTs(TLI, DAG.getDataLayout(), PN.getType(), ValueVTs);
11201       for (EVT VT : ValueVTs) {
11202         const unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
11203         for (unsigned i = 0; i != NumRegisters; ++i)
11204           FuncInfo.PHINodesToUpdate.push_back(
11205               std::make_pair(&*MBBI++, Reg + i));
11206         Reg += NumRegisters;
11207       }
11208     }
11209   }
11210 
11211   ConstantsOut.clear();
11212 }
11213 
11214 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
11215   MachineFunction::iterator I(MBB);
11216   if (++I == FuncInfo.MF->end())
11217     return nullptr;
11218   return &*I;
11219 }
11220 
11221 /// During lowering new call nodes can be created (such as memset, etc.).
11222 /// Those will become new roots of the current DAG, but complications arise
11223 /// when they are tail calls. In such cases, the call lowering will update
11224 /// the root, but the builder still needs to know that a tail call has been
11225 /// lowered in order to avoid generating an additional return.
11226 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
11227   // If the node is null, we do have a tail call.
11228   if (MaybeTC.getNode() != nullptr)
11229     DAG.setRoot(MaybeTC);
11230   else
11231     HasTailCall = true;
11232 }
11233 
11234 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
11235                                         MachineBasicBlock *SwitchMBB,
11236                                         MachineBasicBlock *DefaultMBB) {
11237   MachineFunction *CurMF = FuncInfo.MF;
11238   MachineBasicBlock *NextMBB = nullptr;
11239   MachineFunction::iterator BBI(W.MBB);
11240   if (++BBI != FuncInfo.MF->end())
11241     NextMBB = &*BBI;
11242 
11243   unsigned Size = W.LastCluster - W.FirstCluster + 1;
11244 
11245   BranchProbabilityInfo *BPI = FuncInfo.BPI;
11246 
11247   if (Size == 2 && W.MBB == SwitchMBB) {
11248     // If any two of the cases has the same destination, and if one value
11249     // is the same as the other, but has one bit unset that the other has set,
11250     // use bit manipulation to do two compares at once.  For example:
11251     // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
11252     // TODO: This could be extended to merge any 2 cases in switches with 3
11253     // cases.
11254     // TODO: Handle cases where W.CaseBB != SwitchBB.
11255     CaseCluster &Small = *W.FirstCluster;
11256     CaseCluster &Big = *W.LastCluster;
11257 
11258     if (Small.Low == Small.High && Big.Low == Big.High &&
11259         Small.MBB == Big.MBB) {
11260       const APInt &SmallValue = Small.Low->getValue();
11261       const APInt &BigValue = Big.Low->getValue();
11262 
11263       // Check that there is only one bit different.
11264       APInt CommonBit = BigValue ^ SmallValue;
11265       if (CommonBit.isPowerOf2()) {
11266         SDValue CondLHS = getValue(Cond);
11267         EVT VT = CondLHS.getValueType();
11268         SDLoc DL = getCurSDLoc();
11269 
11270         SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
11271                                  DAG.getConstant(CommonBit, DL, VT));
11272         SDValue Cond = DAG.getSetCC(
11273             DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
11274             ISD::SETEQ);
11275 
11276         // Update successor info.
11277         // Both Small and Big will jump to Small.BB, so we sum up the
11278         // probabilities.
11279         addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob);
11280         if (BPI)
11281           addSuccessorWithProb(
11282               SwitchMBB, DefaultMBB,
11283               // The default destination is the first successor in IR.
11284               BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0));
11285         else
11286           addSuccessorWithProb(SwitchMBB, DefaultMBB);
11287 
11288         // Insert the true branch.
11289         SDValue BrCond =
11290             DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
11291                         DAG.getBasicBlock(Small.MBB));
11292         // Insert the false branch.
11293         BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
11294                              DAG.getBasicBlock(DefaultMBB));
11295 
11296         DAG.setRoot(BrCond);
11297         return;
11298       }
11299     }
11300   }
11301 
11302   if (TM.getOptLevel() != CodeGenOptLevel::None) {
11303     // Here, we order cases by probability so the most likely case will be
11304     // checked first. However, two clusters can have the same probability in
11305     // which case their relative ordering is non-deterministic. So we use Low
11306     // as a tie-breaker as clusters are guaranteed to never overlap.
11307     llvm::sort(W.FirstCluster, W.LastCluster + 1,
11308                [](const CaseCluster &a, const CaseCluster &b) {
11309       return a.Prob != b.Prob ?
11310              a.Prob > b.Prob :
11311              a.Low->getValue().slt(b.Low->getValue());
11312     });
11313 
11314     // Rearrange the case blocks so that the last one falls through if possible
11315     // without changing the order of probabilities.
11316     for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
11317       --I;
11318       if (I->Prob > W.LastCluster->Prob)
11319         break;
11320       if (I->Kind == CC_Range && I->MBB == NextMBB) {
11321         std::swap(*I, *W.LastCluster);
11322         break;
11323       }
11324     }
11325   }
11326 
11327   // Compute total probability.
11328   BranchProbability DefaultProb = W.DefaultProb;
11329   BranchProbability UnhandledProbs = DefaultProb;
11330   for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
11331     UnhandledProbs += I->Prob;
11332 
11333   MachineBasicBlock *CurMBB = W.MBB;
11334   for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
11335     bool FallthroughUnreachable = false;
11336     MachineBasicBlock *Fallthrough;
11337     if (I == W.LastCluster) {
11338       // For the last cluster, fall through to the default destination.
11339       Fallthrough = DefaultMBB;
11340       FallthroughUnreachable = isa<UnreachableInst>(
11341           DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
11342     } else {
11343       Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
11344       CurMF->insert(BBI, Fallthrough);
11345       // Put Cond in a virtual register to make it available from the new blocks.
11346       ExportFromCurrentBlock(Cond);
11347     }
11348     UnhandledProbs -= I->Prob;
11349 
11350     switch (I->Kind) {
11351       case CC_JumpTable: {
11352         // FIXME: Optimize away range check based on pivot comparisons.
11353         JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first;
11354         SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second;
11355 
11356         // The jump block hasn't been inserted yet; insert it here.
11357         MachineBasicBlock *JumpMBB = JT->MBB;
11358         CurMF->insert(BBI, JumpMBB);
11359 
11360         auto JumpProb = I->Prob;
11361         auto FallthroughProb = UnhandledProbs;
11362 
11363         // If the default statement is a target of the jump table, we evenly
11364         // distribute the default probability to successors of CurMBB. Also
11365         // update the probability on the edge from JumpMBB to Fallthrough.
11366         for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
11367                                               SE = JumpMBB->succ_end();
11368              SI != SE; ++SI) {
11369           if (*SI == DefaultMBB) {
11370             JumpProb += DefaultProb / 2;
11371             FallthroughProb -= DefaultProb / 2;
11372             JumpMBB->setSuccProbability(SI, DefaultProb / 2);
11373             JumpMBB->normalizeSuccProbs();
11374             break;
11375           }
11376         }
11377 
11378         // If the default clause is unreachable, propagate that knowledge into
11379         // JTH->FallthroughUnreachable which will use it to suppress the range
11380         // check.
11381         //
11382         // However, don't do this if we're doing branch target enforcement,
11383         // because a table branch _without_ a range check can be a tempting JOP
11384         // gadget - out-of-bounds inputs that are impossible in correct
11385         // execution become possible again if an attacker can influence the
11386         // control flow. So if an attacker doesn't already have a BTI bypass
11387         // available, we don't want them to be able to get one out of this
11388         // table branch.
11389         if (FallthroughUnreachable) {
11390           Function &CurFunc = CurMF->getFunction();
11391           bool HasBranchTargetEnforcement = false;
11392           if (CurFunc.hasFnAttribute("branch-target-enforcement")) {
11393             HasBranchTargetEnforcement =
11394                 CurFunc.getFnAttribute("branch-target-enforcement")
11395                     .getValueAsBool();
11396           } else {
11397             HasBranchTargetEnforcement =
11398                 CurMF->getMMI().getModule()->getModuleFlag(
11399                     "branch-target-enforcement");
11400           }
11401           if (!HasBranchTargetEnforcement)
11402             JTH->FallthroughUnreachable = true;
11403         }
11404 
11405         if (!JTH->FallthroughUnreachable)
11406           addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
11407         addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
11408         CurMBB->normalizeSuccProbs();
11409 
11410         // The jump table header will be inserted in our current block, do the
11411         // range check, and fall through to our fallthrough block.
11412         JTH->HeaderBB = CurMBB;
11413         JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
11414 
11415         // If we're in the right place, emit the jump table header right now.
11416         if (CurMBB == SwitchMBB) {
11417           visitJumpTableHeader(*JT, *JTH, SwitchMBB);
11418           JTH->Emitted = true;
11419         }
11420         break;
11421       }
11422       case CC_BitTests: {
11423         // FIXME: Optimize away range check based on pivot comparisons.
11424         BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
11425 
11426         // The bit test blocks haven't been inserted yet; insert them here.
11427         for (BitTestCase &BTC : BTB->Cases)
11428           CurMF->insert(BBI, BTC.ThisBB);
11429 
11430         // Fill in fields of the BitTestBlock.
11431         BTB->Parent = CurMBB;
11432         BTB->Default = Fallthrough;
11433 
11434         BTB->DefaultProb = UnhandledProbs;
11435         // If the cases in bit test don't form a contiguous range, we evenly
11436         // distribute the probability on the edge to Fallthrough to two
11437         // successors of CurMBB.
11438         if (!BTB->ContiguousRange) {
11439           BTB->Prob += DefaultProb / 2;
11440           BTB->DefaultProb -= DefaultProb / 2;
11441         }
11442 
11443         if (FallthroughUnreachable)
11444           BTB->FallthroughUnreachable = true;
11445 
11446         // If we're in the right place, emit the bit test header right now.
11447         if (CurMBB == SwitchMBB) {
11448           visitBitTestHeader(*BTB, SwitchMBB);
11449           BTB->Emitted = true;
11450         }
11451         break;
11452       }
11453       case CC_Range: {
11454         const Value *RHS, *LHS, *MHS;
11455         ISD::CondCode CC;
11456         if (I->Low == I->High) {
11457           // Check Cond == I->Low.
11458           CC = ISD::SETEQ;
11459           LHS = Cond;
11460           RHS=I->Low;
11461           MHS = nullptr;
11462         } else {
11463           // Check I->Low <= Cond <= I->High.
11464           CC = ISD::SETLE;
11465           LHS = I->Low;
11466           MHS = Cond;
11467           RHS = I->High;
11468         }
11469 
11470         // If Fallthrough is unreachable, fold away the comparison.
11471         if (FallthroughUnreachable)
11472           CC = ISD::SETTRUE;
11473 
11474         // The false probability is the sum of all unhandled cases.
11475         CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB,
11476                      getCurSDLoc(), I->Prob, UnhandledProbs);
11477 
11478         if (CurMBB == SwitchMBB)
11479           visitSwitchCase(CB, SwitchMBB);
11480         else
11481           SL->SwitchCases.push_back(CB);
11482 
11483         break;
11484       }
11485     }
11486     CurMBB = Fallthrough;
11487   }
11488 }
11489 
11490 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
11491                                               CaseClusterIt First,
11492                                               CaseClusterIt Last) {
11493   return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
11494     if (X.Prob != CC.Prob)
11495       return X.Prob > CC.Prob;
11496 
11497     // Ties are broken by comparing the case value.
11498     return X.Low->getValue().slt(CC.Low->getValue());
11499   });
11500 }
11501 
11502 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
11503                                         const SwitchWorkListItem &W,
11504                                         Value *Cond,
11505                                         MachineBasicBlock *SwitchMBB) {
11506   assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
11507          "Clusters not sorted?");
11508 
11509   assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
11510 
11511   // Balance the tree based on branch probabilities to create a near-optimal (in
11512   // terms of search time given key frequency) binary search tree. See e.g. Kurt
11513   // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
11514   CaseClusterIt LastLeft = W.FirstCluster;
11515   CaseClusterIt FirstRight = W.LastCluster;
11516   auto LeftProb = LastLeft->Prob + W.DefaultProb / 2;
11517   auto RightProb = FirstRight->Prob + W.DefaultProb / 2;
11518 
11519   // Move LastLeft and FirstRight towards each other from opposite directions to
11520   // find a partitioning of the clusters which balances the probability on both
11521   // sides. If LeftProb and RightProb are equal, alternate which side is
11522   // taken to ensure 0-probability nodes are distributed evenly.
11523   unsigned I = 0;
11524   while (LastLeft + 1 < FirstRight) {
11525     if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1)))
11526       LeftProb += (++LastLeft)->Prob;
11527     else
11528       RightProb += (--FirstRight)->Prob;
11529     I++;
11530   }
11531 
11532   while (true) {
11533     // Our binary search tree differs from a typical BST in that ours can have up
11534     // to three values in each leaf. The pivot selection above doesn't take that
11535     // into account, which means the tree might require more nodes and be less
11536     // efficient. We compensate for this here.
11537 
11538     unsigned NumLeft = LastLeft - W.FirstCluster + 1;
11539     unsigned NumRight = W.LastCluster - FirstRight + 1;
11540 
11541     if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
11542       // If one side has less than 3 clusters, and the other has more than 3,
11543       // consider taking a cluster from the other side.
11544 
11545       if (NumLeft < NumRight) {
11546         // Consider moving the first cluster on the right to the left side.
11547         CaseCluster &CC = *FirstRight;
11548         unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
11549         unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
11550         if (LeftSideRank <= RightSideRank) {
11551           // Moving the cluster to the left does not demote it.
11552           ++LastLeft;
11553           ++FirstRight;
11554           continue;
11555         }
11556       } else {
11557         assert(NumRight < NumLeft);
11558         // Consider moving the last element on the left to the right side.
11559         CaseCluster &CC = *LastLeft;
11560         unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
11561         unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
11562         if (RightSideRank <= LeftSideRank) {
11563           // Moving the cluster to the right does not demot it.
11564           --LastLeft;
11565           --FirstRight;
11566           continue;
11567         }
11568       }
11569     }
11570     break;
11571   }
11572 
11573   assert(LastLeft + 1 == FirstRight);
11574   assert(LastLeft >= W.FirstCluster);
11575   assert(FirstRight <= W.LastCluster);
11576 
11577   // Use the first element on the right as pivot since we will make less-than
11578   // comparisons against it.
11579   CaseClusterIt PivotCluster = FirstRight;
11580   assert(PivotCluster > W.FirstCluster);
11581   assert(PivotCluster <= W.LastCluster);
11582 
11583   CaseClusterIt FirstLeft = W.FirstCluster;
11584   CaseClusterIt LastRight = W.LastCluster;
11585 
11586   const ConstantInt *Pivot = PivotCluster->Low;
11587 
11588   // New blocks will be inserted immediately after the current one.
11589   MachineFunction::iterator BBI(W.MBB);
11590   ++BBI;
11591 
11592   // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
11593   // we can branch to its destination directly if it's squeezed exactly in
11594   // between the known lower bound and Pivot - 1.
11595   MachineBasicBlock *LeftMBB;
11596   if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
11597       FirstLeft->Low == W.GE &&
11598       (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
11599     LeftMBB = FirstLeft->MBB;
11600   } else {
11601     LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
11602     FuncInfo.MF->insert(BBI, LeftMBB);
11603     WorkList.push_back(
11604         {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
11605     // Put Cond in a virtual register to make it available from the new blocks.
11606     ExportFromCurrentBlock(Cond);
11607   }
11608 
11609   // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
11610   // single cluster, RHS.Low == Pivot, and we can branch to its destination
11611   // directly if RHS.High equals the current upper bound.
11612   MachineBasicBlock *RightMBB;
11613   if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
11614       W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
11615     RightMBB = FirstRight->MBB;
11616   } else {
11617     RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
11618     FuncInfo.MF->insert(BBI, RightMBB);
11619     WorkList.push_back(
11620         {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
11621     // Put Cond in a virtual register to make it available from the new blocks.
11622     ExportFromCurrentBlock(Cond);
11623   }
11624 
11625   // Create the CaseBlock record that will be used to lower the branch.
11626   CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
11627                getCurSDLoc(), LeftProb, RightProb);
11628 
11629   if (W.MBB == SwitchMBB)
11630     visitSwitchCase(CB, SwitchMBB);
11631   else
11632     SL->SwitchCases.push_back(CB);
11633 }
11634 
11635 // Scale CaseProb after peeling a case with the probablity of PeeledCaseProb
11636 // from the swith statement.
11637 static BranchProbability scaleCaseProbality(BranchProbability CaseProb,
11638                                             BranchProbability PeeledCaseProb) {
11639   if (PeeledCaseProb == BranchProbability::getOne())
11640     return BranchProbability::getZero();
11641   BranchProbability SwitchProb = PeeledCaseProb.getCompl();
11642 
11643   uint32_t Numerator = CaseProb.getNumerator();
11644   uint32_t Denominator = SwitchProb.scale(CaseProb.getDenominator());
11645   return BranchProbability(Numerator, std::max(Numerator, Denominator));
11646 }
11647 
11648 // Try to peel the top probability case if it exceeds the threshold.
11649 // Return current MachineBasicBlock for the switch statement if the peeling
11650 // does not occur.
11651 // If the peeling is performed, return the newly created MachineBasicBlock
11652 // for the peeled switch statement. Also update Clusters to remove the peeled
11653 // case. PeeledCaseProb is the BranchProbability for the peeled case.
11654 MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
11655     const SwitchInst &SI, CaseClusterVector &Clusters,
11656     BranchProbability &PeeledCaseProb) {
11657   MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
11658   // Don't perform if there is only one cluster or optimizing for size.
11659   if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
11660       TM.getOptLevel() == CodeGenOptLevel::None ||
11661       SwitchMBB->getParent()->getFunction().hasMinSize())
11662     return SwitchMBB;
11663 
11664   BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100);
11665   unsigned PeeledCaseIndex = 0;
11666   bool SwitchPeeled = false;
11667   for (unsigned Index = 0; Index < Clusters.size(); ++Index) {
11668     CaseCluster &CC = Clusters[Index];
11669     if (CC.Prob < TopCaseProb)
11670       continue;
11671     TopCaseProb = CC.Prob;
11672     PeeledCaseIndex = Index;
11673     SwitchPeeled = true;
11674   }
11675   if (!SwitchPeeled)
11676     return SwitchMBB;
11677 
11678   LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: "
11679                     << TopCaseProb << "\n");
11680 
11681   // Record the MBB for the peeled switch statement.
11682   MachineFunction::iterator BBI(SwitchMBB);
11683   ++BBI;
11684   MachineBasicBlock *PeeledSwitchMBB =
11685       FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock());
11686   FuncInfo.MF->insert(BBI, PeeledSwitchMBB);
11687 
11688   ExportFromCurrentBlock(SI.getCondition());
11689   auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
11690   SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt,
11691                           nullptr,   nullptr,      TopCaseProb.getCompl()};
11692   lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
11693 
11694   Clusters.erase(PeeledCaseIt);
11695   for (CaseCluster &CC : Clusters) {
11696     LLVM_DEBUG(
11697         dbgs() << "Scale the probablity for one cluster, before scaling: "
11698                << CC.Prob << "\n");
11699     CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb);
11700     LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n");
11701   }
11702   PeeledCaseProb = TopCaseProb;
11703   return PeeledSwitchMBB;
11704 }
11705 
11706 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
11707   // Extract cases from the switch.
11708   BranchProbabilityInfo *BPI = FuncInfo.BPI;
11709   CaseClusterVector Clusters;
11710   Clusters.reserve(SI.getNumCases());
11711   for (auto I : SI.cases()) {
11712     MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
11713     const ConstantInt *CaseVal = I.getCaseValue();
11714     BranchProbability Prob =
11715         BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
11716             : BranchProbability(1, SI.getNumCases() + 1);
11717     Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
11718   }
11719 
11720   MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
11721 
11722   // Cluster adjacent cases with the same destination. We do this at all
11723   // optimization levels because it's cheap to do and will make codegen faster
11724   // if there are many clusters.
11725   sortAndRangeify(Clusters);
11726 
11727   // The branch probablity of the peeled case.
11728   BranchProbability PeeledCaseProb = BranchProbability::getZero();
11729   MachineBasicBlock *PeeledSwitchMBB =
11730       peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
11731 
11732   // If there is only the default destination, jump there directly.
11733   MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
11734   if (Clusters.empty()) {
11735     assert(PeeledSwitchMBB == SwitchMBB);
11736     SwitchMBB->addSuccessor(DefaultMBB);
11737     if (DefaultMBB != NextBlock(SwitchMBB)) {
11738       DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
11739                               getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
11740     }
11741     return;
11742   }
11743 
11744   SL->findJumpTables(Clusters, &SI, DefaultMBB, DAG.getPSI(), DAG.getBFI());
11745   SL->findBitTestClusters(Clusters, &SI);
11746 
11747   LLVM_DEBUG({
11748     dbgs() << "Case clusters: ";
11749     for (const CaseCluster &C : Clusters) {
11750       if (C.Kind == CC_JumpTable)
11751         dbgs() << "JT:";
11752       if (C.Kind == CC_BitTests)
11753         dbgs() << "BT:";
11754 
11755       C.Low->getValue().print(dbgs(), true);
11756       if (C.Low != C.High) {
11757         dbgs() << '-';
11758         C.High->getValue().print(dbgs(), true);
11759       }
11760       dbgs() << ' ';
11761     }
11762     dbgs() << '\n';
11763   });
11764 
11765   assert(!Clusters.empty());
11766   SwitchWorkList WorkList;
11767   CaseClusterIt First = Clusters.begin();
11768   CaseClusterIt Last = Clusters.end() - 1;
11769   auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB);
11770   // Scale the branchprobability for DefaultMBB if the peel occurs and
11771   // DefaultMBB is not replaced.
11772   if (PeeledCaseProb != BranchProbability::getZero() &&
11773       DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()])
11774     DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb);
11775   WorkList.push_back(
11776       {PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
11777 
11778   while (!WorkList.empty()) {
11779     SwitchWorkListItem W = WorkList.pop_back_val();
11780     unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
11781 
11782     if (NumClusters > 3 && TM.getOptLevel() != CodeGenOptLevel::None &&
11783         !DefaultMBB->getParent()->getFunction().hasMinSize()) {
11784       // For optimized builds, lower large range as a balanced binary tree.
11785       splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
11786       continue;
11787     }
11788 
11789     lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);
11790   }
11791 }
11792 
11793 void SelectionDAGBuilder::visitStepVector(const CallInst &I) {
11794   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11795   auto DL = getCurSDLoc();
11796   EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
11797   setValue(&I, DAG.getStepVector(DL, ResultVT));
11798 }
11799 
11800 void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) {
11801   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11802   EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
11803 
11804   SDLoc DL = getCurSDLoc();
11805   SDValue V = getValue(I.getOperand(0));
11806   assert(VT == V.getValueType() && "Malformed vector.reverse!");
11807 
11808   if (VT.isScalableVector()) {
11809     setValue(&I, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V));
11810     return;
11811   }
11812 
11813   // Use VECTOR_SHUFFLE for the fixed-length vector
11814   // to maintain existing behavior.
11815   SmallVector<int, 8> Mask;
11816   unsigned NumElts = VT.getVectorMinNumElements();
11817   for (unsigned i = 0; i != NumElts; ++i)
11818     Mask.push_back(NumElts - 1 - i);
11819 
11820   setValue(&I, DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), Mask));
11821 }
11822 
11823 void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I) {
11824   auto DL = getCurSDLoc();
11825   SDValue InVec = getValue(I.getOperand(0));
11826   EVT OutVT =
11827       InVec.getValueType().getHalfNumVectorElementsVT(*DAG.getContext());
11828 
11829   unsigned OutNumElts = OutVT.getVectorMinNumElements();
11830 
11831   // ISD Node needs the input vectors split into two equal parts
11832   SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
11833                            DAG.getVectorIdxConstant(0, DL));
11834   SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
11835                            DAG.getVectorIdxConstant(OutNumElts, DL));
11836 
11837   // Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing
11838   // legalisation and combines.
11839   if (OutVT.isFixedLengthVector()) {
11840     SDValue Even = DAG.getVectorShuffle(OutVT, DL, Lo, Hi,
11841                                         createStrideMask(0, 2, OutNumElts));
11842     SDValue Odd = DAG.getVectorShuffle(OutVT, DL, Lo, Hi,
11843                                        createStrideMask(1, 2, OutNumElts));
11844     SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc());
11845     setValue(&I, Res);
11846     return;
11847   }
11848 
11849   SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
11850                             DAG.getVTList(OutVT, OutVT), Lo, Hi);
11851   setValue(&I, Res);
11852 }
11853 
11854 void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I) {
11855   auto DL = getCurSDLoc();
11856   EVT InVT = getValue(I.getOperand(0)).getValueType();
11857   SDValue InVec0 = getValue(I.getOperand(0));
11858   SDValue InVec1 = getValue(I.getOperand(1));
11859   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11860   EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
11861 
11862   // Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing
11863   // legalisation and combines.
11864   if (OutVT.isFixedLengthVector()) {
11865     unsigned NumElts = InVT.getVectorMinNumElements();
11866     SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVec0, InVec1);
11867     setValue(&I, DAG.getVectorShuffle(OutVT, DL, V, DAG.getUNDEF(OutVT),
11868                                       createInterleaveMask(NumElts, 2)));
11869     return;
11870   }
11871 
11872   SDValue Res = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL,
11873                             DAG.getVTList(InVT, InVT), InVec0, InVec1);
11874   Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Res.getValue(0),
11875                     Res.getValue(1));
11876   setValue(&I, Res);
11877 }
11878 
11879 void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) {
11880   SmallVector<EVT, 4> ValueVTs;
11881   ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
11882                   ValueVTs);
11883   unsigned NumValues = ValueVTs.size();
11884   if (NumValues == 0) return;
11885 
11886   SmallVector<SDValue, 4> Values(NumValues);
11887   SDValue Op = getValue(I.getOperand(0));
11888 
11889   for (unsigned i = 0; i != NumValues; ++i)
11890     Values[i] = DAG.getNode(ISD::FREEZE, getCurSDLoc(), ValueVTs[i],
11891                             SDValue(Op.getNode(), Op.getResNo() + i));
11892 
11893   setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
11894                            DAG.getVTList(ValueVTs), Values));
11895 }
11896 
11897 void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) {
11898   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11899   EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
11900 
11901   SDLoc DL = getCurSDLoc();
11902   SDValue V1 = getValue(I.getOperand(0));
11903   SDValue V2 = getValue(I.getOperand(1));
11904   int64_t Imm = cast<ConstantInt>(I.getOperand(2))->getSExtValue();
11905 
11906   // VECTOR_SHUFFLE doesn't support a scalable mask so use a dedicated node.
11907   if (VT.isScalableVector()) {
11908     MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
11909     setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2,
11910                              DAG.getConstant(Imm, DL, IdxVT)));
11911     return;
11912   }
11913 
11914   unsigned NumElts = VT.getVectorNumElements();
11915 
11916   uint64_t Idx = (NumElts + Imm) % NumElts;
11917 
11918   // Use VECTOR_SHUFFLE to maintain original behaviour for fixed-length vectors.
11919   SmallVector<int, 8> Mask;
11920   for (unsigned i = 0; i < NumElts; ++i)
11921     Mask.push_back(Idx + i);
11922   setValue(&I, DAG.getVectorShuffle(VT, DL, V1, V2, Mask));
11923 }
11924 
11925 // Consider the following MIR after SelectionDAG, which produces output in
11926 // phyregs in the first case or virtregs in the second case.
11927 //
11928 // INLINEASM_BR ..., implicit-def $ebx, ..., implicit-def $edx
11929 // %5:gr32 = COPY $ebx
11930 // %6:gr32 = COPY $edx
11931 // %1:gr32 = COPY %6:gr32
11932 // %0:gr32 = COPY %5:gr32
11933 //
11934 // INLINEASM_BR ..., def %5:gr32, ..., def %6:gr32
11935 // %1:gr32 = COPY %6:gr32
11936 // %0:gr32 = COPY %5:gr32
11937 //
11938 // Given %0, we'd like to return $ebx in the first case and %5 in the second.
11939 // Given %1, we'd like to return $edx in the first case and %6 in the second.
11940 //
11941 // If a callbr has outputs, it will have a single mapping in FuncInfo.ValueMap
11942 // to a single virtreg (such as %0). The remaining outputs monotonically
11943 // increase in virtreg number from there. If a callbr has no outputs, then it
11944 // should not have a corresponding callbr landingpad; in fact, the callbr
11945 // landingpad would not even be able to refer to such a callbr.
11946 static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) {
11947   MachineInstr *MI = MRI.def_begin(Reg)->getParent();
11948   // There is definitely at least one copy.
11949   assert(MI->getOpcode() == TargetOpcode::COPY &&
11950          "start of copy chain MUST be COPY");
11951   Reg = MI->getOperand(1).getReg();
11952   MI = MRI.def_begin(Reg)->getParent();
11953   // There may be an optional second copy.
11954   if (MI->getOpcode() == TargetOpcode::COPY) {
11955     assert(Reg.isVirtual() && "expected COPY of virtual register");
11956     Reg = MI->getOperand(1).getReg();
11957     assert(Reg.isPhysical() && "expected COPY of physical register");
11958     MI = MRI.def_begin(Reg)->getParent();
11959   }
11960   // The start of the chain must be an INLINEASM_BR.
11961   assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR &&
11962          "end of copy chain MUST be INLINEASM_BR");
11963   return Reg;
11964 }
11965 
11966 // We must do this walk rather than the simpler
11967 //   setValue(&I, getCopyFromRegs(CBR, CBR->getType()));
11968 // otherwise we will end up with copies of virtregs only valid along direct
11969 // edges.
11970 void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
11971   SmallVector<EVT, 8> ResultVTs;
11972   SmallVector<SDValue, 8> ResultValues;
11973   const auto *CBR =
11974       cast<CallBrInst>(I.getParent()->getUniquePredecessor()->getTerminator());
11975 
11976   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11977   const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
11978   MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
11979 
11980   unsigned InitialDef = FuncInfo.ValueMap[CBR];
11981   SDValue Chain = DAG.getRoot();
11982 
11983   // Re-parse the asm constraints string.
11984   TargetLowering::AsmOperandInfoVector TargetConstraints =
11985       TLI.ParseConstraints(DAG.getDataLayout(), TRI, *CBR);
11986   for (auto &T : TargetConstraints) {
11987     SDISelAsmOperandInfo OpInfo(T);
11988     if (OpInfo.Type != InlineAsm::isOutput)
11989       continue;
11990 
11991     // Pencil in OpInfo.ConstraintType and OpInfo.ConstraintVT based on the
11992     // individual constraint.
11993     TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
11994 
11995     switch (OpInfo.ConstraintType) {
11996     case TargetLowering::C_Register:
11997     case TargetLowering::C_RegisterClass: {
11998       // Fill in OpInfo.AssignedRegs.Regs.
11999       getRegistersForValue(DAG, getCurSDLoc(), OpInfo, OpInfo);
12000 
12001       // getRegistersForValue may produce 1 to many registers based on whether
12002       // the OpInfo.ConstraintVT is legal on the target or not.
12003       for (size_t i = 0, e = OpInfo.AssignedRegs.Regs.size(); i != e; ++i) {
12004         Register OriginalDef = FollowCopyChain(MRI, InitialDef++);
12005         if (Register::isPhysicalRegister(OriginalDef))
12006           FuncInfo.MBB->addLiveIn(OriginalDef);
12007         // Update the assigned registers to use the original defs.
12008         OpInfo.AssignedRegs.Regs[i] = OriginalDef;
12009       }
12010 
12011       SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
12012           DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, CBR);
12013       ResultValues.push_back(V);
12014       ResultVTs.push_back(OpInfo.ConstraintVT);
12015       break;
12016     }
12017     case TargetLowering::C_Other: {
12018       SDValue Flag;
12019       SDValue V = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(),
12020                                                   OpInfo, DAG);
12021       ++InitialDef;
12022       ResultValues.push_back(V);
12023       ResultVTs.push_back(OpInfo.ConstraintVT);
12024       break;
12025     }
12026     default:
12027       break;
12028     }
12029   }
12030   SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
12031                           DAG.getVTList(ResultVTs), ResultValues);
12032   setValue(&I, V);
12033 }
12034