1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 //===----------------------------------------------------------------------===// 4 5 #include "llvm/CodeGen/MachineInstr.h" 6 #include "llvm/CodeGen/MachineBasicBlock.h" 7 #include "llvm/Value.h" 8 #include "llvm/Target/TargetMachine.h" 9 #include "llvm/Target/TargetInstrInfo.h" 10 #include "llvm/Target/MRegisterInfo.h" 11 12 // Global variable holding an array of descriptors for machine instructions. 13 // The actual object needs to be created separately for each target machine. 14 // This variable is initialized and reset by class TargetInstrInfo. 15 // 16 // FIXME: This should be a property of the target so that more than one target 17 // at a time can be active... 18 // 19 extern const TargetInstrDescriptor *TargetInstrDescriptors; 20 21 // Constructor for instructions with variable #operands 22 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands) 23 : opCode(OpCode), 24 opCodeFlags(0), 25 operands(numOperands, MachineOperand()), 26 numImplicitRefs(0) 27 { 28 } 29 30 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 31 /// not a resize for them. It is expected that if you use this that you call 32 /// add* methods below to fill up the operands, instead of the Set methods. 33 /// Eventually, the "resizing" ctors will be phased out. 34 /// 35 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands, 36 bool XX, bool YY) 37 : opCode(Opcode), 38 opCodeFlags(0), 39 numImplicitRefs(0) 40 { 41 operands.reserve(numOperands); 42 } 43 44 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 45 /// MachineInstr is created and added to the end of the specified basic block. 46 /// 47 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, 48 unsigned numOperands) 49 : opCode(Opcode), 50 opCodeFlags(0), 51 numImplicitRefs(0) 52 { 53 assert(MBB && "Cannot use inserting ctor with null basic block!"); 54 operands.reserve(numOperands); 55 MBB->push_back(this); // Add instruction to end of basic block! 56 } 57 58 59 // OperandComplete - Return true if it's illegal to add a new operand 60 bool MachineInstr::OperandsComplete() const 61 { 62 int NumOperands = TargetInstrDescriptors[opCode].numOperands; 63 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 64 return true; // Broken: we have all the operands of this instruction! 65 return false; 66 } 67 68 69 // 70 // Support for replacing opcode and operands of a MachineInstr in place. 71 // This only resets the size of the operand vector and initializes it. 72 // The new operands must be set explicitly later. 73 // 74 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands) 75 { 76 assert(getNumImplicitRefs() == 0 && 77 "This is probably broken because implicit refs are going to be lost."); 78 opCode = Opcode; 79 operands.clear(); 80 operands.resize(numOperands, MachineOperand()); 81 } 82 83 void 84 MachineInstr::SetMachineOperandVal(unsigned i, 85 MachineOperand::MachineOperandType opType, 86 Value* V, 87 bool isdef, 88 bool isDefAndUse) 89 { 90 assert(i < operands.size()); // may be explicit or implicit op 91 operands[i].opType = opType; 92 operands[i].value = V; 93 operands[i].regNum = -1; 94 95 if (isDefAndUse) 96 operands[i].flags = MachineOperand::DEFUSEFLAG; 97 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) 98 operands[i].flags = MachineOperand::DEFONLYFLAG; 99 else 100 operands[i].flags = 0; 101 } 102 103 void 104 MachineInstr::SetMachineOperandConst(unsigned i, 105 MachineOperand::MachineOperandType operandType, 106 int64_t intValue) 107 { 108 assert(i < getNumOperands()); // must be explicit op 109 assert(TargetInstrDescriptors[opCode].resultPos != (int) i && 110 "immed. constant cannot be defined"); 111 112 operands[i].opType = operandType; 113 operands[i].value = NULL; 114 operands[i].immedVal = intValue; 115 operands[i].regNum = -1; 116 operands[i].flags = 0; 117 } 118 119 void 120 MachineInstr::SetMachineOperandReg(unsigned i, 121 int regNum, 122 bool isdef) { 123 assert(i < getNumOperands()); // must be explicit op 124 125 operands[i].opType = MachineOperand::MO_MachineRegister; 126 operands[i].value = NULL; 127 operands[i].regNum = regNum; 128 129 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) 130 operands[i].flags = MachineOperand::DEFONLYFLAG; 131 else 132 operands[i].flags = 0; 133 134 insertUsedReg(regNum); 135 } 136 137 void 138 MachineInstr::SetRegForOperand(unsigned i, int regNum) 139 { 140 assert(i < getNumOperands()); // must be explicit op 141 operands[i].setRegForValue(regNum); 142 insertUsedReg(regNum); 143 } 144 145 void 146 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) 147 { 148 getImplicitOp(i).setRegForValue(regNum); 149 insertUsedReg(regNum); 150 } 151 152 153 // Subsitute all occurrences of Value* oldVal with newVal in all operands 154 // and all implicit refs. 155 // If defsOnly == true, substitute defs only. 156 unsigned 157 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, 158 bool defsOnly, bool notDefsAndUses, 159 bool& someArgsWereIgnored) 160 { 161 assert((defsOnly || !notDefsAndUses) && 162 "notDefsAndUses is irrelevant if defsOnly == false."); 163 164 unsigned numSubst = 0; 165 166 // Subsitute operands 167 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 168 if (*O == oldVal) 169 if (!defsOnly || 170 notDefsAndUses && O.isDefOnly() || 171 !notDefsAndUses && !O.isUseOnly()) 172 { 173 O.getMachineOperand().value = newVal; 174 ++numSubst; 175 } 176 else 177 someArgsWereIgnored = true; 178 179 // Subsitute implicit refs 180 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) 181 if (getImplicitRef(i) == oldVal) 182 if (!defsOnly || 183 notDefsAndUses && getImplicitOp(i).opIsDefOnly() || 184 !notDefsAndUses && !getImplicitOp(i).opIsUse()) 185 { 186 getImplicitOp(i).value = newVal; 187 ++numSubst; 188 } 189 else 190 someArgsWereIgnored = true; 191 192 return numSubst; 193 } 194 195 196 void 197 MachineInstr::dump() const 198 { 199 std::cerr << " " << *this; 200 } 201 202 static inline std::ostream& 203 OutputValue(std::ostream &os, const Value* val) 204 { 205 os << "(val "; 206 os << (void*) val; // print address always 207 if (val && val->hasName()) 208 os << " " << val->getName() << ")"; // print name also, if available 209 return os; 210 } 211 212 static inline void OutputReg(std::ostream &os, unsigned RegNo, 213 const MRegisterInfo *MRI = 0) { 214 if (MRI) { 215 if (RegNo < MRegisterInfo::FirstVirtualRegister) 216 os << "%" << MRI->get(RegNo).Name; 217 else 218 os << "%reg" << RegNo; 219 } else 220 os << "%mreg(" << RegNo << ")"; 221 } 222 223 static void print(const MachineOperand &MO, std::ostream &OS, 224 const TargetMachine &TM) { 225 const MRegisterInfo *MRI = TM.getRegisterInfo(); 226 bool CloseParen = true; 227 if (MO.opHiBits32()) 228 OS << "%lm("; 229 else if (MO.opLoBits32()) 230 OS << "%lo("; 231 else if (MO.opHiBits64()) 232 OS << "%hh("; 233 else if (MO.opLoBits64()) 234 OS << "%hm("; 235 else 236 CloseParen = false; 237 238 switch (MO.getType()) { 239 case MachineOperand::MO_VirtualRegister: 240 if (MO.getVRegValue()) { 241 OS << "%reg"; 242 OutputValue(OS, MO.getVRegValue()); 243 if (MO.hasAllocatedReg()) 244 OS << "=="; 245 } 246 if (MO.hasAllocatedReg()) 247 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 248 break; 249 case MachineOperand::MO_CCRegister: 250 OS << "%ccreg"; 251 OutputValue(OS, MO.getVRegValue()); 252 if (MO.hasAllocatedReg()) { 253 OS << "=="; 254 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 255 } 256 break; 257 case MachineOperand::MO_MachineRegister: 258 OutputReg(OS, MO.getMachineRegNum(), MRI); 259 break; 260 case MachineOperand::MO_SignExtendedImmed: 261 OS << (long)MO.getImmedValue(); 262 break; 263 case MachineOperand::MO_UnextendedImmed: 264 OS << (long)MO.getImmedValue(); 265 break; 266 case MachineOperand::MO_PCRelativeDisp: { 267 const Value* opVal = MO.getVRegValue(); 268 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 269 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 270 if (opVal->hasName()) 271 OS << opVal->getName(); 272 else 273 OS << (const void*) opVal; 274 OS << ")"; 275 break; 276 } 277 case MachineOperand::MO_MachineBasicBlock: 278 OS << "bb<" 279 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 280 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 281 break; 282 case MachineOperand::MO_FrameIndex: 283 OS << "<fi#" << MO.getFrameIndex() << ">"; 284 break; 285 case MachineOperand::MO_ConstantPoolIndex: 286 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 287 break; 288 case MachineOperand::MO_GlobalAddress: 289 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 290 break; 291 case MachineOperand::MO_ExternalSymbol: 292 OS << "<es:" << MO.getSymbolName() << ">"; 293 break; 294 default: 295 assert(0 && "Unrecognized operand type"); 296 } 297 298 if (CloseParen) 299 OS << ")"; 300 } 301 302 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { 303 unsigned StartOp = 0; 304 305 // Specialize printing if op#0 is definition 306 if (getNumOperands() && 307 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) { 308 ::print(getOperand(0), OS, TM); 309 OS << " = "; 310 ++StartOp; // Don't print this operand again! 311 } 312 OS << TM.getInstrInfo().getName(getOpcode()); 313 314 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 315 const MachineOperand& mop = getOperand(i); 316 if (i != StartOp) 317 OS << ","; 318 OS << " "; 319 ::print(mop, OS, TM); 320 321 if (mop.opIsDefAndUse()) 322 OS << "<def&use>"; 323 else if (mop.opIsDefOnly()) 324 OS << "<def>"; 325 } 326 327 // code for printing implict references 328 if (getNumImplicitRefs()) { 329 OS << "\tImplicitRefs: "; 330 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 331 OS << "\t"; 332 OutputValue(OS, getImplicitRef(i)); 333 if (getImplicitOp(i).opIsDefAndUse()) 334 OS << "<def&use>"; 335 else if (getImplicitOp(i).opIsDefOnly()) 336 OS << "<def>"; 337 } 338 } 339 340 OS << "\n"; 341 } 342 343 344 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) 345 { 346 os << TargetInstrDescriptors[MI.opCode].Name; 347 348 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { 349 os << "\t" << MI.getOperand(i); 350 if (MI.getOperand(i).opIsDefOnly()) 351 os << "<d>"; 352 if (MI.getOperand(i).opIsDefAndUse()) 353 os << "<d&u>"; 354 } 355 356 // code for printing implict references 357 unsigned NumOfImpRefs = MI.getNumImplicitRefs(); 358 if (NumOfImpRefs > 0) { 359 os << "\tImplicit: "; 360 for (unsigned z=0; z < NumOfImpRefs; z++) { 361 OutputValue(os, MI.getImplicitRef(z)); 362 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>"; 363 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>"; 364 os << "\t"; 365 } 366 } 367 368 return os << "\n"; 369 } 370 371 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) 372 { 373 if (MO.opHiBits32()) 374 OS << "%lm("; 375 else if (MO.opLoBits32()) 376 OS << "%lo("; 377 else if (MO.opHiBits64()) 378 OS << "%hh("; 379 else if (MO.opLoBits64()) 380 OS << "%hm("; 381 382 switch (MO.getType()) 383 { 384 case MachineOperand::MO_VirtualRegister: 385 if (MO.hasAllocatedReg()) 386 OutputReg(OS, MO.getAllocatedRegNum()); 387 388 if (MO.getVRegValue()) { 389 if (MO.hasAllocatedReg()) OS << "=="; 390 OS << "%vreg"; 391 OutputValue(OS, MO.getVRegValue()); 392 } 393 break; 394 case MachineOperand::MO_CCRegister: 395 OS << "%ccreg"; 396 OutputValue(OS, MO.getVRegValue()); 397 if (MO.hasAllocatedReg()) { 398 OS << "=="; 399 OutputReg(OS, MO.getAllocatedRegNum()); 400 } 401 break; 402 case MachineOperand::MO_MachineRegister: 403 OutputReg(OS, MO.getMachineRegNum()); 404 break; 405 case MachineOperand::MO_SignExtendedImmed: 406 OS << (long)MO.getImmedValue(); 407 break; 408 case MachineOperand::MO_UnextendedImmed: 409 OS << (long)MO.getImmedValue(); 410 break; 411 case MachineOperand::MO_PCRelativeDisp: 412 { 413 const Value* opVal = MO.getVRegValue(); 414 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 415 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 416 if (opVal->hasName()) 417 OS << opVal->getName(); 418 else 419 OS << (const void*) opVal; 420 OS << ")"; 421 break; 422 } 423 case MachineOperand::MO_MachineBasicBlock: 424 OS << "bb<" 425 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 426 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 427 break; 428 case MachineOperand::MO_FrameIndex: 429 OS << "<fi#" << MO.getFrameIndex() << ">"; 430 break; 431 case MachineOperand::MO_ConstantPoolIndex: 432 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 433 break; 434 case MachineOperand::MO_GlobalAddress: 435 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 436 break; 437 case MachineOperand::MO_ExternalSymbol: 438 OS << "<es:" << MO.getSymbolName() << ">"; 439 break; 440 default: 441 assert(0 && "Unrecognized operand type"); 442 break; 443 } 444 445 if (MO.flags & 446 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | 447 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) 448 OS << ")"; 449 450 return OS; 451 } 452