1 //===-- LiveRegMatrix.cpp - Track register interference -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the LiveRegMatrix analysis pass. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/LiveRegMatrix.h" 15 #include "RegisterCoalescer.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/VirtRegMap.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/raw_ostream.h" 22 #include "llvm/Support/Format.h" 23 #include "llvm/Target/TargetRegisterInfo.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "regalloc" 28 29 STATISTIC(NumAssigned , "Number of registers assigned"); 30 STATISTIC(NumUnassigned , "Number of registers unassigned"); 31 32 char LiveRegMatrix::ID = 0; 33 INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix", 34 "Live Register Matrix", false, false) 35 INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 36 INITIALIZE_PASS_DEPENDENCY(VirtRegMap) 37 INITIALIZE_PASS_END(LiveRegMatrix, "liveregmatrix", 38 "Live Register Matrix", false, false) 39 40 LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID), 41 UserTag(0), RegMaskTag(0), RegMaskVirtReg(0) {} 42 43 void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const { 44 AU.setPreservesAll(); 45 AU.addRequiredTransitive<LiveIntervals>(); 46 AU.addRequiredTransitive<VirtRegMap>(); 47 MachineFunctionPass::getAnalysisUsage(AU); 48 } 49 50 bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) { 51 TRI = MF.getSubtarget().getRegisterInfo(); 52 MRI = &MF.getRegInfo(); 53 LIS = &getAnalysis<LiveIntervals>(); 54 VRM = &getAnalysis<VirtRegMap>(); 55 56 unsigned NumRegUnits = TRI->getNumRegUnits(); 57 if (NumRegUnits != Matrix.size()) 58 Queries.reset(new LiveIntervalUnion::Query[NumRegUnits]); 59 Matrix.init(LIUAlloc, NumRegUnits); 60 61 // Make sure no stale queries get reused. 62 invalidateVirtRegs(); 63 return false; 64 } 65 66 void LiveRegMatrix::releaseMemory() { 67 for (unsigned i = 0, e = Matrix.size(); i != e; ++i) { 68 Matrix[i].clear(); 69 // No need to clear Queries here, since LiveIntervalUnion::Query doesn't 70 // have anything important to clear and LiveRegMatrix's runOnFunction() 71 // does a std::unique_ptr::reset anyways. 72 } 73 } 74 75 template<typename Callable> 76 bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, 77 unsigned PhysReg, Callable Func) { 78 if (VRegInterval.hasSubRanges()) { 79 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 80 unsigned Unit = (*Units).first; 81 unsigned Mask = (*Units).second; 82 for (LiveInterval::subrange_iterator S = VRegInterval.subrange_begin(), 83 SE = VRegInterval.subrange_end(); S != SE; ++S) { 84 if (S->LaneMask & Mask) { 85 if (Func(Unit, *S)) 86 return true; 87 break; 88 } 89 } 90 } 91 } else { 92 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 93 if (Func(*Units, VRegInterval)) 94 return true; 95 } 96 } 97 return false; 98 } 99 100 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { 101 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 102 << " to " << PrintReg(PhysReg, TRI) << ':'); 103 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 104 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 105 MRI->setPhysRegUsed(PhysReg); 106 107 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 108 const LiveRange &Range) { 109 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); 110 Matrix[Unit].unify(VirtReg, Range); 111 return false; 112 }); 113 114 ++NumAssigned; 115 DEBUG(dbgs() << '\n'); 116 } 117 118 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { 119 unsigned PhysReg = VRM->getPhys(VirtReg.reg); 120 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) 121 << " from " << PrintReg(PhysReg, TRI) << ':'); 122 VRM->clearVirt(VirtReg.reg); 123 124 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 125 const LiveRange &Range) { 126 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI)); 127 Matrix[Unit].extract(VirtReg, Range); 128 return false; 129 }); 130 131 ++NumUnassigned; 132 DEBUG(dbgs() << '\n'); 133 } 134 135 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, 136 unsigned PhysReg) { 137 // Check if the cached information is valid. 138 // The same BitVector can be reused for all PhysRegs. 139 // We could cache multiple VirtRegs if it becomes necessary. 140 if (RegMaskVirtReg != VirtReg.reg || RegMaskTag != UserTag) { 141 RegMaskVirtReg = VirtReg.reg; 142 RegMaskTag = UserTag; 143 RegMaskUsable.clear(); 144 LIS->checkRegMaskInterference(VirtReg, RegMaskUsable); 145 } 146 147 // The BitVector is indexed by PhysReg, not register unit. 148 // Regmask interference is more fine grained than regunits. 149 // For example, a Win64 call can clobber %ymm8 yet preserve %xmm8. 150 return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg)); 151 } 152 153 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, 154 unsigned PhysReg) { 155 if (VirtReg.empty()) 156 return false; 157 CoalescerPair CP(VirtReg.reg, PhysReg, *TRI); 158 159 bool Result = foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 160 const LiveRange &Range) { 161 const LiveRange &UnitRange = LIS->getRegUnit(Unit); 162 return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes()); 163 }); 164 return Result; 165 } 166 167 LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg, 168 unsigned RegUnit) { 169 LiveIntervalUnion::Query &Q = Queries[RegUnit]; 170 Q.init(UserTag, &VirtReg, &Matrix[RegUnit]); 171 return Q; 172 } 173 174 LiveRegMatrix::InterferenceKind 175 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { 176 if (VirtReg.empty()) 177 return IK_Free; 178 179 // Regmask interference is the fastest check. 180 if (checkRegMaskInterference(VirtReg, PhysReg)) 181 return IK_RegMask; 182 183 // Check for fixed interference. 184 if (checkRegUnitInterference(VirtReg, PhysReg)) 185 return IK_RegUnit; 186 187 // Check the matrix for virtual register interference. 188 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 189 if (query(VirtReg, *Units).checkInterference()) 190 return IK_VirtReg; 191 192 return IK_Free; 193 } 194