1 //===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The LiveRangeEdit class represents changes done to a virtual register when it 11 // is spilled or split. 12 //===----------------------------------------------------------------------===// 13 14 #include "LiveRangeEdit.h" 15 #include "VirtRegMap.h" 16 #include "llvm/ADT/SetVector.h" 17 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/raw_ostream.h" 22 23 using namespace llvm; 24 25 LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg, 26 LiveIntervals &LIS, 27 VirtRegMap &VRM) { 28 MachineRegisterInfo &MRI = VRM.getRegInfo(); 29 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 30 VRM.grow(); 31 VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg)); 32 LiveInterval &LI = LIS.getOrCreateInterval(VReg); 33 newRegs_.push_back(&LI); 34 return LI; 35 } 36 37 void LiveRangeEdit::scanRemattable(LiveIntervals &lis, 38 const TargetInstrInfo &tii, 39 AliasAnalysis *aa) { 40 for (LiveInterval::vni_iterator I = parent_.vni_begin(), 41 E = parent_.vni_end(); I != E; ++I) { 42 VNInfo *VNI = *I; 43 if (VNI->isUnused()) 44 continue; 45 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def); 46 if (!DefMI) 47 continue; 48 if (tii.isTriviallyReMaterializable(DefMI, aa)) 49 remattable_.insert(VNI); 50 } 51 scannedRemattable_ = true; 52 } 53 54 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis, 55 const TargetInstrInfo &tii, 56 AliasAnalysis *aa) { 57 if (!scannedRemattable_) 58 scanRemattable(lis, tii, aa); 59 return !remattable_.empty(); 60 } 61 62 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 63 /// OrigIdx are also available with the same value at UseIdx. 64 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, 65 SlotIndex OrigIdx, 66 SlotIndex UseIdx, 67 LiveIntervals &lis) { 68 OrigIdx = OrigIdx.getUseIndex(); 69 UseIdx = UseIdx.getUseIndex(); 70 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) { 71 const MachineOperand &MO = OrigMI->getOperand(i); 72 if (!MO.isReg() || !MO.getReg() || MO.getReg() == getReg()) 73 continue; 74 // Reserved registers are OK. 75 if (MO.isUndef() || !lis.hasInterval(MO.getReg())) 76 continue; 77 // We don't want to move any defs. 78 if (MO.isDef()) 79 return false; 80 // We cannot depend on virtual registers in uselessRegs_. 81 if (uselessRegs_) 82 for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui) 83 if ((*uselessRegs_)[ui]->reg == MO.getReg()) 84 return false; 85 86 LiveInterval &li = lis.getInterval(MO.getReg()); 87 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx); 88 if (!OVNI) 89 continue; 90 if (OVNI != li.getVNInfoAt(UseIdx)) 91 return false; 92 } 93 return true; 94 } 95 96 bool LiveRangeEdit::canRematerializeAt(Remat &RM, 97 SlotIndex UseIdx, 98 bool cheapAsAMove, 99 LiveIntervals &lis) { 100 assert(scannedRemattable_ && "Call anyRematerializable first"); 101 102 // Use scanRemattable info. 103 if (!remattable_.count(RM.ParentVNI)) 104 return false; 105 106 // No defining instruction. 107 RM.OrigMI = lis.getInstructionFromIndex(RM.ParentVNI->def); 108 assert(RM.OrigMI && "Defining instruction for remattable value disappeared"); 109 110 // If only cheap remats were requested, bail out early. 111 if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove()) 112 return false; 113 114 // Verify that all used registers are available with the same values. 115 if (!allUsesAvailableAt(RM.OrigMI, RM.ParentVNI->def, UseIdx, lis)) 116 return false; 117 118 return true; 119 } 120 121 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB, 122 MachineBasicBlock::iterator MI, 123 unsigned DestReg, 124 const Remat &RM, 125 LiveIntervals &lis, 126 const TargetInstrInfo &tii, 127 const TargetRegisterInfo &tri) { 128 assert(RM.OrigMI && "Invalid remat"); 129 tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri); 130 rematted_.insert(RM.ParentVNI); 131 return lis.InsertMachineInstrInMaps(--MI).getDefIndex(); 132 } 133 134 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) { 135 if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg)) 136 LIS.removeInterval(Reg); 137 } 138 139 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead, 140 LiveIntervals &LIS, VirtRegMap &VRM, 141 const TargetInstrInfo &TII) { 142 SetVector<LiveInterval*, 143 SmallVector<LiveInterval*, 8>, 144 SmallPtrSet<LiveInterval*, 8> > ToShrink; 145 146 for (;;) { 147 // Erase all dead defs. 148 while (!Dead.empty()) { 149 MachineInstr *MI = Dead.pop_back_val(); 150 assert(MI->allDefsAreDead() && "Def isn't really dead"); 151 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex(); 152 153 // Never delete inline asm. 154 if (MI->isInlineAsm()) { 155 DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI); 156 continue; 157 } 158 159 // Use the same criteria as DeadMachineInstructionElim. 160 bool SawStore = false; 161 if (!MI->isSafeToMove(&TII, 0, SawStore)) { 162 DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI); 163 continue; 164 } 165 166 DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI); 167 168 // Check for live intervals that may shrink 169 for (MachineInstr::mop_iterator MOI = MI->operands_begin(), 170 MOE = MI->operands_end(); MOI != MOE; ++MOI) { 171 if (!MOI->isReg()) 172 continue; 173 unsigned Reg = MOI->getReg(); 174 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 175 continue; 176 LiveInterval &LI = LIS.getInterval(Reg); 177 178 // Shrink read registers. 179 if (MI->readsVirtualRegister(Reg)) 180 ToShrink.insert(&LI); 181 182 // Remove defined value. 183 if (MOI->isDef()) { 184 if (VNInfo *VNI = LI.getVNInfoAt(Idx)) { 185 if (delegate_) 186 delegate_->LRE_WillShrinkVirtReg(LI.reg); 187 LI.removeValNo(VNI); 188 if (LI.empty()) { 189 ToShrink.remove(&LI); 190 eraseVirtReg(Reg, LIS); 191 } 192 } 193 } 194 } 195 196 if (delegate_) 197 delegate_->LRE_WillEraseInstruction(MI); 198 LIS.RemoveMachineInstrFromMaps(MI); 199 MI->eraseFromParent(); 200 } 201 202 if (ToShrink.empty()) 203 break; 204 205 // Shrink just one live interval. Then delete new dead defs. 206 LiveInterval *LI = ToShrink.back(); 207 ToShrink.pop_back(); 208 if (delegate_) 209 delegate_->LRE_WillShrinkVirtReg(LI->reg); 210 if (!LIS.shrinkToUses(LI, &Dead)) 211 continue; 212 213 // LI may have been separated, create new intervals. 214 LI->RenumberValues(LIS); 215 ConnectedVNInfoEqClasses ConEQ(LIS); 216 unsigned NumComp = ConEQ.Classify(LI); 217 if (NumComp <= 1) 218 continue; 219 DEBUG(dbgs() << NumComp << " components: " << *LI << '\n'); 220 SmallVector<LiveInterval*, 8> Dups(1, LI); 221 for (unsigned i = 1; i != NumComp; ++i) 222 Dups.push_back(&createFrom(LI->reg, LIS, VRM)); 223 ConEQ.Distribute(&Dups[0], VRM.getRegInfo()); 224 } 225 } 226 227